JPS61127043A - Data processor - Google Patents

Abstract

PURPOSE:To attain the accurate interruption of execution of a program by comparing the prescribed setting conditions with the signal on an internal bus and producing the control signal corresponding to the setting conditions according to the output signal of said comparison. CONSTITUTION:The internal address, internal data and internal control buses 12-14 are connected to a microprocessor part 11 consisting of a control part and an executing unit. Then break condition setting data registers 16a-16c and a control register 17 are connected to the buses 12 and 13 respectively. The data of registers 16a-16c are applied to the reference input side terminals of comparators 18a-18c. While the signals of buses 12-14 are applied to the comparison input side terminals respectively. The output of comparators 18a-18c are supplied to gate circuits 19a-19c which are controlled by the output of the register 17. Then output signals of those comparators are also supplied to a signalproducing circuit 21 via an OR gate circuit 20. The produced interruption signal IQ is supplied to the processor part 11.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to data processing technology, and relates to a technology that is effective when used, for example, in an emulator that emulates a microprocessor or a system development device that incorporates such a function. .

[Background Art] Software development and debugging of a microcomputer system developed by a user is sometimes performed using a device as shown in FIG. That is,
An IC socket 2 for a microprocessor (hereinafter referred to as MPU) provided on a board la constituting a microcomputer system (user system) 1,
The same MPU as the system 1 MPU via connector 3
An adaptive system emulator (hereinafter referred to as ASE) 4 having a built-in system is connected thereto. This ASE4 is
CRT display device 5 and floppy disk device 6a via cable CA.

6b, etc., is connected to a system development device 7 called a support tool.

In the above system, a source program written in a language such as an assembler or a compiler that is input from the keyboard of the CRT display device 5 is first written to a floppy disk 6a, and then written to an MP in the system development device 7.
The program is translated into machine language by U (not shown) and written to the floppy disk 6b in the form of an object program.

The program written on the floppy disk 6b is
The MPU in ASEA transfers the data to a RAM (random access memory) 8 or the like in the user system 1 and writes it.

The user program written to RAM8 etc. is
When the connector 3 is pulled out from the C socket 2 and the MPU 9 of the system is inserted in its place, the process is executed by this MPU 9. In the system shown in FIG. 2, the user program can be debugged while being emulated by the MPU (same type as MPU 9) in ASE4.

In this case, the CRT display 5, floppy disk devices 6a, 6b, etc. are controlled.

There is a host MPU in the system development device 7 that translates assembler and compiler languages into machine language, and also edits data obtained by executing user programs using the MPU in the ASE4 and displays it on the CRT display 5. It's set in nine.

The emulator can be provided with a function that allows the MPU in the system development device 7 to process data obtained as a result of emulation in a form that is easy to edit. In the above system, the MPU in ASEJ serves both emulation and data processing functions. Therefore, the MPU in ASEJ is spatially divided into emulation mode and system mode for execution based on control signals output from the controller in system development device E7.

When debugging a user program using the above emulator system, the program is generally cut into pieces and emulated. is detected and the execution of the program is interrupted at that point.

According to the above break method, for example, if the signals on the address bus are monitored and the program is broken (interrupted) when the address, etc. matches a predetermined condition, the program will be executed as soon as the break condition is met. will be stopped. The state of the system immediately before the break is captured in real time into a storage device that stores data on the bus called a trace memory. This makes it possible to analyze the contents of the trace memory after a break to determine the cause of the program's runaway, and to debug the user program or system.

An emulator system having the above configuration is disclosed in, for example, Japanese Patent Application No. 58-34565.

By the way, conventional microprocessors are not designed to have auxiliary functions for emulation as described above. Therefore, when configuring an emulation system such as a system development device, it is necessary to set break conditions. External circuits must be configured with registers, a comparison circuit to detect when a breakpoint has been passed, or a circuit that generates a signal such as an interrupt signal that stops the microprocessor when a breakpoint is passed. Ta.

Therefore, it has been found that such an external device has the disadvantage that, due to the delay time in the circuit, the microprocessor starts the next instruction cycle as soon as the break condition is satisfied, even if the program is intended to be stopped.

Furthermore, recent microprocessors have become increasingly sophisticated. For example, some devices have a so-called briefetch function in which several instructions to be executed next are fetched into internal registers in advance using vacant bus cycles. In such a microprocessor, simply monitoring signals on the external address bus and data bus does not allow the user to check whether those signals correspond to the currently executing instruction or whether they correspond to the prefetched instruction. I can't identify what it is. As a result, it becomes increasingly difficult to stop the program at a desired breakpoint.

[Object of the Invention] The object of the invention is to provide a data processing technology that can accurately and quickly interrupt program execution or start an external device under desired conditions when emulating a microprocessor. Our goal is to provide the following.

The above and other objects and novel features of the present invention will become clear from the description of the present specification and the accompanying drawings.

[Summary of the Invention] A summary of typical inventions disclosed in this article is as follows.

In other words, on the semiconductor chip on which the microprocessor is formed, a register in which a stop or start condition is set is compared with its control register, and the set condition is compared with a signal on an internal bus, and when they match, for example, a program is By providing a circuit that generates an interrupt signal that interrupts the execution of the program or a control signal such as a start signal to the outside, it is possible to interrupt the execution of the program under desired conditions during emulation without installing any external circuit. This allows the external device to quickly interrupt the program with shorter delay times than when such a signal is generated in the circuit. or activate a desired device.

In addition, by decoding control signals inside a microprocessor and determining whether or not to effectively generate control signals such as interrupt signals based on the decoded signals, it is possible to improve the functionality of microprocessors as they become more sophisticated. Even if instructions or data different from those originally executed by the microprocessor appear on the bus, interrupt signals etc. will not be generated due to the instructions or data that are originally executed by the microprocessor. This allows it to be activated.

[Embodiment 1] FIG. 1 shows an embodiment in which the present invention is applied to a microprocessor. Each circuit portion surrounded by a chain line A in the figure is formed on a single semiconductor substrate (chip) made of single crystal silicon.

In the figure, reference numeral 11 denotes a microprocessor section consisting of, for example, a control section and an execution unit. An interrupt control circuit 11a for interrupting the execution of the program by 11 is provided.

An internal address bus 12, an internal data bus 13, and an internal control bus 14 are connected to the microprocessor section 11.

In this embodiment, a break condition setting data register 16a connected to the internal data bus 13 is
, 16b, 16c, and a control register 17 for determining their usage status. Each of the above registers 16a.

16b, 16c and 17 are the microprocessor unit 1;
1 by a predetermined address signal supplied via the internal address bus 12.

Data can be read and written.

The data set in the data registers 15a, 15b, and 16c are supplied to reference input terminals of multi-bit comparators 18a, 18b, and 18c, respectively. On the other hand, each signal on the internal bus 13, internal control bus 14, and internal address bus 12 is applied to the comparison input side terminals of the comparators L8a, 18b, and 18c.

The output signals of the comparators 18a, 18b, 18c are supplied to gate circuits 19a, 19b, 19c controlled by the output of the control register 17, respectively. Further, the output signals of the comparators that have passed through these gate circuits 19a to 19c are supplied to a signal forming circuit 21 via an OR gate circuit 20.

Each of the above data registers 16a, 16b,
Break conditions can be set in I6C corresponding to each of the data signal, control signal, and address signal on the bus. control register 17
For example, each bit of the control register 17 is set to "1". And that “1
'' is enabled, and when the bit is set to "0", the break condition of the corresponding data register is disabled.

That is, depending on the states of three bits corresponding to data registers 16a to 16c of control register 17, gate circuits 19a to 19c are respectively opened or closed. When the gate circuits 19a to 19c are in the open state, the corresponding comparators 18a to 18
When the output signal of c is supplied to the signal forming circuit 21 via the OR gate circuit 20 and is in the closed state, the output of the comparator is not supplied to the signal forming circuit 21.

Therefore, in this embodiment, data registers 16a-1
By appropriately setting the contents of control register 6c and control register 17, when any one of the signals applied to internal buses 12 to 14 matches a predetermined condition,
A match output signal is generated from any one of comparators 8a-8c.

This allows the signal forming circuit 21 to operate.

The signal forming circuit 21 is, for example, as shown in FIG. A control signal IQ is formed and outputted to the control circuit 11a. Although not particularly limited, in this embodiment, the control signal IQ formed by the signal forming circuit 21 is also output to the outside from the external terminal 22.

Furthermore, in this embodiment, a counter 23 for counting the comparator 18a to 18c(7)-number specific force signal that has passed through the OR gate circuit 20, and a count value setting register for setting the count value of this counter 23 are provided. 24 are provided. Corresponding to this counter 23, a bit is provided in the control register 17 to indicate whether the output of this counter 23 is enabled or disabled.

When the bit corresponding to the counter 23 in the control register 17 is set to "1", for example, the output of that bit opens the AND gate circuit G1 in the signal forming circuit 21 and closes the AND gate circuit G2. Therefore,
Comparator 18a.

The coincidence output signals of 18b and 18c are output as they are through the OR gate circuit G4, and are supplied to the microprocessor section 11 as an interrupt signal IQ.

On the other hand, if the bit corresponding to counter 23 in control register 17 is set to "0", AND gate circuit G1 in signal forming circuit 21 is closed and gate circuit 62 is opened instead. Therefore, the comparators 18a~
The coincidence output signal of 18c is not passed, allowing the output of counter 23 to pass through gate G2. Since the counter 23 is configured to count the coincidence output signals output from the comparators 18a to 18c, the coincidence output signals of the comparators 18a to 18c are counted by the register 23.
When a predetermined number of signals are output, the output of the counter 23 changes and the signal forming circuit 2
1, the interrupt signal IQ is output.

Next, a description will be given of the operation when the microprocessor configured as described above is installed as the emulation MPU10 in a system development apparatus as shown in FIG. 2 and a user program is debugged.

When debugging, the program is divided and emulation is performed.

Therefore, it is necessary to set conditions (breakpoints) to interrupt the program.

According to the microprocessor of this embodiment, a signal output from the microprocessor section 11 onto the internal address bus 12, a signal output onto the internal data bus 13, or a signal output from the internal control bus 1 is used as a breakpoint.
4 can be set as the target.

In that case, before executing the user program by emulation, the host MP in the system development device 7
In response to a command from U, the emulation microprocessor (1o) sets the breakpoint given from the keyboard or the like in the data registers 16a to 16b in the microprocessor 10, and also sets which register is valid. Information indicating whether to do so is set in the control register 17.

Also, if a loop in the user program you are trying to debug contains a bug.

After going through the loop dozens or even hundreds of times, you may break out of the loop and the program jumps somewhere else. If you want to find such a bug, set an appropriate count value to the counter value setting register 24 in the microprocessor unit 1 before starting emulation.
Set by 1.

The microprocessor (10) then starts emulation by commands from the host MPU.

At the same time, the signals appearing on the external bus of the emulation microprocessor (10) are captured one after another into a trace memory (not shown) until the emulation microprocessor (10) is stopped at a breakpoint (break condition), and then the host MPU Bugs can be easily discovered by displaying the data captured in the trace memory on the screen of the CRT display device 5 in response to a command from.

In the above case, when the break condition is met, the operation of the microprocessor unit 11 is stopped by the interrupt signal output from the signal forming circuit 21, and the emulation microprocessor (10) starts executing the reuser program. will be stopped. In this state, in order to exchange data with the host MPU side, for example, jump to a predetermined interrupt routine based on an interrupt signal, or output data from the signal forming circuit 21 to the external terminal 22. Based on the signal IQ, the memory in which the user program is stored and the memory in which the program on the system development device side is stored are switched, and when the user program is interrupted, the next step is to switch the memory in accordance with the system development program. Uration microprocessor (10)
make it work. As a result, the emulation microprocessor is operated in a spatially divided manner between the emulation mode and the system mode.

Note that in the above embodiment, the case where program execution is interrupted when a predetermined condition is met was explained, but in emulation, it is possible to observe the waveform of a signal on the bus or start tracing from the middle of program execution. There are cases like this.

If you want the microprocessor to have such a function, for example, in the above embodiment, the control register 17 is provided with a bit indicating whether to set a break condition or a trigger condition. The output of the bit is supplied to the signal forming circuit 21, so that when the coincidence output signals of the comparators 18a to 18c are outputted, a control signal indicating that the condition is satisfied is outputted only to the external terminal 22. Then, a control signal outputted to the external terminal 22 may be used to start a synchroscope to start observing a waveform, or to start a tracing memory to start tracing.

In that case, the data registers 16a to 16c may be configured so that either a break condition or a trigger condition can be selectively set, or a register that sets a break condition and its comparator may be used to set a trigger condition. The register to be set and its comparator may be provided separately.

According to the above embodiment, a circuit detects whether a predetermined condition is satisfied during emulation, and when one condition is satisfied,
Since the circuits that form signals to interrupt programs or start desired devices are installed on the same chip as the microprocessor, external circuits require less delay time than if such circuits were constructed using circuits. becomes very short. Therefore.

Immediately after a condition is met, program execution can be interrupted or a desired device can be activated, allowing debugging work to be performed quickly and accurately.

In addition, recent microprocessors are highly functional as described above, and have a briefetch function and a pipeline processing function. Therefore, it is not possible to distinguish whether an instruction is currently being executed or not just by looking at external signals. However, even in such a case, it is possible to distinguish by looking at the control signals within the microprocessor section 11, but such control signals are usually not output to the outside of the microprocessor.
Additionally, a large number of external terminals (pins) are required for output.

However, according to the present invention, for example, in the above embodiment, a decoder is provided for decoding appropriate several control signals outputted from the control section in the microprocessor section 11, and the signal forming circuit 21 is formed by the decoded signals. By controlling whether or not to input the interrupt signal to the microprocessor section 11, it is possible to easily distinguish whether or not the instruction is currently being executed, and to accurately interrupt the instruction.

First, an embodiment of a circuit that detects the establishment of an accurate break condition based on an appropriate control signal in the microprocessor section 11 and generates an interrupt to the microprocessor will be described.

[Example 2 FIG. 3 is a block diagram of the second embodiment.

In the figure, 29 is a decoder that decodes the control signal output from the microprocessor section 11;
0 is an instruction queue that stores n prefetched instructions and addresses corresponding to the instructions. Instructions and addresses are loaded into this queue each time an instruction is fetched and sequentially shifted to the right. The rightmost instruction is the instruction currently being executed. This configuration allows n instructions to be prefetched.

According to the illustrated configuration, data in the instruction queue immediately before the instruction being executed is used as reference input to the comparators 18a to 18c. Whether or not to enable the output results of the comparators 18a to 18c is determined by an internal control signal output from the decoder 29 in addition to the control register signal. This control signal specifies the address at which the break is applied or the timing immediately before the opcode is actually executed.

This allows the program to be interrupted accurately.

In the above embodiment, the present invention is applied to a microprocessor, but it can also be applied to a single-chip microcomputer.

In that case, the internal buses 12 to 14 in the above embodiment
The configuration is such that a ROM (read only memory), a RAM (random access memory), an I10 board, etc. are connected between them.

[Effects (1) On the chip in which the microprocessor is formed, a register that sets the stop or start condition, a control register that determines its usage status, and a signal on the internal bus are compared with the set condition and the signal on the internal bus is matched. For example, a circuit is provided to generate a control signal such as an interrupt signal or a start signal that interrupts program execution when By being able to generate a signal to interrupt or operate an external device, external devices can quickly interrupt a program with shorter delay times than when such a signal is generated in the circuit. This has the effect that a desired device can be activated.

(2) On the chip on which the microprocessor is formed, there are registers that set stop or start conditions and control registers that determine their usage status.

A circuit is provided that compares the set conditions and the signals on the internal bus, and when they match, generates a control signal such as an interrupt signal that interrupts program execution, and also decodes the control signals inside the microprocessor. The decoded signal then determines whether or not to effectively generate a control signal such as an interrupt signal, so as the microprocessor becomes more sophisticated, the instructions that the microprocessor originally executes are An effect that prevents interrupt signals from being generated even if different instructions or data appear on the bus, making it possible to always interrupt program execution or start an external device at a precise location. There is.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, when one of the address signal, data signal, or control signal matches a set condition as a break condition, an interrupt is generated to the microprocessor section. It is also possible to adopt a configuration in which an interrupt signal is not generated unless at least two of these signals match.

Further, in the above embodiment, when the break condition is met, an appropriate control signal is outputted from the external terminal 22 to the outside, but a configuration in which the output to the outside is omitted may also be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the case where the present invention is applied to a microprocessor, and FIG. 2 is a block diagram showing an example of the overall configuration of a system development device to which the microprocessor according to the present invention is applied. FIG. 3 is a block diagram of another embodiment. ■...User system, 2...IC socket, 3...Connector, 4...ASE (Adaptive System Evaluator), 5...CR
T display, 6a, 6b...floppy disk device, 7...system development device, 8...RA
M, 9...MPU (microprocessor), 10.
...MPU for emulation, ll...Microprocessor section, 12...Internal address bus, 13
...Internal data bus, 14...Internal control bus, 16a, 16b, 16c...Data register, 17...Control register, 18a,
18b, 18c... Comparison means (comparator), 1
9a, 19b, 19c...gate circuit, 21...
・Signal forming circuit, 23...Counter, 24...
Count value setting register, 25... external address terminal, 26... external data terminal, 27... external interrupt input terminal. 28...Control terminal, 30...Instruction cue.

Claims (1)

[Claims] 1. A microprocessor section consisting of a control section and an execution unit, a setting means capable of setting a predetermined condition, and a comparison for comparing the conditions set in the setting means and a signal on an internal bus. 1. A data processing device comprising: a signal forming means for forming a control signal corresponding to the setting condition based on a signal output from the comparing means. 2. The setting means is capable of setting a stop condition for interrupting the execution of the program by the microprocessor section, and the signal forming means sends the signal to the microprocessor when the setting condition matches the signal on the internal bus. 2. The data processing apparatus according to claim 1, wherein an interrupt control signal is generated for the data processing section. 3. The setting means includes a plurality of registers in which stop conditions and/or start conditions can be set for each type of signal on the bus to be compared, and a register that determines the usage status of these registers. A data processing device according to claim 1 or 2, characterized in that: 4. The comparison means includes a counting means for counting the number of times the condition set in the setting means matches the signal on the internal bus, and operates the signal forming means when the number of matches reaches a predetermined number. 3. A data processing device according to claim 1, 2, or 3, characterized in that the data processing device is configured to perform the following operations. 5. A patent characterized in that the microprocessor section has a decoder that decodes an appropriate control signal inside the microprocessor section, and the decoded signal of the decoder controls the formation or output of the signal in the signal forming means. A data processing device according to claim 1, 2, 3, or 4.