JPS61126617U - - Google Patents
Info
- Publication number
- JPS61126617U JPS61126617U JP866185U JP866185U JPS61126617U JP S61126617 U JPS61126617 U JP S61126617U JP 866185 U JP866185 U JP 866185U JP 866185 U JP866185 U JP 866185U JP S61126617 U JPS61126617 U JP S61126617U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- capacitor
- resistance value
- terminal
- gate terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Junction Field-Effect Transistors (AREA)
Description
第１図は本考案によるＦＥＴのバイアス回路の
一実施例の構成を示す回路図、第２図は従来のＦ
ＥＴのバイアス回路の構成を示す回路図である。
１……ＦＥＴ、２……ゲート端子、３……ドレ
イン端子、４……ソース端子、５……ＲＦ入力端
子、６……ＲＦ出力端子、７……負電圧端子、８
……正電圧端子、９，１０……抵抗器、１１，２
１，２２……コンデンサ。
FIG. 1 is a circuit diagram showing the configuration of an embodiment of an FET bias circuit according to the present invention, and FIG.
FIG. 2 is a circuit diagram showing the configuration of a bias circuit of ET. 1...FET, 2...Gate terminal, 3...Drain terminal, 4...Source terminal, 5...RF input terminal, 6...RF output terminal, 7...Negative voltage terminal, 8
...Positive voltage terminal, 9,10...Resistor, 11,2
1, 22... Capacitor.
Claims (1)
印加し、負電圧供給端子と接地間に抵抗値Ｒ１の
第１の抵抗器と抵抗値Ｒ２の第２の抵抗器を直列
に接続して前記第１と第２の抵抗器の接続点とゲ
ート端子を接続することにより該ゲート端子に負
電圧を印加して、デプレツシヨン型電界効果トラ
ンジスタを動作させるバイアス回路において、前
記第１の抵抗器と並列に容量値Ｃ１の第１のコン
デンサを接続し、前記第２の抵抗器と並列に容量
値Ｃ２の第２のコンデンサを接続し、前記第１の
抵抗器の抵抗値Ｒ１と前記第２の抵抗器の抵抗値
Ｒ２との比Ｒ１／Ｒ２と、前記第１のコンデンサ
の容量リアクタンス（１ＷＣ１）と前記第２のコ
ンデンサの容量リアクタンス（１ＷＣ２）との比
Ｃ２／Ｃ１を等しくしたことを特徴とする電界効
果トランジスタのバイアス回路。 The source terminal is grounded, a positive voltage is applied to the drain terminal, and a first resistor with a resistance value of R1 and a second resistor with a resistance value of R2 are connected in series between the negative voltage supply terminal and the ground. In a bias circuit for operating a depletion field effect transistor by connecting a connection point between the first and second resistors and a gate terminal to apply a negative voltage to the gate terminal, the first resistor and the gate terminal are connected to each other. A first capacitor with a capacitance value C 1 is connected in parallel, a second capacitor with a capacitance value C 2 is connected in parallel with the second resistor, and the resistance value R 1 of the first resistor and the The ratio R 1 /R 2 of the resistance value R 2 of the second resistor and the ratio C 2 of the capacitive reactance (1WC 1 ) of the first capacitor to the capacitive reactance (1WC 2 ) of the second capacitor A bias circuit for a field effect transistor, characterized in that / C1 is made equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP866185U JPS61126617U (en) | 1985-01-26 | 1985-01-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP866185U JPS61126617U (en) | 1985-01-26 | 1985-01-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61126617U true JPS61126617U (en) | 1986-08-08 |
Family
ID=30488154
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP866185U Pending JPS61126617U (en) | 1985-01-26 | 1985-01-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61126617U (en) |
-
1985
- 1985-01-26 JP JP866185U patent/JPS61126617U/ja active Pending
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