JPS61125602A - Digital-type adjuster - Google Patents

Digital-type adjuster

Info

Publication number
JPS61125602A
JPS61125602A JP24740984A JP24740984A JPS61125602A JP S61125602 A JPS61125602 A JP S61125602A JP 24740984 A JP24740984 A JP 24740984A JP 24740984 A JP24740984 A JP 24740984A JP S61125602 A JPS61125602 A JP S61125602A
Authority
JP
Japan
Prior art keywords
pid
digital
integral
standby
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24740984A
Other languages
Japanese (ja)
Inventor
Yoshitaka Ikeda
池田 嘉隆
Noriaki Tominaga
憲明 富永
Yasuyuki Yamane
山根 康幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP24740984A priority Critical patent/JPS61125602A/en
Publication of JPS61125602A publication Critical patent/JPS61125602A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B7/00Arrangements for obtaining smooth engagement or disengagement of automatic control
    • G05B7/02Arrangements for obtaining smooth engagement or disengagement of automatic control electric

Abstract

PURPOSE:To avoid an excessive change in a control signal supplied to a controlled system even if an output is switched from a digital type adjuster at the operating side to that at the standby side. CONSTITUTION:A switching signal S3 from a monitor 7 discriminates the PID adjuster at the operating side 11 and that at the standby side 12. The PID arithmetic based on equations 1-4 is executed in said adjuster 11, and a signal S5 is supplied to the controlled system 4. A control amount X is detected by a detector 3 and fed back to said adjusters 11 and 12. The PID adjuster at the operating side 12 estimates the integral arithmetic result of the PID adjuster at the operating side 12 according to equation 5, and the PID arithmetic is executed based on equations 6-9 with the estimated value as an integral initial value. After the prescribed time expires, the integral arithmetic result of the PID adjuster at the operating side 11 is again estimated, and the PID arithmetic is executed with the estimated value as an integral arithmetic value. After wards said sequence is interacted by the prescribed interval. Thus outputs of both PID adjusters go to approximately the same values.

Description

【発明の詳細な説明】 ・;産業上の利用分野) 本発明は、積分勤1γを含む複数のディジタル型[i器
により多重冗長系を構成するディジタル型調節装置の改
良に関する。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an improvement in a digital adjustment device that configures a multiple redundant system by a plurality of digital controllers including an integral factor 1γ.

〔従来の技術〕[Conventional technology]

近年、積分動作を含む11節器の分野にもディジタル化
が進んでおり、マイコンあるいはミニコンと呼ばれる小
型コンピュータを用いたディジタル型PID調節器が開
発され実用に供されている。
In recent years, digitization has progressed in the field of 11-node controllers including integral operations, and digital PID controllers using small computers called microcomputers or minicomputers have been developed and put into practical use.

一般に、上記ディジタル型PID[l器は多重冗長系を
構成することにより、その信頼性を高めている。
Generally, the reliability of the digital PID device is increased by constructing a multiple redundant system.

第2図は2台のディジタル型PIO!1節器を用いて二
重冗長系を構成した従来のディジタルIPID調節装置
を示すブロック図である。例えばマイコンにより構成さ
れた稼動11PIDli節器1および待機側PID!1
節器2は、検出器3により検出される制御対象4に対す
る制御量Xの検出llX1と、端子5から供給される前
記制tl]IXの設定tiix2とを入力し、これらの
II all偏差をPID演算により求めるものとなっ
ている。上記両PID調節器1.2のエカは、切換スイ
ッチ6により選択された方が前記111111対象4に
供給されるものとなっている。また上記両PID調節器
1.2の入出力信号は監視器7に与えられる。そして上
記監視器7により前記両調節器1.2の正常、異常が判
断され、両PfD調節器1.2が正常の場合にはプライ
オリティの高い稼動側PID!11節器1が選択され、
一方が異常の場合には正常なPID!m1節器が選択さ
れるような切換制御信号が前記切換スイッチ6に送出さ
れると共に、警報器(不図示)に警報信号が発せられ、
オペレータに対して調節器の異常が知らされるものとな
っている。
Figure 2 shows two digital PIOs! FIG. 2 is a block diagram showing a conventional digital IPID adjustment device that uses a single node to configure a double redundant system. For example, the operating 11 PID controller 1 and the standby PID are configured by a microcomputer! 1
The moderator 2 inputs the detection 11X1 of the control amount It is determined by calculation. The power of both PID regulators 1.2 is such that the one selected by the changeover switch 6 is supplied to the 111111 target 4. Further, the input and output signals of both PID controllers 1 and 2 are provided to a monitor 7. Then, the monitor 7 determines whether both the regulators 1.2 are normal or abnormal, and if both the PfD regulators 1.2 are normal, the operating side PID with high priority! 11 verse 1 is selected,
If one is abnormal, it is a normal PID! A switching control signal for selecting the m1 moderator is sent to the changeover switch 6, and an alarm signal is issued to an alarm (not shown),
The operator is notified of any abnormalities in the controller.

このようにPID!1ID21節器用いて二重冗長系を
構成すると共に、前記検出器4.切換スイッチ6および
監視器7を設け、上記両PID!1節器1.2の単一使
用時に比べ格段と信頼性が高くなるように構成すること
により、高信頼性のディジタル型PID制[装置を得る
ことができる。
Like this PID! A double redundant system is constructed using 1 ID and 21 nodes, and the detector 4. A changeover switch 6 and a monitor 7 are provided, and both of the above PID! A highly reliable digital PID system can be obtained by configuring the system so that the reliability is much higher than when the single section unit 1.2 is used alone.

(発明が解決しようとする問題点) しかるに、前述したように積分演算を含む複数のディジ
タル型調節器を用いて多重冗長系を構成する場合、各デ
ィジタル型調節器にて演算される制御偏差が異なる値に
なると、調節器の出力が積分演算のために最大または最
小に振切れてしまうことがある。すなわち、時刻tにて
稼動側PIDX1節器1により求めた制御偏差e1 (
t>と待機側PID調節器2により求めた制御偏差e2
 (t)とが、雑音の影響やデータ取込みタイミングの
ずれ等により異なることがある。そうすると、Ill 
IIIループに含まれている稼動側PID11節器1の
制御I幅偏差t(t)は最終的に零となるが、lll1
11ループに含まれていない待機側PID調節器2の制
御偏差e2 (t)は零にならない。そのため、上記待
機側PID調節器2では制御偏差e2 (t)を何回も
積分することになり、ついには出力が最大値あるいは最
小値に振切れてしまうことになる。
(Problem to be Solved by the Invention) However, as described above, when a multiple redundant system is constructed using a plurality of digital regulators including integral calculations, the control deviation calculated by each digital regulator is If the values are different, the output of the regulator may swing out to the maximum or minimum due to the integral operation. That is, the control deviation e1 (
t> and the control deviation e2 determined by the standby PID controller 2
(t) may differ due to the influence of noise, a shift in data acquisition timing, etc. Then, Ill
The control I width deviation t(t) of the operating side PID11 node 1 included in the III loop eventually becomes zero, but lll1
The control deviation e2 (t) of the standby side PID controller 2 that is not included in the loop No. 11 does not become zero. Therefore, the standby PID controller 2 integrates the control deviation e2 (t) many times, and the output eventually reaches the maximum or minimum value.

この状態で前記稼動側PIDKllli!1に異常が発
生すると、監視器7により切換スイッチ6が切換えられ
待機側PID調節器2がIII ’taループに含まれ
るので、制御対象3に供給される制御信号は過大変化す
る。したがって上記制御対象3に対する@III xが
大きく変動し、安定したall(Illが行なえなくな
るという問題が生じていた。
In this state, the operating side PIDKlli! When an abnormality occurs in the controller 1, the changeover switch 6 is switched by the monitor 7 and the standby PID controller 2 is included in the III'ta loop, so the control signal supplied to the controlled object 3 changes excessively. Therefore, @III x for the controlled object 3 fluctuates greatly, causing a problem that stable all (Ill) cannot be performed.

そこで本発明は、たとえ稼動側ディジタル型調節器に異
常が発生し待傭側ディジタル型調節器に切換えられても
制御対象に供給される制御信号は過大変化せず、制御対
象に対する制御量が大きく変動するおそれもなく、常に
安定した制御が可能なディジタル型調節装置を提供する
ことを目的としている。
Therefore, in the present invention, even if an abnormality occurs in the active digital controller and it is switched to the standby digital controller, the control signal supplied to the controlled object will not change excessively, and the control amount for the controlled object will be large. It is an object of the present invention to provide a digital adjustment device that can always perform stable control without fear of fluctuation.

(問題点を解決するための手段〕 本発明は上記問題点を解決し目的を達成するために次の
ような手段を講じたことを特徴としている。すなわち、
制御ループに含まれ積分演算を行なう稼動側ディジタル
型調節器の積分演算結果を少なくとも一つの待機側ディ
ジタル型調節器により推定し、この推定された積分演算
結果を初期値として積分演算を行なうと共に、前記稼動
側ディジタル型11節器および待機側ディジタル型調節
器の動作状態を監視器により監視し、上記稼動側ディジ
タル型調節器に異常が生じた場合には前記待灘測ディジ
タル型調節器を一11111ループに含ませるように切
換手段により調節器出力を切換えるようにしたことを特
徴としている。
(Means for Solving the Problems) The present invention is characterized by taking the following measures to solve the above problems and achieve the objectives.
Estimating the integral calculation result of the active digital controller included in the control loop and performing the integral calculation by at least one standby digital controller, and performing the integral calculation using the estimated integral calculation result as an initial value, The operating status of the digital 11-section controller on the operating side and the digital controller on the standby side is monitored by a monitor, and if an abnormality occurs in the digital regulator on the operating side, the digital controller on the standby side is immediately replaced. It is characterized in that the regulator output is switched by a switching means so as to be included in the 11111 loop.

〔作用〕[Effect]

このような手段を講じたことにより、常に待機側ディジ
タル型調節器の出力が稼動側ディジタル型調節器の出力
とほぼ等しい値になるので、稼動側ディジタル型調節器
から侍礪側ディジタル型調節器に出力が切換わっでも制
御対象に供給される制御信号に過大変化は生じない。
By taking such measures, the output of the standby digital controller is always approximately equal to the output of the active digital controller, so that the output from the active digital controller to the standby digital controller is Even if the output is switched to , no excessive change will occur in the control signal supplied to the controlled object.

〔実施例〕 第1図は本発明の一実施例として二重冗長方式のディジ
タル型PID調節装置の構成を示すブロック図である。
[Embodiment] FIG. 1 is a block diagram showing the configuration of a double redundant type digital PID adjustment device as an embodiment of the present invention.

なお第2図と同一部分には同一符号を付し、詳しい説明
は省略する。本実施例においては、マイコンにより構成
される稼動側PIDv4節器11と待機IIIIPID
調節器12とに、llj器4における検出11X1を示
すフィードバック信号S1.端子5から供給される設定
値×2を示す設定置信号S2の他に、監視器7から出力
される切換制御信号S3が入力されるものとなっている
Note that the same parts as in FIG. 2 are given the same reference numerals, and detailed explanations will be omitted. In this embodiment, an active side PIDv4 moderator 11 and a standby IIIPID configured by a microcomputer are used.
The regulator 12 receives a feedback signal S1 . In addition to the setting signal S2 indicating the set value x2 supplied from the terminal 5, a switching control signal S3 outputted from the monitor 7 is input.

また稼動側PIDJiij器11には侍礪側PID制御
fi12の出力信号S4が入力され、待1111111
1PIO51!ii器12に:1.tlllllP I
 Din器11の出力信号S5が入力されるものとなっ
ている。上記稼動側PID!11節器11ではディジタ
ル型PID演算が1テなわれ、待機側PID調節器12
では所定時間間隔毎に稼動1[IPio調節器11にお
ける積分演I[結果を推定し、積分演算の初期値を上記
推定された積分演算結果の値に変更した後、ディジタル
型PID演算を行なうものとなっている。
In addition, the output signal S4 of the samurai side PID control fi12 is input to the working side PID controller 11, and the waiting 1111111
1PIO51! ii to vessel 12: 1. tllllllP I
The output signal S5 of the Din device 11 is input. The above operating side PID! In the 11-section unit 11, one digital type PID calculation is performed, and the standby side PID controller 12
Then, at predetermined time intervals, the operation 1 [integral operation I in the IPio controller 11] is estimated, the initial value of the integral operation is changed to the value of the estimated integral operation result, and then the digital PID operation is performed. It becomes.

上記稼動IIIPID調節器11におけるディジタル型
PID演稗は、調節器出力をU、積分演算結果をS、微
分演算結果をり、制@偏差をeとすると Un −kp  (en +SA +DA )    
 −(1)Sa −(T/T+  )Σe i    
     −(2)On = (To、/T)<en 
−en−s  )   ・13)e、q  −X 2n
  −X IrL・14)なる式に基いて行なわれる。
The digital PID operation in the operating III PID regulator 11 is as follows: Un -kp (en +SA +DA) where the regulator output is U, the integral operation result is S, the differential operation result is R, and the control@deviation is e.
−(1)Sa −(T/T+)Σe i
−(2)On = (To, /T)<en
-en-s) ・13)e, q -X 2n
-X IrL·14).

なお上記各式において、kPはゲイン、Tはサンプリン
グ周期、T+は積分時間、Toは微分時間、nはnサン
プリング時点での値を示している。
In each of the above equations, kP is the gain, T is the sampling period, T+ is the integration time, To is the differentiation time, and n is the value at n sampling times.

ここで上記(1)式と(3式により Sn = (1/kp )Lln + (To/T)e
a−+[(T+To )/T] ea    −(5)
が得られる。したがって待機側PID調節器12におい
て、稼動側PID!II節器11から取り込まれる出力
Uと待機側PID調節器12にて演算されたl1III
l偏差eとを用いて上記(5)式に示す演算を行なうこ
とにより、稼動111PIDE1節器11における積分
演算結果が推定されるので、この推定された積分演算結
果を積分初期値として新たなPID演褌演算なわれる。
Here, according to the above formula (1) and (3), Sn = (1/kp)Lln + (To/T)e
a-+[(T+To)/T]ea-(5)
is obtained. Therefore, in the standby side PID controller 12, the active side PID! The output U taken in from the II node 11 and l1III calculated by the standby side PID controller 12
By performing the calculation shown in equation (5) above using The calculation is done.

すなわち、nサンプリング時点で持11111PID調
節1612が稼動側PID調節器11の積分演算結果S
Aを推定したとすると、(n+1)サンプリング時点以
後の待機側PID調節器12におけるPID演算は Uwps−kp (ewM+swM+Dwm)=・(0
5wM−8a  +  (T/T+  )  とe w
 +    □17)Ilシn Dwy−(To/T)(ewM−eWA−t )・・・
a ews−X2M−X 1wM          −(
9)なる1式に基いて行なわれる。なお上記各式におい
てWは侍曙側であることを示し、Mは(n+1)以上ノ
サンプリング時点を示している。
That is, at the time of n sampling, the PID adjustment 1612 is the integral calculation result S of the operating side PID controller 11.
Assuming that A is estimated, the PID calculation in the standby PID controller 12 after the (n+1) sampling time is Uwps-kp (ewM+swM+Dwm)=・(0
5wM-8a + (T/T+) and e w
+ □17) Ilshin Dwy-(To/T) (ewM-eWA-t)...
a ews-X2M-X 1wM-(
9). Note that in each of the above equations, W indicates the Samurai Akebono side, and M indicates the sampling point of (n+1) or more.

このように構成された本実m例においては、監視器7か
らの切換制御信号s3により稼動側PID調節器11と
11j機開PID!1節器12とが判別される。そして
稼動側PIDI節器11において前記(1)〜(4式に
基<PID演算が行なわれ、この稼動側調節器11の出
力信号S5が切換スイッチ′6を経て制御対象4に供給
される。上記制御対象4に対する制御量Xは検出器3に
よって検出され、この検出&IX1は前記稼動側PID
調節器11および侍(表側PID調節器12にフィード
バックされる。一方、侍tilRIIPID調節器12
においては、稼動111PID!1節器11の積分演算
結果を前記(5)式に基いて推定し、推定された積分F
14算結果を積分初期値として前記(a〜(9)式に基
<PID演算が行なわれ、所定時間が経過した時点で再
び稼動側PID11節器11の積分演算結果を推定し、
これを積分初期値としてPID演算を行ない、以下これ
が所定間隔で繰返される。こうすることにより、待機側
PID調節器12の出力は稼動側PIO調節器11の出
力とほぼ等しい値となる。
In this example configured as described above, the operating side PID controllers 11 and 11j open PID! by the switching control signal s3 from the monitor 7. 1-section device 12 is determined. Then, <PID calculation is performed in the operating side PIDI moderator 11 based on the above-mentioned equations (1) to (4), and the output signal S5 of this operating side regulator 11 is supplied to the controlled object 4 via the changeover switch '6. The control amount X for the controlled object 4 is detected by the detector 3, and this detection &IX1 is the operating side PID
controller 11 and Samurai (feedback to the front side PID controller 12. On the other hand, the Samurai tilRIIPID controller 12
In operation 111PID! The integral calculation result of the one-node unit 11 is estimated based on the above equation (5), and the estimated integral F
14 calculation result is used as the initial integration value, <PID calculation is performed based on the above formulas (a to (9)), and when a predetermined time has elapsed, the integration calculation result of the operating side PID 11 node 11 is estimated again,
PID calculation is performed using this as the initial value of integration, and this is repeated at predetermined intervals thereafter. By doing so, the output of the standby side PID regulator 12 becomes approximately equal to the output of the active side PIO regulator 11.

したがって、前記稼動側PID調節器11における異常
が監視器7にて検出され、このFM視器7から出力され
る切換制御信号S3に応じて切換スイッチ6が切換えら
れ、lll1lIループに待機側PID調節器12が含
まれても、上記制御対象4に供給される制御信号が過大
変化するおそれはない。
Therefore, an abnormality in the operating side PID regulator 11 is detected by the monitor 7, and the changeover switch 6 is switched in accordance with the switching control signal S3 outputted from the FM monitor 7, and the standby side PID adjustment is performed in the llll1lI loop. Even if the controller 12 is included, there is no risk that the control signal supplied to the controlled object 4 will change excessively.

かくして制御対象4に対する制御量Xが大きく変動する
こともなく、安定した制御が可能となる。
In this way, the control amount X for the controlled object 4 does not vary greatly, making stable control possible.

なお、本発明は前記実施例に限定されるものではない。Note that the present invention is not limited to the above embodiments.

たとえば前記実施例ではPID調節器を2個用いて二重
冗長系を構成した場合を示したが、311以上用いて三
重以上の多重冗長系を構成しても同様な効果を秦する。
For example, in the above embodiment, a double redundant system is constructed using two PID controllers, but the same effect can be obtained even if 311 or more are used to construct a triple or higher multiple redundant system.

また前記実施例ではPID調節器を用いた場合を示した
が、積分動作を含む他の調節器すなわちP調節器、PD
調節器、P+y4m器等にも適用可能である。このほか
本発明の要旨を越えない範囲で種々変形実施可能である
のは勿論である。
Further, in the above embodiment, a case was shown in which a PID regulator was used, but other regulators including an integral operation, such as a P regulator, a PD regulator, etc.
It is also applicable to regulators, P+y4m devices, etc. It goes without saying that various other modifications can be made without departing from the gist of the present invention.

(発明の効果) 以上詳述したように本発明は、制御ループに含まれ積分
演算を行なう稼vJ@ディジタル型lit節器の積分演
算結果を少なくとも一つの待機側ディジタル型調節器に
より推定し、この推定された積分演舞結果を初期値とし
て積分演算を行なうと共に、前記稼lll側ディジタル
型調節器および待機側ディジタル型11節器の動作状態
を監視器により監視し、上記稼動側ディジタル型諷節器
に異常が生じた場合には前記待機側ディジタル型調節器
を制御ループに含ませるように切換手段により調節器出
力を切換えるようにしたものである。
(Effects of the Invention) As described in detail above, the present invention estimates the integral calculation result of the active vJ@digital type lit moderator included in the control loop and performs the integral calculation by at least one standby side digital type controller, Integral calculations are performed using this estimated integral performance result as an initial value, and the operating states of the working side digital controller and the standby digital controller are monitored by a monitor, and the operating status of the working side digital controller is monitored. When an abnormality occurs in the controller, the switching means switches the regulator output so that the standby digital regulator is included in the control loop.

したがって本発明によれば、常に待機側ディジタル型v
A節器の出力が稼動側ディジタル型調節器の出力とほぼ
等しい値になるので、たとえ稼動側ディジタル型調節器
に異常が発生し待機側ディジタル型調節器に切換えられ
ても制御対象に供給される制御信号は過大変化せず、制
御対象に対する制御量が大きく変動するおそれもなく、
常に安定した制−が可能なディジタル型調節装置を提供
できる。
Therefore, according to the present invention, the standby digital type v
Since the output of the A node is approximately equal to the output of the active digital controller, even if an abnormality occurs in the active digital controller and the switch is switched to the standby digital controller, the output will not be supplied to the controlled object. The control signal will not change excessively, and the control amount for the controlled object will not fluctuate greatly.
It is possible to provide a digital adjustment device that allows stable control at all times.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の構成を示すブロック図、第
2図は従来例を示すブロック図である。 1.11・・・稼動側PID調節器、2.12・・・待
機IIIPID調節器、3・・・検出器、4・・・tl
lII[l対象、5・・・端子、6・・・切換スイッチ
、7・・・監視器。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1.11... Working side PID controller, 2.12... Standby III PID regulator, 3... Detector, 4... tl
lII [l Target, 5...terminal, 6...changeover switch, 7...monitor.

Claims (1)

【特許請求の範囲】[Claims] 制御ループに含まれ積分演算を行なう稼動側ディジタル
型調節器と、この稼動側ディジタル型調節器における積
分演算結果を推定しこの積分演算結果を初期値として積
分演算を行なう少なくとも一つの待機側ディジタル型調
節器と、この待機側ディジタル型調節器および前記稼動
側ディジタル型調節器の動作状態を監視する監視器と、
この監視器により前記稼動側ディジタル型調節器に異常
が生じた場合には前記待機側ディジタル型調節器を前記
制御ループに含ませるように調節器出力を切換える切換
手段とを具備したことを特徴とするディジタル型調節装
置。
An active digital type controller included in the control loop and performing integral calculations; and at least one standby digital type controller that estimates the integral calculation results in the active digital type controller and performs integral calculations using the integral calculation results as an initial value. a controller; a monitor that monitors the operating states of the standby digital regulator and the active digital regulator;
The monitor further comprises switching means for switching the regulator output so that the standby digital regulator is included in the control loop when an abnormality occurs in the operating digital regulator. A digital adjustment device.
JP24740984A 1984-11-22 1984-11-22 Digital-type adjuster Pending JPS61125602A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24740984A JPS61125602A (en) 1984-11-22 1984-11-22 Digital-type adjuster

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24740984A JPS61125602A (en) 1984-11-22 1984-11-22 Digital-type adjuster

Publications (1)

Publication Number Publication Date
JPS61125602A true JPS61125602A (en) 1986-06-13

Family

ID=17163003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24740984A Pending JPS61125602A (en) 1984-11-22 1984-11-22 Digital-type adjuster

Country Status (1)

Country Link
JP (1) JPS61125602A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0589372U (en) * 1992-05-12 1993-12-07 オーチス エレベータ カンパニー Structure of face plate for hole button

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56166501A (en) * 1980-05-27 1981-12-21 Yokogawa Hokushin Electric Corp Dual system of adjusting device
JPS573101A (en) * 1980-06-09 1982-01-08 Hitachi Ltd Multiple control device
JPS5933501A (en) * 1982-08-20 1984-02-23 Mitsubishi Electric Corp Controller

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56166501A (en) * 1980-05-27 1981-12-21 Yokogawa Hokushin Electric Corp Dual system of adjusting device
JPS573101A (en) * 1980-06-09 1982-01-08 Hitachi Ltd Multiple control device
JPS5933501A (en) * 1982-08-20 1984-02-23 Mitsubishi Electric Corp Controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0589372U (en) * 1992-05-12 1993-12-07 オーチス エレベータ カンパニー Structure of face plate for hole button

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