JPS61125166A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61125166A JPS61125166A JP59246028A JP24602884A JPS61125166A JP S61125166 A JPS61125166 A JP S61125166A JP 59246028 A JP59246028 A JP 59246028A JP 24602884 A JP24602884 A JP 24602884A JP S61125166 A JPS61125166 A JP S61125166A
- Authority
- JP
- Japan
- Prior art keywords
- type
- type impurity
- semiconductor device
- layer
- contact hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明はＣＭＯＳ（相補型ＭＯＳトランジスタ）回路を
備える半導体装置の製造方法に関し、特に不純物層にお
けるアロイスパイクの防止を図った半導体装置の型造方
法に関するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a method for manufacturing a semiconductor device including a CMOS (complementary MOS transistor) circuit, and more particularly to a method for molding a semiconductor device that aims to prevent alloy spikes in an impurity layer. It is.
近年におけろＩＣ，ＬＳＩ等の半導体装置の高集積化に
伴って素子の微細化が進められ、ＭＯＳ型半導体装置で
はＭＯＳ）ランジスタのスケールダウン、即ちショート
チャネル化が進められ℃（・る。そしてこのショートチ
ャネル化に伴って、素子の不純物層（一般にはソース・
ドレイン領域等）の接合深さも０．２〜０．４μｍ程度
に浅くされて（・る。In recent years, as semiconductor devices such as ICs and LSIs have become more highly integrated, elements have become smaller and smaller, and transistors in MOS type semiconductor devices have been scaled down, that is, short-channeled. Along with this short channel, the impurity layer (generally the source layer) of the element
The junction depth of the drain region, etc.) is also made shallow to about 0.2 to 0.4 μm.
ところで、配線層は通常アルミニウム（ＡＩ）が用いら
れるので、この不純物層は通常Ａｌと接続されてし・る
。このＡＪと不純物層（Ｓｉ）との接続のオーミンク性
を得るための熱処理によって、不純物層（基板）中のＳ
ｉがＡＩ中に溶出するという所謂アロイスパイクが発生
する。モし℃、このアロイスパイクが不純物層の接合面
に達すると接合が短絡したりリーク電流が増大する等素
子の信頼性が低下される。したがって、前述のように接
合深さが益々浅（され℃きている近年のＭＯＳトランジ
スタでは、アロイスパイクによる信頼性の低下が著しく
、高集積化を妨げる原因の一つになって−・る。By the way, since aluminum (AI) is usually used for the wiring layer, this impurity layer is usually connected to Al. By heat treatment to obtain the ohmink property of the connection between this AJ and the impurity layer (Si), S
A so-called alloy spike occurs in which i is eluted into AI. At low temperatures, if this alloy spike reaches the junction surface of the impurity layer, the junction may be short-circuited, leakage current may increase, and the reliability of the device may be reduced. Therefore, as mentioned above, in recent MOS transistors in which the junction depth has become shallower and shallower, reliability is significantly lowered due to alloy spikes, which is one of the reasons for hindering higher integration.
このようなことから、アロイスパイクを抑制ないし防止
する稿々の試みもなされている。例えばＡＩの形成前の
コンタクトホールを通して不純物層にこれと同一導電型
の不純物を再度拡散（補助拡散）させ、その部位の接合
深さを局部的に大きくする方法が提案されて〜・る。こ
の方法は拡散工程を一つ付加するだけで簡便に実施でき
、しかも効果も大きいので有効である。For this reason, attempts have been made to suppress or prevent alloy spikes. For example, a method has been proposed in which an impurity of the same conductivity type is re-diffused (auxiliary diffusion) into the impurity layer through a contact hole before the formation of the AI, thereby locally increasing the junction depth at that location. This method is effective because it can be easily carried out by adding one diffusion step and is highly effective.
しかしながら、この方法は異なる導電型の不純物層・９
まりＰ型歪細物層とＮ型不純物層が併存する半導体装置
（一般にはＣＭＯ３装置）にそのまま適用することがで
きない。したがって製造工程数の多いＣＭＯＳ装置の製
造工程を更に大幅に増大させると℃・う問題が生じろ。However, this method requires impurity layers of different conductivity types.
Therefore, it cannot be directly applied to a semiconductor device (generally a CMO3 device) in which a P-type strained thin layer and an N-type impurity layer coexist. Therefore, if the number of manufacturing steps for a CMOS device is significantly increased, problems will arise.
なお、アロイスパイクの種々の防止法としては、日経マ
グロウヒル社発行、「日経エレクトロニクス（別冊マイ
クロデノ、くイセズ）」、１９ ｓ Ｏ年１月２３日号
、Ｐ１２２に記載のものがある。Various methods for preventing alloy spikes include those described in "Nikkei Electronics (Special Issue Microdeno, Kuisezu)" published by Nikkei McGraw-Hill, January 23, 19 s O, p. 122.
し発明の目的〕
本発明の目的はＣＭＯＳ装置におい℃も極めて容易にし
かも工程数を殆んど増７１０させることなくアロイスパ
イクの防止を図ることのできる半導体装置の製造方法を
提供することにある。OBJECT OF THE INVENTION] An object of the present invention is to provide a method for manufacturing a semiconductor device that can extremely easily reduce temperature in a CMOS device and prevent alloy spikes without increasing the number of steps. .
また、本発明の他の目的は多結晶シリコン層。Another object of the present invention is to provide a polycrystalline silicon layer.
高融点金属シリサイド層ある（・はポリサイド層とＡＩ
とのコンタクト（接続）の改善を図ることのできる方法
を提供することにある。There is a high melting point metal silicide layer (・ is a polycide layer and an AI
The purpose is to provide a method that can improve contact (connection) with.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかＫなるであ
ろう。The above and other objects and novel features of the present invention include:
It will be clear from the description of this specification and the accompanying drawings.
［発明の概要］
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.
すなわち、ＣＭＯＳ装置のコンタクトホールな形成した
上で、Ｐ型不純物層よりも低濃夏でＮ型不純物をコンタ
クトホールを通して導入することにより、Ｐ型不純物層
の特性を阻害することなくＮ型不純物層の接合を局部的
に大きくし、これによりＰ型およびＮ型不純物層でのア
ロイスパイクの発生を防止するものである。In other words, by forming a contact hole for a CMOS device and then introducing N-type impurities through the contact hole at a lower concentration than the P-type impurity layer, the N-type impurity layer can be formed without impairing the characteristics of the P-type impurity layer. The purpose of this is to locally enlarge the junction, thereby preventing the occurrence of alloy spikes in the P-type and N-type impurity layers.
また、ＣＭＯＳ装置のコンタクトホールな形成した上で
、少なくともＰ型不純物層のコンタクトホールを閉塞し
、その上で充分大きなイオン打込量でＮ型不純物のイオ
ン打込入を行ない、Ｎ型不純物層の接合ｇｌＡすを充分
太き（してアロイスパイクの防止を確実なものとし、合
わせて多結晶シリコンとＡＪとのコンタクトの改善を図
るものである。In addition, after forming a contact hole for a CMOS device, at least the contact hole of the P-type impurity layer is closed, and then N-type impurity ions are implanted with a sufficiently large ion implantation amount to form an N-type impurity layer. The purpose is to make the junction GL sufficiently thick to ensure prevention of alloy spikes and to improve the contact between the polycrystalline silicon and the AJ.
〔実施例１〕
第１図は本発明の方法により製造するＣＭＯＳ構造の半
導体装置を示す。[Example 1] FIG. 1 shows a CMOS structure semiconductor device manufactured by the method of the present invention.
Ｎ型シリコン単結晶からなる半導体基板１上のフィール
ド絶縁膜（Ｓｉか膜）２によって画成された領域ＫＰ型
タウエルとＮ型ウェル４を形成し、ここにＮチャネルＭ
Ｏ８＋−ランジスタ５とＰチャネルＭＯＳトランジスタ
６を夫々形成しｉｌ、・る。A region KP-type twell and an N-type well 4 defined by a field insulating film (Si film) 2 on a semiconductor substrate 1 made of an N-type silicon single crystal are formed, and an N-channel M well 4 is formed here.
An O8+- transistor 5 and a P-channel MOS transistor 6 are formed, respectively.
ＮチャネルＭＯ８）ランジスタ５は多結晶シリコンから
なるゲートを極７と、Ｎ型不純物（ＡＳ ）をイオン打
込みして形成したＮ型ソース・ドレイン領域８とで構成
して℃・る。これらソース・ドレイン領域８は接合深さ
が約０．２μｍであるが、本例ではドレイン側の一部下
側にＮ型不純物層９を設けて局部的に深く形成し、ここ
にＡｌ配線１０を接続して℃・る。N-channel MO transistor 5 consists of a gate made of polycrystalline silicon, a pole 7, and an N-type source/drain region 8 formed by ion implantation of N-type impurities (AS). These source/drain regions 8 have a junction depth of approximately 0.2 μm, but in this example, an N-type impurity layer 9 is provided below a portion of the drain side to form a locally deep layer, and an Al wiring 10 is placed here. Connect ℃・ru.
また、ＰチャンネルＭＯＳトランジスタ６は多結晶シリ
コンからなるゲート電極１１と、Ｐ型不純物（Ｂ）をイ
オン打込入して形成したＰ型ンース・ドレイン領域１２
とで構成して℃・る。このソース・ドレイン領域１２の
接合深さは約０．４μｍであり、ドレイン側にＡＪ配線
１３を接続している。The P-channel MOS transistor 6 also includes a gate electrode 11 made of polycrystalline silicon, and a P-type source/drain region 12 formed by ion-implanting P-type impurities (B).
It is composed of ℃・ru. The junction depth of this source/drain region 12 is approximately 0.4 μm, and the AJ wiring 13 is connected to the drain side.
更に前記各ゲート電極７，１１と同時に形成した多Ｍ
晶シリコン膜１４．１５およびその上に層間絶縁膜１６
を介して形成した第２多結晶シリコン膜１７には夫々Ａ
ｌ配線１８，１９，２０を接続している。図中、２１は
ゲート絶縁膜である。Further, a multilayer M formed at the same time as each gate electrode 7, 11
A crystalline silicon film 14, 15 and an interlayer insulating film 16 thereon.
The second polycrystalline silicon film 17 formed through the A
l wirings 18, 19, and 20 are connected. In the figure, 21 is a gate insulating film.
次に以上の構成のＣＭＯＳの製造方法は、第２図に示す
ように常法によりコンタクトホールノ形成までを行なう
。すなわち、
（１）シリコン基板１にＰ型ウェル３． Ｎｆｆ１ウエ
ル４を選訳的に不純物を導入し、これを熱拡散すること
により形成し、その上でフィールド絶縁膜２とゲート絶
縁膜２１を形成する。Next, in the method for manufacturing the CMOS having the above structure, as shown in FIG. 2, the steps up to the formation of contact holes are carried out by a conventional method. That is, (1) P-type well 3. The Nff1 well 4 is formed by selectively introducing impurities and thermally diffusing the impurities, and then the field insulating film 2 and the gate insulating film 21 are formed thereon.
（２）Ｎ型にドープさせた多結晶シリコン膜を堆積しか
つパターニングすることによりゲート電極７゜１１と配
線用の多結晶シリコン膜１４，１５を形成する。(2) A gate electrode 7.11 and polycrystalline silicon films 14 and 15 for wiring are formed by depositing and patterning an N-type doped polycrystalline silicon film.
（３１Ｎ型ウエル４側をレジスト等のマスクで覆った状
態でＰ型ウェル３に対しセルファライン法によってＡｓ
（ひ素）をイオン打込みし、Ｎ型ソース・ドレイン領域
８．８を形成する。濃度は１０２１０２ｌ”である。(With the 31N type well 4 side covered with a mask such as a resist, As is applied to the P type well 3 using the self-line method.
(Arsenic) ions are implanted to form N-type source/drain regions 8.8. The concentration is 102102 l''.
（４）今度はＰ型ウェル３側をレジスト等のマスクで覆
った状態でＮ型つニ／Ｌ／４に対しセルファライン法に
よってＢ（ボロン）をイオン打込みし、Ｐ型ンース・ド
レイン領域１２．１２を形成する。(4) Next, with the P-type well 3 side covered with a mask such as a resist, B (boron) ions are implanted into the N-type Tsuni/L/4 by the self-line method, and the P-type drain region 12 Form .12.
濃度は１０２０ ｃｍ−３である。The concentration is 1020 cm-3.
（５）シかる上で、ＰＳＧ等の層間絶縁膜１６を形成し
、その上建第２多侍晶シリコン膜１７を形成し、更にそ
の上に前述と同質の層間絶縁膜１６（符号は同じ）を形
成する。(5) On top of the film, an interlayer insulating film 16 such as PSG is formed, and a second polymorphous silicon film 17 is formed thereon, and an interlayer insulating film 16 of the same quality as described above (same reference numerals are ) to form.
（６）そして、Ａｌ配線を接続すべき位置、つまりＮ型
ドレイン領域（不純物層）８、Ｐ型ドレイン頒域（不純
物層）１２、多結晶シリコン膜１４゜１５、第２多結晶
シリコン膜１７に夫々対応する位置にコンタクトホール
２２，２３，２４，２５゜２６を形成する。(6) Then, the positions where the Al wiring should be connected, that is, the N-type drain region (impurity layer) 8, the P-type drain region (impurity layer) 12, the polycrystalline silicon film 14° 15, the second polycrystalline silicon film 17 Contact holes 22, 23, 24, and 25° 26 are formed at positions corresponding to , respectively.
そして、本例にあっては、第２図に示すように、このコ
ンタクトホール２２． ２３． ２４． ２５゜２６が
全て開放された状態で全面にＰ（りん）等のＮ型不純物
をイオン打込みして℃・る。この場合、イオン打込量は
１０２０ｃｍ＋３よりも小さい量でイオン打込みを行な
う。この結果、Ｎ型ドレイン領域８ではＡｓよりも拡散
速度の大きなＰが打込まれるためコンタクトホール２２
の対応部位で深く拡散され、第１図に示したように局部
的に深〜・接合の不純物層９が形成されることになる。In this example, as shown in FIG. 2, this contact hole 22. 23. 24. With all 25° and 26 open, an N-type impurity such as P (phosphorus) is ion-implanted into the entire surface at a temperature of 25°C. In this case, the ion implantation amount is smaller than 1020 cm+3. As a result, P, which has a higher diffusion rate than As, is implanted into the N-type drain region 8, so the contact hole 22
The impurity layer 9 is diffused deeply in the corresponding region, and a deep junction impurity layer 9 is locally formed as shown in FIG.
−万、Ｐ型ドレイン１２においては、Ｐの拡散運屓がＢ
より若干小さいことおよび濃度がＢよりも小さく・こと
から、Ｎ型不純物層がＮウェル領域に達するまで下刃に
形成されることはなく、かつＰ型ドレイン１２が損傷さ
れることもな〜・。-10,000, in the P-type drain 12, the diffusion transport of P is B
Since it is slightly smaller than B and its concentration is lower than that of B, the N-type impurity layer is not formed on the lower blade until it reaches the N-well region, and the P-type drain 12 is not damaged. .
したがって、その後にＡＪ膜の堆積、パターニングを行
なってＡｌ配線１０，１３．１Ｂ、１９゜２０を形成す
れば、ｅＫＮ型ドレイン１０にお℃・てはＰのイオン打
込みにより接合深さか大きくされているためにアロイス
パイクが生じることはな（・。マタ、Ｐ型ドレイン１２
にあっては、もともと接合が深℃・ためにアロイスパイ
クは生じな（・。Therefore, if the AJ film is deposited and patterned after that to form the Al interconnects 10, 13.1B, 19°20, the junction depth will be increased by ion implantation of P into the eKN type drain 10 at °C. Alloy spikes do not occur because of the
In this case, alloy spikes do not occur because the bond is originally deep.
これにより、従来のＣＭＯＳ央造工程の途中でイオン打
込量の制限されたイオン打込工程を行なうだけでアロイ
スパイクの生じなし・装置を完成することができ、容易
に高信頼性のｃＭｏｓ型半導体装置を得ることができろ
。As a result, it is possible to complete a device without producing alloy spikes by simply performing an ion implantation process with a limited amount of ion implantation during the conventional CMOS central fabrication process, and it is possible to easily create a highly reliable cMOS type device. You can get semiconductor devices.
〔実施例２〕
第３図は本発明の他の実施例を示し、前記第１図のＣＭ
ＯＳ！！置を製造する別の方法を示して℃・る。[Embodiment 2] FIG. 3 shows another embodiment of the present invention, and the CM of FIG.
OS! ! Here we show another method of manufacturing the temperature range.
すなわち、前例と同様にコンタクトホール２２゜２３．
２４，２５．２６を形成した後にＮ型ドレイン８のみを
開放させるように他のコンタクトホール２３，２４，２
５．２６上にレジスト２７をパターニングしてこれを閉
塞している。そして、その上からＮ型不純物のＰをイオ
ン打込みすることＫよりＮ型ドレイン領域８のみにＰを
イオン打込入でき、その下側にＮ型不純物層９を形成し
て接合深さを大きくすることができる。この場合、Ｐ型
ドレイン領域１２には全くＰがイオン打込されないので
、Ｐのイオン打込ｔはＰ型ドレイン領域のイオン打込量
を考慮する必要はなく、光分に大きな量、つまり＠度に
して１０ ！０ｃｍ−’以上の量での打込みを可能とし
、アロイスパイクを防止し得る充分な深さの接合を形成
することができる。That is, as in the previous example, the contact holes 22°, 23.
After forming contact holes 24, 25, and 26, other contact holes 23, 24, and 2 are formed so that only the N-type drain 8 is opened.
A resist 27 is patterned on 5.26 to close it. Then, by ion-implanting P as an N-type impurity from above, P can be ion-implanted only into the N-type drain region 8, and an N-type impurity layer 9 is formed below it to increase the junction depth. can do. In this case, since no P ions are implanted into the P-type drain region 12, the P ion implantation t does not need to take into account the ion implantation amount of the P-type drain region, and is a large amount in terms of light, that is, @ 10 times! It is possible to implant with an amount of 0 cm-' or more, and to form a bond of sufficient depth to prevent alloy spikes.
なお、工程としてはレジスト工程が１工程必要とされる
が、大喝な工程の増加ではな（製造を複雑化することは
ない。Although one resist step is required as a process, it is not a drastic increase in the number of steps (it does not complicate the manufacturing process).
第４図は前述方法の一部を変形したものであり、レジス
ト２８をＰ型ドレイン領域１２のコンタクトホール２３
をのみ閉塞するようにパターニングしたものである。こ
の場合においても、Ｎ型不純物としてのＰのイオン打込
みに際しては、Ｐ型ドレイン領域１２へのＰの打込みを
考慮する必要がな（・ことから、必要なイオン打込量で
のＮ型不純物層９の形成を行なうことができ、Ｎ型ドレ
イン領域８においてアロイスパイクを防止するのに光分
な接合深さを得ろことができる。FIG. 4 shows a partial modification of the above-mentioned method, in which the resist 28 is applied to the contact hole 23 of the P-type drain region 12.
It is patterned to occlude only the . Even in this case, when ion implanting P as an N-type impurity, there is no need to consider implanting P into the P-type drain region 12. 9 can be formed, and a junction depth sufficient to prevent alloy spikes in the N-type drain region 8 can be obtained.
また、これと共にコンタクトホール２４，２５゜２６を
通して多結晶シリコン膜１４，１５と第２多結晶シリコ
７１ｇＩ！１７にも充分にＰをイオン打込入してそのｆ
Ｉｋ度を高めることができるので、その抵抗を下げ、Ａ
Ｉ！配１ｇＪ１８，１９．２０との接続を良好なものに
できる。特に、ＰチャンネルＭＯＳトランジスタ６の近
傍の多結晶シリコン膜１５ではＰ型ンース・ドレイン領
域１２．１２の形成の際のＢのイオン打込入に工つてＮ
型不純物濃度が低下された状態にあるため、改めてＰを
イオン打込みすることによりこれを修正し、前述のよう
に艮好な接続を得ることができる。At the same time, the polycrystalline silicon films 14 and 15 are connected to the second polycrystalline silicon film 71gI! through the contact holes 24 and 25°26. 17 is also sufficiently ion-implanted with P, and its f
Since the Ik degree can be increased, the resistance can be lowered and the A
I! Good connection with wiring 1gJ18, 19.20 can be achieved. In particular, in the polycrystalline silicon film 15 near the P-channel MOS transistor 6, N
Since the type impurity concentration is in a reduced state, this can be corrected by anew P ion implantation, and a good connection can be obtained as described above.
（１１ＣＭ ＯＳ装置のコンタクトホールを形成した後
に、Ｐ型ソース・ドレイン領域のイオン打込量より小さ
いイオン打込量で全面にりん等のＮ型不純物をイオン打
込入しているので、Ｐ型ノース・ドレイン領域を損傷す
ることなくＮ型ソース・ドレイン領域に局部的に深い接
合を形成でき、Ａｌコンタクトによるアロイスパイクを
防止し、半導体装置の信頼性を向上できる。(After forming the contact holes for the 11CM OS device, N-type impurities such as phosphorus are ion-implanted into the entire surface with a smaller ion-implantation amount than the ion-implantation amount for the P-type source/drain regions. A locally deep junction can be formed in the N-type source/drain region without damaging the north/drain region, preventing alloy spikes caused by Al contacts, and improving the reliability of the semiconductor device.
（２） これまでと同じＣＭＯＳ製造工程の途中でＮ
型不純物のイオン打込みを行なうだけでアロイスパイク
の防止を図ることができるので、製造工程を殆んど増加
することはなく、容易に製造できる。(2) During the same CMOS manufacturing process as before, N
Since alloy spikes can be prevented simply by ion implantation of type impurities, the manufacturing process can be easily manufactured with almost no increase in the number of manufacturing steps.
（３）少なくともＰ型ソース・ドレイン領域のコンタク
トホールを閉塞した状態でＮ型不純物のイオン打込みを
行なうので、Ｐ型ノース・ドレイン領域のイオン打込量
よりも大きいイオン打込みを行なってもＰ型ソニス・ド
レイン領域を損傷することはなく、これＫよりＮ型ソー
ス・ドレイン領域に充分の量のＮ型不純物の打込みを可
能とし、アロイスパイクの防止に充分な深（・接合を得
ることができる。(3) Since N-type impurity ions are implanted with at least the contact holes in the P-type source/drain region blocked, even if the ion implantation amount is larger than that of the P-type north drain region, the P-type It does not damage the sonic/drain regions, and it is possible to implant a sufficient amount of N-type impurities into the N-type source/drain regions using K, and to obtain a junction deep enough to prevent alloy spikes. .
（４） これまでと同じＣＭＯＳｊＪ造工程の途少工
程レジスト工程とイオン打込み工程を付加するだけでよ
いので、大喝な工程の増力０は必要なく、他のアロイス
パイク防止方法に比較して容易に行なうことができる。(4) Since it is only necessary to add the resist process and ion implantation process to the same CMOSJJ fabrication process as before, there is no need to increase the force of the major process, and it is easier than other alloy spike prevention methods. can be done.
（５）Ｎ型ソース・ドレイン領域へのＮ型不純物のイオ
ン打込みと同時に多結晶ポリシリコン膜へのイオン打込
みを行なって℃・ろので、多結晶ポリシリコンの低抵抗
化を図り、ＡＩｌコンタクトとの接続を良好なものにす
ることができる。(5) At the same time as the ion implantation of N-type impurity into the N-type source/drain region, the ion implantation into the polycrystalline polysilicon film is performed to lower the resistance of the polycrystalline polysilicon and connect it to the Al contact. connection can be made good.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しなし・範囲で種々変更
可能であることはいうまでもない。たとえば、第２実施
例の方法ではＮ型不純物にＡｓを用℃・ることもできる
。また、不純物層はＮ型ソース・ドレイン以外にも基板
コンタクトやウェルコンタクト等のＮ型不純物層にも適
用できる。Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, in the method of the second embodiment, As can be used as the N-type impurity. Furthermore, the impurity layer can be applied not only to N-type sources and drains but also to N-type impurity layers such as substrate contacts and well contacts.
またポリシリコン層は高融点金属層、あるいはそのシリ
サイド層、またはポリシリコン層とその上に形成された
高融点金属層またはそのシリサイド層からなる２層構造
であってもよい。Further, the polysilicon layer may be a high melting point metal layer, a silicide layer thereof, or a two-layer structure consisting of a polysilicon layer and a high melting point metal layer or silicide layer formed thereon.
し利用分野〕
以上の説明では主として本発明者′ＶＣよってなされた
発明をその背景となった利用分野である０ＭＯ８装置の
Ｎ型ソース・ドレイン領域でのアロイスパイク防止方法
に適用した場合について説明したが、それに限定される
ものではな（前述のように基板コンタクト、ウェルコン
タクトやその外のコンタクトを有するＮ型不純物層への
適用、およびＡＪ以外のコンタクト材料を用（・る場合
にも同様に適用できる。[Field of Application] The above explanation has mainly been about the application of the invention made by the present inventor, VC, to a method for preventing alloy spikes in the N-type source/drain region of an 0MO8 device, which is the field of application that formed the background of the invention. However, it is not limited to this (as mentioned above, it can be applied to an N-type impurity layer having a substrate contact, well contact, or other contact), or when using a contact material other than AJ. Applicable.
第１図は本発明方法により製造する０ＭＯ５装置の断面
図、
第２図は本発明の一実施例方法を説明するための断面図
、
第３図は本発明の他の実施例方法を説明するための断面
図、
第４図はその変形方法の断面図である。
１・・・シリコン基板、３・・・Ｎ型りエル、４・・・
Ｐ型ウェル、５・・・Ｎチャネ／Ｉ／ＭＯＳトランジス
タ、６・・・ＰチャネルＭＯＳトランジスタ、７・・・
ゲート電極、８・・・Ｎ型ソース・ドレイン領域、９・
・・Ｎ型不純物層、１０・・・Ａ！配置１！（コンタク
ト）、１１・・・ゲート電極、１２・・・Ｐ型ソース・
ドレイン領域、１３・・・ＡＩ配Ｍ（コンタクト）、１
４．１５・・・多結晶シリコン膜、１９・・・層間絶ｌ
ｉｋ鵬、１７川第２多結晶シリコン膜、１８，１９．２
０・・・Ａ！配線（コンタクト）、２２〜２６・・・コ
ンタクトホール、２７．２８・・・レジスト。Fig. 1 is a cross-sectional view of an 0MO5 device manufactured by the method of the present invention, Fig. 2 is a cross-sectional view for explaining one embodiment of the method of the present invention, and Fig. 3 is a cross-sectional view for explaining another embodiment of the method of the present invention. FIG. 4 is a cross-sectional view of the deformation method. 1...Silicon substrate, 3...N type reel, 4...
P-type well, 5... N channel/I/MOS transistor, 6... P channel MOS transistor, 7...
Gate electrode, 8... N-type source/drain region, 9.
...N-type impurity layer, 10...A! Placement 1! (contact), 11...gate electrode, 12...P-type source
Drain region, 13... AI contact (contact), 1
4.15...polycrystalline silicon film, 19...layer interlayer l
ik Peng, 17 River 2nd polycrystalline silicon film, 18, 19.2
0...A! Wiring (contact), 22-26... Contact hole, 27.28... Resist.
Claims (1)
後に、Ｐ型不純物層よりも小さいイオン打込量で前記コ
ンタクトホールを通してＮ型不純物をイオン打込みする
ことを特徴とする半導体装置の製造方法。 ２、コンタクトホールはＮ型、Ｐ型の各不純物層、多結
晶シリコン層、高融点金属層、高融点金属シリサイド層
あるいはポリサイド層に対して形成する特許請求の範囲
第１項記載の半導体装置の製造方法。 ３、Ｎ型不純物はりん又はひ素である特許請求の範囲第
１項又は第２項記載の半導体装置の製造方法。 ４、Ｐ型、Ｎ型不純物層は夫々Ｐチャネル、Ｎチャネル
各ＭＯＳトランジスタのソース・ドレイン領域および配
線領域である特許請求の範囲第１項ないし第３項のいず
れかに記載の半導体装置の製造方法。 ５、ＣＭＯＳ構造の半導体装置のコンタクトホール形成
後に、少なくともＰ型不純物層のホールを閉塞してＮ型
不純物をイオン打込みすることを特徴とする半導体装置
の製造方法。 ６、Ｎ型不純物層のホールのみを開放状態にしてＮ型不
純物層をイオン打込みしてなる特許請求の範囲第５項記
載の半導体装置の製造方法。 ７、Ｎ型不純物はＰ型不純物層よりも大きいイオン打込
量でイオン打込みしてなる特許請求の範囲第５項又は第
６項記載の半導体装置の製造方法。 ８、Ｎ型不純物はりん又はひ素である特許請求の範囲第
５項ないし第７項のいずれかに記載の半導体装置の製造
方法。 ９、コンタクトホールはパターニングしたフォトレジス
トで閉塞する特許請求の範囲第５項ないし第８項のいず
れかに記載の半導体装置の製造方法。[Claims] 1. After forming a contact hole of a semiconductor device having a CMOS structure, an N-type impurity is ion-implanted through the contact hole with a smaller ion implantation amount than that of a P-type impurity layer. Production method. 2. The semiconductor device according to claim 1, wherein the contact hole is formed in each of N-type and P-type impurity layers, a polycrystalline silicon layer, a high melting point metal layer, a high melting point metal silicide layer, or a polycide layer. Production method. 3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the N-type impurity is phosphorus or arsenic. 4. Manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the P-type and N-type impurity layers are source/drain regions and wiring regions of P-channel and N-channel MOS transistors, respectively. Method. 5. A method for manufacturing a semiconductor device, which comprises, after forming a contact hole in a CMOS structure semiconductor device, blocking at least a hole in a P-type impurity layer and implanting N-type impurity ions. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the N-type impurity layer is ion-implanted with only the holes in the N-type impurity layer open. 7. The method of manufacturing a semiconductor device according to claim 5 or 6, wherein the N-type impurity is ion-implanted with a larger ion implantation amount than the P-type impurity layer. 8. The method for manufacturing a semiconductor device according to any one of claims 5 to 7, wherein the N-type impurity is phosphorus or arsenic. 9. The method of manufacturing a semiconductor device according to any one of claims 5 to 8, wherein the contact hole is closed with a patterned photoresist.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59246028A JPS61125166A (en) | 1984-11-22 | 1984-11-22 | Manufacture of semiconductor device |
| KR1019850008576A KR940006668B1 (en) | 1984-11-22 | 1985-11-16 | Manufacturing method of semiconductor ic device |
| EP85114857A EP0183204A3 (en) | 1984-11-22 | 1985-11-22 | Process for fabricating semiconductor integrated circuit devices |
| CN85109742A CN85109742B (en) | 1984-11-22 | 1985-11-22 | Method of producing semiconductor integrated circuit devices |
| US06/800,954 US4734383A (en) | 1984-11-22 | 1985-11-22 | Fabricating semiconductor devices to prevent alloy spiking |
| US07/351,323 US5055420A (en) | 1984-11-22 | 1989-05-09 | Process for fabricating semiconductor integrated circuit devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59246028A JPS61125166A (en) | 1984-11-22 | 1984-11-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61125166A true JPS61125166A (en) | 1986-06-12 |
Family
ID=17142373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59246028A Pending JPS61125166A (en) | 1984-11-22 | 1984-11-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61125166A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02235369A (en) * | 1989-03-09 | 1990-09-18 | Fujitsu Ltd | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856450A (en) * | 1981-09-30 | 1983-04-04 | Nec Corp | Complementary mos semiconductor device |
| JPS5874070A (en) * | 1982-10-08 | 1983-05-04 | Hitachi Ltd | Manufacture of semiconductor device |
-
1984
- 1984-11-22 JP JP59246028A patent/JPS61125166A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5856450A (en) * | 1981-09-30 | 1983-04-04 | Nec Corp | Complementary mos semiconductor device |
| JPS5874070A (en) * | 1982-10-08 | 1983-05-04 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02235369A (en) * | 1989-03-09 | 1990-09-18 | Fujitsu Ltd | Semiconductor device |
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