JPS61124157A - 半導体装置用キヤツプ・フレ−ム - Google Patents
半導体装置用キヤツプ・フレ−ムInfo
- Publication number
- JPS61124157A JPS61124157A JP59245312A JP24531284A JPS61124157A JP S61124157 A JPS61124157 A JP S61124157A JP 59245312 A JP59245312 A JP 59245312A JP 24531284 A JP24531284 A JP 24531284A JP S61124157 A JPS61124157 A JP S61124157A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- frame
- caps
- resin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59245312A JPS61124157A (ja) | 1984-11-20 | 1984-11-20 | 半導体装置用キヤツプ・フレ−ム |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59245312A JPS61124157A (ja) | 1984-11-20 | 1984-11-20 | 半導体装置用キヤツプ・フレ−ム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61124157A true JPS61124157A (ja) | 1986-06-11 |
| JPH0351300B2 JPH0351300B2 (enExample) | 1991-08-06 |
Family
ID=17131797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59245312A Granted JPS61124157A (ja) | 1984-11-20 | 1984-11-20 | 半導体装置用キヤツプ・フレ−ム |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61124157A (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63174340A (ja) * | 1987-01-13 | 1988-07-18 | Ibiden Co Ltd | 半導体装置 |
| JPH0529152U (ja) * | 1992-08-07 | 1993-04-16 | イビデン株式会社 | 電子部品装置 |
-
1984
- 1984-11-20 JP JP59245312A patent/JPS61124157A/ja active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63174340A (ja) * | 1987-01-13 | 1988-07-18 | Ibiden Co Ltd | 半導体装置 |
| JPH0529152U (ja) * | 1992-08-07 | 1993-04-16 | イビデン株式会社 | 電子部品装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0351300B2 (enExample) | 1991-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5322207A (en) | Method and apparatus for wire bonding semiconductor dice to a leadframe | |
| US8071426B2 (en) | Method and apparatus for no lead semiconductor package | |
| US5034350A (en) | Semiconductor device package with dies mounted on both sides of the central pad of a metal frame | |
| US5652185A (en) | Maximized substrate design for grid array based assemblies | |
| US6462273B1 (en) | Semiconductor card and method of fabrication | |
| US6376277B2 (en) | Semiconductor package | |
| US6175149B1 (en) | Mounting multiple semiconductor dies in a package | |
| JPS629639A (ja) | 半導体装置の製造方法 | |
| EP0923120A1 (en) | Method for manufacturing semiconductor device | |
| KR20050066999A (ko) | 반도체장치 및 그 제조방법 | |
| JPS61124157A (ja) | 半導体装置用キヤツプ・フレ−ム | |
| US6475878B1 (en) | Method for singulation of integrated circuit devices | |
| US10079162B1 (en) | Method for making lead frames for integrated circuit packages | |
| JPH08227964A (ja) | リードフレーム、半導体集積回路装置、半導体集積回路装置製造方法及び半導体集積回路装置製造装置 | |
| US8106489B1 (en) | Integrated circuit package and packaging method | |
| US20150206829A1 (en) | Semiconductor package with interior leads | |
| EP4657521A1 (en) | A method of fabricating a semiconductor integrated circuits package | |
| JPH08125088A (ja) | リードフレームおよびこのリードフレームを用いた電子部品の製造方法 | |
| JPS63120450A (ja) | 半導体装置の製造方法およびこれに用いるリ−ドフレ−ム | |
| JPH0831998A (ja) | 半導体装置およびその製造に用いるリードフレームならびにワイヤボンディング装置 | |
| JP2000349187A (ja) | 半導体装置及び半導体装置の製造方法 | |
| KR200164519Y1 (ko) | 캡형 멀티 칩 모듈 반도체 패키지 | |
| KR100377466B1 (ko) | 반도체패키지용 써킷테이프의 라미네이션 장치 및 그 방법 | |
| JP2001144036A (ja) | Icチップのパッケージ方法 | |
| JP2000077450A (ja) | 半導体装置およびその製造方法 |