JPH0351300B2 - - Google Patents
Info
- Publication number
- JPH0351300B2 JPH0351300B2 JP59245312A JP24531284A JPH0351300B2 JP H0351300 B2 JPH0351300 B2 JP H0351300B2 JP 59245312 A JP59245312 A JP 59245312A JP 24531284 A JP24531284 A JP 24531284A JP H0351300 B2 JPH0351300 B2 JP H0351300B2
- Authority
- JP
- Japan
- Prior art keywords
- cap
- frame
- caps
- resin
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
- H10W76/12—Containers or parts thereof characterised by their shape
- H10W76/15—Containers comprising an insulating or insulated base
- H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W95/00—Packaging processes not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59245312A JPS61124157A (ja) | 1984-11-20 | 1984-11-20 | 半導体装置用キヤツプ・フレ−ム |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59245312A JPS61124157A (ja) | 1984-11-20 | 1984-11-20 | 半導体装置用キヤツプ・フレ−ム |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61124157A JPS61124157A (ja) | 1986-06-11 |
| JPH0351300B2 true JPH0351300B2 (enExample) | 1991-08-06 |
Family
ID=17131797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59245312A Granted JPS61124157A (ja) | 1984-11-20 | 1984-11-20 | 半導体装置用キヤツプ・フレ−ム |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61124157A (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0821641B2 (ja) * | 1987-01-13 | 1996-03-04 | イビデン株式会社 | 半導体装置 |
| JPH0529152U (ja) * | 1992-08-07 | 1993-04-16 | イビデン株式会社 | 電子部品装置 |
-
1984
- 1984-11-20 JP JP59245312A patent/JPS61124157A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61124157A (ja) | 1986-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5652185A (en) | Maximized substrate design for grid array based assemblies | |
| US6376277B2 (en) | Semiconductor package | |
| US6462273B1 (en) | Semiconductor card and method of fabrication | |
| US8071426B2 (en) | Method and apparatus for no lead semiconductor package | |
| US5034350A (en) | Semiconductor device package with dies mounted on both sides of the central pad of a metal frame | |
| US6723585B1 (en) | Leadless package | |
| US5322207A (en) | Method and apparatus for wire bonding semiconductor dice to a leadframe | |
| KR0179920B1 (ko) | 칩 사이즈 패키지의 제조방법 | |
| US20010017410A1 (en) | Mounting multiple semiconductor dies in a package | |
| US6110755A (en) | Method for manufacturing semiconductor device | |
| JPS629639A (ja) | 半導体装置の製造方法 | |
| US9443791B2 (en) | Leadless semiconductor package and method | |
| JPH0828455B2 (ja) | リードフレーム及びそれを用いた電子部品の製造方法 | |
| US6475878B1 (en) | Method for singulation of integrated circuit devices | |
| JPS61124157A (ja) | 半導体装置用キヤツプ・フレ−ム | |
| US10079162B1 (en) | Method for making lead frames for integrated circuit packages | |
| US20200321228A1 (en) | Method of manufacturing a lead frame, method of manufacturing an electronic apparatus, and electronic apparatus | |
| JPH08227964A (ja) | リードフレーム、半導体集積回路装置、半導体集積回路装置製造方法及び半導体集積回路装置製造装置 | |
| US8106489B1 (en) | Integrated circuit package and packaging method | |
| KR20010061886A (ko) | 적층 칩 패키지 | |
| JP3243951B2 (ja) | 電子部品の製造方法 | |
| JP2000349187A (ja) | 半導体装置及び半導体装置の製造方法 | |
| KR200164519Y1 (ko) | 캡형 멀티 칩 모듈 반도체 패키지 | |
| JPH0770640B2 (ja) | Icチップの製造方法 | |
| KR890003214B1 (ko) | 주석 도금이 된 반도체 제조용 리드 프레임(lead frame)및 그 제조방법 |