JPS61123553U - - Google Patents
Info
- Publication number
- JPS61123553U JPS61123553U JP584385U JP584385U JPS61123553U JP S61123553 U JPS61123553 U JP S61123553U JP 584385 U JP584385 U JP 584385U JP 584385 U JP584385 U JP 584385U JP S61123553 U JPS61123553 U JP S61123553U
- Authority
- JP
- Japan
- Prior art keywords
- layer
- plating layer
- conductive
- printer head
- copper plating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007747 plating Methods 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 230000003287 optical effect Effects 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Exposure Or Original Feeding In Electrophotography (AREA)
- Dot-Matrix Printers And Others (AREA)
Description
第１図は本考案実施例の光プリンタヘツドの要
部断面図で、第２図は光プリスタヘツドの斜視図
である。
１…基台、２…導体、２１…導電性印刷層、２
２…銅メツキ層、２３…第２のメツキ層、３…発
光ダイオードアレイ、５，５…配線導体。
FIG. 1 is a sectional view of essential parts of an optical printer head according to an embodiment of the present invention, and FIG. 2 is a perspective view of the optical printer head. DESCRIPTION OF SYMBOLS 1... Base, 2... Conductor, 21... Conductive printed layer, 2
2... Copper plating layer, 23... Second plating layer, 3... Light emitting diode array, 5, 5... Wiring conductor.
Claims (1)
導体上に整列して載置固着された発光ダイオード
アレイとを有する光プリンタヘツドにおいて、前
記導体は導電性印刷層と、その導電性印刷層上の
銅メツキ層と、銅メツキ層上の第２メツキ層を具
備した事を特徴とする光プリンタヘツド。 (2) 前記導電性印刷層は金を主体とする材料か
らなり、前記銅メツキ層は導電性印刷層より厚い
事を特徴とする前記実用新案登録請求の範囲第１
項記載の光プリンタヘツド。[Scope of claims for utility model registration] (1) A base and a long conductor provided on the base;
In an optical printer head having a light emitting diode array aligned and fixed on a conductor, the conductor includes a conductive printed layer, a copper plating layer on the conductive print layer, and a second copper plating layer on the conductive print layer. An optical printer head characterized by having a plating layer. (2) Claim 1 of the above-mentioned utility model registration, wherein the conductive printed layer is made of a material mainly containing gold, and the copper plating layer is thicker than the conductive printed layer.
Optical printer head as described in section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP584385U JPS61123553U (en) | 1985-01-19 | 1985-01-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP584385U JPS61123553U (en) | 1985-01-19 | 1985-01-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61123553U true JPS61123553U (en) | 1986-08-04 |
Family
ID=30482730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP584385U Pending JPS61123553U (en) | 1985-01-19 | 1985-01-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61123553U (en) |
-
1985
- 1985-01-19 JP JP584385U patent/JPS61123553U/ja active Pending