JPS61123156A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61123156A JPS61123156A JP24120884A JP24120884A JPS61123156A JP S61123156 A JPS61123156 A JP S61123156A JP 24120884 A JP24120884 A JP 24120884A JP 24120884 A JP24120884 A JP 24120884A JP S61123156 A JPS61123156 A JP S61123156A
- Authority
- JP
- Japan
- Prior art keywords
- terminals
- cascade
- sides
- metallic
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Microwave Amplifiers (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は超高周波回路に用いられる半導体装置に係り、
特にパフケージを改良したこの種の半導体装置に関する
。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device used in an ultra-high frequency circuit,
In particular, the present invention relates to this type of semiconductor device with an improved puff cage.
衛星通信等に用いられるマイクロ波、準ミリ波等の超高
周波回路モジュールを構成する超高周波半導体装置は増
幅素子や発振素子等を、マイクロストリップラインより
なるリード端子を有するパッケージに搭載される。BACKGROUND ART A super high frequency semiconductor device constituting a super high frequency circuit module for microwaves, quasi-millimeter waves, etc. used in satellite communications etc. has an amplifier element, an oscillating element, etc. mounted in a package having lead terminals made of microstrip lines.
上記端子を有する超高周波半導体装置を縦続接続して回
路モジエールを構成するためには、内部回路は反射波の
影響を除去して特性インピーダンスに整合することが必
要となり、これを行うことにより複数段直接結合が可能
となる。In order to configure a circuit module by cascade-connecting ultra-high frequency semiconductor devices having the above terminals, the internal circuit must eliminate the influence of reflected waves and match the characteristic impedance. Direct connection is possible.
さらに内部回路によっては、縦続接続可能な端子の他に
内部回路の機能を制御する補助端子を必要とする場合が
あり、このような半導体装置に対して有効なパンケージ
の改良が望まれる。Further, depending on the internal circuit, in addition to terminals that can be connected in series, auxiliary terminals may be required to control the functions of the internal circuit, and it is desired to improve the pancage to be effective for such semiconductor devices.
第5図は従来例による縦続接続可能なパッケージの平面
図と正面図と側断面図である。FIG. 5 is a plan view, a front view, and a side sectional view of a conventional package that can be connected in series.
このパッケージを用いた半導体装置は本発明者により特
願昭57−073080号明細書に開示されており、超
高周波用として優れた特性を有する。A semiconductor device using this package was disclosed by the present inventor in Japanese Patent Application No. 57-073080, and has excellent characteristics for ultra-high frequencies.
図において、1は金属基体、IAは金属国体、2乃至7
は電気端子で、これらの端子は絶縁物基体2A乃至7A
と、ストリップラインを形成するリード片2B乃至7B
と、絶縁物駒体2C乃至7Cとにより構成され、金属国
体IAに嵌挿される。In the figure, 1 is a metal base, IA is a metal body, 2 to 7
are electrical terminals, and these terminals are connected to insulating substrates 2A to 7A.
and lead pieces 2B to 7B forming a strip line.
and insulator pieces 2C to 7C, and is inserted into the metal body IA.
なお絶縁物基体2A乃至7Aと、絶縁物駒体2c乃至7
Cの金属国体IAに接する部分は前もってメタライズ膜
を被着しておく。Note that the insulator bases 2A to 7A and the insulator pieces 2c to 7
A metallized film is previously applied to the portion of C that is in contact with the metal body IA.
2.3は高周波(RF)端子、4,5,6.7は直流(
D C>端子である。2.3 is a high frequency (RF) terminal, 4, 5, and 6.7 are DC (
D C> terminal.
この実施例のものを複数個連結するには、少なくとも最
初と最後のもの以外のリード片は除去し、ストリップ・
ライン同志をリード・ポンディングして行う。To connect multiple pieces of this example, remove at least the first and last lead pieces, and strip
This is done by lead pounding the line comrades.
この例では、内部回路はバランス型増幅器をサファイア
基板に搭載し、それを金属国体IAに封入した。In this example, the internal circuit is a balanced amplifier mounted on a sapphire substrate, which is enclosed in a metal metal IA.
この装置では電気端子は擬似同軸になっているので、ア
ース電極(金属基体1)によりDC端子から隔離され、
高周波結合は全く見られない。In this device, the electrical terminal is pseudo-coaxial, so it is isolated from the DC terminal by the ground electrode (metal base 1).
No high frequency coupling is observed.
電力利得は8〜18GH2で5〜6dBと小型パッケー
ジに封入されたものとしては、極めて良好な高周波特性
を示している。The power gain is 8 to 18 GH2 and 5 to 6 dB, which shows extremely good high frequency characteristics for a device sealed in a small package.
また人出力のV S W R(Voltage Sta
nding WaveRatio、定在波比)は8〜1
8GHzで1.2〜1.4と極めて良い特性が得られた
。VSWRは反射率をTとすると、
γ=1 で、 V SWR=■
r=o で、 VSWR=1
となり、VSWRが2〜3以下であれば多段接続が可能
となるため、このパフケージを用いてCAS P A
C(Cascadable Packaged Amp
lifier)を構成できる。In addition, the human output V S W R (Voltage Sta.
nding WaveRatio, standing wave ratio) is 8 to 1
Very good characteristics of 1.2 to 1.4 at 8 GHz were obtained. For VSWR, if the reflectance is T, then γ=1, VSWR=■ r=o, and VSWR=1. If VSWR is 2 to 3 or less, multi-stage connection is possible, so using this puff cage. C.A.S.P.A.
C (Cascadable Packaged Amp
can be configured.
例えば増幅段と利得可変段よりなる増幅器のそれぞれの
段を別々のパッケージに搭載して構成する場合は、利得
可変段は通常PIN@衰器が用いられ、この機能を生か
すために補助端子(コントロール端子)を必要とするが
、この内部回路を従来例のパッケージに封入するために
補助端子にDC端子等の縦続接続可能な端子を使用する
と、縦続接続性が損なわれることになる。For example, when configuring an amplifier consisting of an amplification stage and a variable gain stage in separate packages, a PIN@attenuator is normally used for the variable gain stage, and in order to take advantage of this function, an auxiliary terminal (control However, if a terminal that can be connected in cascade, such as a DC terminal, is used as an auxiliary terminal in order to encapsulate this internal circuit in a conventional package, cascade connectivity will be impaired.
上記問題点の解決は、半導体チップが略矩形の金属容器
に搭載され、該金属容器が金属蓋体によって気密封止さ
れる構造を有し、縦続接続可能な端子を該金属容器の相
対する2辺に、その他の端子を該金属容器の相対する2
辺以外の辺に具備してなる本発明による半導体装置によ
り達成される。The solution to the above problem is to have a structure in which a semiconductor chip is mounted in a substantially rectangular metal container, the metal container is hermetically sealed with a metal lid, and cascade-connectable terminals are connected to two opposite terminals of the metal container. Attach the other terminals to the opposite sides of the metal container.
This is achieved by the semiconductor device according to the present invention, which is provided on sides other than the sides.
(作用〕
′4i1続接続可能な端子を、縦続接続方向に垂直な金
属容器の辺に設けることにより′4ii続接続を行い、
補助端子を縦続接続方向に並行な辺に設けることにより
内部回路の機能を有効に働かすことができる。(Function) By providing a terminal capable of connecting a single '4i connection on the side of the metal container perpendicular to the cascade connection direction, a '4ii connection is made.
By providing auxiliary terminals on sides parallel to the cascade connection direction, the function of the internal circuit can be effectively utilized.
第1図(a)乃至(d)はそれぞれ本発明による縦続接
続可能なパッケージを用いた半導体装置の平面図と正面
図と側面図と側断面図である。FIGS. 1(a) to 1(d) are a plan view, a front view, a side view, and a side sectional view, respectively, of a semiconductor device using packages that can be connected in series according to the present invention.
図において、8,9は補助端子で、これらの端子は縦続
接続可能な端子2乃至7と同様に構成され、金属国体I
Aの縦続接続方向に並行な2辺にそれぞれ嵌挿される。In the figure, 8 and 9 are auxiliary terminals, and these terminals are configured in the same way as the terminals 2 to 7 that can be connected in cascade, and are connected to metal national body I.
They are inserted into the two sides parallel to the cascade connection direction of A.
縦続接続可能な端子はRF端子2,3と、DC端子4.
5,6.’7で、金属国体IAの縦続接続方向に垂直な
2つの辺に嵌挿し、一方の辺を入力側とし、他方の辺を
出力側とする。Terminals that can be connected in cascade are RF terminals 2 and 3, and DC terminal 4.
5,6. '7, it is inserted into the two sides perpendicular to the cascade connection direction of the metal national body IA, and one side is set as the input side and the other side is set as the output side.
11は内部回路を示す。11 indicates an internal circuit.
第2図はパッケージに搭載する利得可変段の回路図であ
る。FIG. 2 is a circuit diagram of a variable gain stage mounted on the package.
図は前述の利得可変段で、通常PIN減衰器を用いて、
ここでの損失を変化させ、増幅器の利得を自由に調節で
きるようにしている。The figure shows the variable gain stage mentioned above, which normally uses a PIN attenuator.
By changing the loss here, the gain of the amplifier can be adjusted freely.
例えば、温度が変化しても利得を一定に保ちたいときは
、温度をサーミスタで検知し、温度が低いときは増幅器
の利得が上がるから、PIN減衰器の減衰量を増やすよ
うにする。また逆の場合は減衰量を少なくする。PIN
減衰器の減衰量の調節はPINダイオードのバイアスを
変えることにより行い、そのために補助端子を必要とす
る。For example, if you want to keep the gain constant even when the temperature changes, the temperature is detected with a thermistor, and when the temperature is low, the gain of the amplifier increases, so the amount of attenuation of the PIN attenuator is increased. In the opposite case, the amount of attenuation is reduced. PIN
The amount of attenuation of the attenuator is adjusted by changing the bias of the PIN diode, which requires an auxiliary terminal.
PIN減衰器はPIN(p型半導体−絶縁面一〇型半導
体の構造)ダイオードよりなり、ラインに並列に挿入さ
れる。PINダイオードが低抵抗になるとラインのイン
ピーダンスは低くなり、0になると入ってきた信号は反
射される。逆にPINダイオードの抵抗を大きくしてゆ
くと、信号は出力側に通るようになり、さらに抵抗を大
きくするとまた反射するようになる。このようにして入
力電力を制御して出力している。The PIN attenuator consists of a PIN (p-type semiconductor-insulating surface 10-type semiconductor structure) diode, which is inserted in parallel to the line. When the resistance of the PIN diode becomes low, the impedance of the line becomes low, and when it becomes 0, the incoming signal is reflected. Conversely, if the resistance of the PIN diode is increased, the signal will pass to the output side, and if the resistance is further increased, the signal will be reflected again. In this way, input power is controlled and output.
反射が増すと入出力側に増幅器を接続できないので1.
入出力側にハイブリッド・カプラを設け、反射した電力
は終端抵抗に吸収させてしまう。このようにするとRF
入力端子より入ってきた信号はPIN減衰器で反射して
も、RF端子に出てこないから、見掛は上枠性インピー
ダンス50Ωで終端したことになる。それゆえ縦続接続
が可能となり、入出力両側に増幅段を接続する。If the reflection increases, an amplifier cannot be connected to the input/output side, so 1.
A hybrid coupler is installed on the input and output sides, and the reflected power is absorbed by the terminating resistor. In this way, RF
Even if the signal coming in from the input terminal is reflected by the PIN attenuator, it does not come out to the RF terminal, so it appears to be terminated with an upper frame impedance of 50Ω. Therefore, a cascade connection is possible, with amplification stages connected on both the input and output sides.
従来例に相当する増幅段は、PINダイオードの代わり
にシングルエンドの増幅器が設けられ、ここで反射した
電力は入出力側に設けたハイブリッド・カプラで吸収し
て入出力のVSWRを良くしていたが、PIN減衰器の
場合も全く同様な構成であるが、補助端子を必要とする
点が異なる。The amplification stage corresponding to the conventional example has a single-ended amplifier instead of a PIN diode, and the power reflected here is absorbed by a hybrid coupler installed on the input/output side to improve the input/output VSWR. However, the PIN attenuator has exactly the same configuration, except that it requires an auxiliary terminal.
第3図は利得可変段のパッケージの内部図である。FIG. 3 is an internal diagram of the variable gain stage package.
図において、PINDiはPINダイオード、Rは終端
抵抗、Cはキャパシタを表す。In the figure, PINDi represents a PIN diode, R represents a terminating resistor, and C represents a capacitor.
12はリボン接続用の金リボンで、ハイブリッドカプラ
はセラミック、あるいはサファイア基板13と14上に
形成される。各部の配線はワイヤ15により行う。
二2B、3B
はそれぞれRF入力端子、RF出力端子である。12 is a gold ribbon for ribbon connection, and the hybrid coupler is formed on ceramic or sapphire substrates 13 and 14. Wiring of each part is performed using wires 15.
22B, 3B
are an RF input terminal and an RF output terminal, respectively.
4B、5Bは増幅器給電用端子で、例えばゲート端子を
、6B、7Bは増幅器給電用端子で、例えばドレイン端
子である。4B and 5B are amplifier power supply terminals, for example gate terminals, and 6B and 7B are amplifier power supply terminals, for example drain terminals.
88、9Bは補助端子で利得制御用端子である。Reference numerals 88 and 9B are auxiliary terminals and are gain control terminals.
第4図は増幅段と利得可変段を縦続接続した平面図であ
る。FIG. 4 is a plan view of an amplification stage and a variable gain stage connected in cascade.
図において、Aは増幅段、GCは利得可変段を表し、利
得可変段は本発明により縦続接続が可能となる。In the figure, A represents an amplification stage and GC represents a variable gain stage, and the variable gain stages can be connected in cascade according to the present invention.
〔発明の効果]
以上詳細に説明したように本発明によれば、増幅段と利
得可変段よりなる増幅器のそれぞれの段を別々のパンケ
ージに搭載して構成する場合、利得可変段においては、
その機能を生かすために必要な補助端子がパッケージに
設けられているため、縦続接続が可能となる。[Effects of the Invention] As explained in detail above, according to the present invention, when each stage of an amplifier consisting of an amplification stage and a variable gain stage is mounted in separate pancages, the variable gain stage has the following effects:
The package has the necessary auxiliary terminals to take advantage of its functionality, allowing cascade connections.
第1図(a)乃至+dlはそれぞれ本発明によるN続接
続可能なパフケージを用いた半導体装置の平面図と正面
図と側面図と側断面図、
第2図はパッケージに搭載する利得可変段の回路図、
第3図は利得可変段のパッケージの内部図、第4図は増
幅段と利得可変段を縦続接続した平面図、
第5図は従来例による縦続接続可能なパッケージの平面
図と正面図と側断面図である。
図において、
■は金属基体、 IAは金属国体、2.3はRF端
子、
4、 5. 6. 7はDC端子、
2A乃至7Aは絶縁物基体、
2B乃至7Bはリード片、
2C乃至7Cは絶縁物駒体、
8.9は補助端子
11は内部回路、 12は金リボン、13、1
4はセラミックまたはサファイア基板、15はワイヤ、
PINDiはPINダイオード、
Rは終端抵抗、 Cはキャパシタ、Aは増幅段、
GCは利得可変段を示す。
15. ¥−I閉
*−2c
IJ−J−フ ηアラ
#3Ii2T
γDノシトロール員町す1(a) to +dl are respectively a plan view, a front view, a side view, and a side sectional view of a semiconductor device using a puff cage capable of N-connection according to the present invention, and FIG. 2 is a diagram of a variable gain stage mounted on the package. Circuit diagram, Figure 3 is an internal diagram of the variable gain stage package, Figure 4 is a plan view of a cascade connection of an amplification stage and variable gain stage, and Figure 5 is a plan view and front view of a conventional package that can be connected in cascade. FIG. In the figure, ■ is a metal base, IA is a metal body, 2.3 is an RF terminal, 4, 5. 6. 7 is a DC terminal, 2A to 7A are insulating substrates, 2B to 7B are lead pieces, 2C to 7C are insulating pieces, 8.9 is an auxiliary terminal 11 is an internal circuit, 12 is a gold ribbon, 13, 1
4 is a ceramic or sapphire substrate, 15 is a wire, PINDi is a PIN diode, R is a terminating resistor, C is a capacitor, A is an amplification stage,
GC indicates a variable gain stage. 15. ¥-I closed*-2c IJ-J-F ηara#3Ii2T γD nositrol member town
Claims (1)
容器が金属蓋体によって気密封止される構造を有し、縦
続接続可能な端子を該金属容器の相対する2辺に、その
他の端子を該金属容器の相対する2辺以外の辺に具備し
てなることを特徴とする半導体装置。The semiconductor chip is mounted in a substantially rectangular metal container, and the metal container is hermetically sealed with a metal lid. Terminals that can be connected in cascade are placed on two opposing sides of the metal container, and other terminals are placed on opposite sides of the metal container. A semiconductor device characterized in that it is provided on a side other than two opposing sides of the metal container.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24120884A JPS61123156A (en) | 1984-11-15 | 1984-11-15 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24120884A JPS61123156A (en) | 1984-11-15 | 1984-11-15 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61123156A true JPS61123156A (en) | 1986-06-11 |
Family
ID=17070805
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24120884A Pending JPS61123156A (en) | 1984-11-15 | 1984-11-15 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61123156A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010013930A (en) * | 2009-09-11 | 2010-01-21 | Ykk Ap株式会社 | Outdoor structure |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59152649A (en) * | 1983-02-21 | 1984-08-31 | Nec Corp | High frequency semiconductor package |
JPS59172747A (en) * | 1983-03-22 | 1984-09-29 | Nec Corp | High frequency semiconductor device |
-
1984
- 1984-11-15 JP JP24120884A patent/JPS61123156A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59152649A (en) * | 1983-02-21 | 1984-08-31 | Nec Corp | High frequency semiconductor package |
JPS59172747A (en) * | 1983-03-22 | 1984-09-29 | Nec Corp | High frequency semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010013930A (en) * | 2009-09-11 | 2010-01-21 | Ykk Ap株式会社 | Outdoor structure |
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