JPH05136607A - Micro wave transistor for electric power amplification - Google Patents

Micro wave transistor for electric power amplification

Info

Publication number
JPH05136607A
JPH05136607A JP3299465A JP29946591A JPH05136607A JP H05136607 A JPH05136607 A JP H05136607A JP 3299465 A JP3299465 A JP 3299465A JP 29946591 A JP29946591 A JP 29946591A JP H05136607 A JPH05136607 A JP H05136607A
Authority
JP
Japan
Prior art keywords
fet
impedance
chip
resistance
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3299465A
Other languages
Japanese (ja)
Inventor
Yuji Oda
雄二 小田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3299465A priority Critical patent/JPH05136607A/en
Publication of JPH05136607A publication Critical patent/JPH05136607A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • H01L2924/30111Impedance matching

Abstract

PURPOSE:To obtain the improve structure for which the effect of the resistance insertion can be stably expected and to realize a stable micro wave amplifier even when the impedance is fluctuated by the dispersion of the capacitance value, etc., of an FET chip, an Au wire and a chip capacitor which are components, at an internal matching type FET. CONSTITUTION:In an envelope 101, an electric field-effect type transistor chip and a matching circuit to convert so as to match the impedance of the said transistor chip to the desired resistance are provided. The matching circuit includes a distribution constant circuit to provide a good conductivity thin metallic film on insulation substrates 14 and 104. At least two places of micro strip lines 14a and 104a to constitute the distribution constant circuit are constituted of the thin resistor film and the electric length of the micro strip line between the thin resistor films is about 1/4 of the wavelength at the frequency to be used.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電力増幅用マイクロ波
トランジスタ、特に外囲器内にインピーダンス変換回路
を有するいわゆる内部整合型トランジスタの構造に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a microwave transistor for power amplification, especially a so-called internally matching type transistor having an impedance conversion circuit in an envelope.

【0002】[0002]

【従来の技術】マイクロ波の増幅を行う装置として電力
増幅用GaAs電界効果型トランジスタ(以下GaAs
FETと略称する)は、従来から使用されてきた進行波
管型増幅器に代わって広く利用されている。電力増幅用
GaAsFETは一般には、ソース電極、ドレイン電
極、ゲート電極を有する微細なGaAs半導体チップが
金属やセラミックからなる外囲器にマウントされ、それ
ぞれの電極が外囲器に設けられた入出力リード端子、接
地用ベース金属に金属細線で接続されている。このよう
な電力増幅用GaAsFETは通常複数個接続して利用
されるが、それぞれのFETの入力、出力インピーダン
スはそれぞれのインピーダンスを有しており、したがっ
て単に接続するだけではFETの持つ能力を最大限に引
き出せない。そのため、各FETの段間には前段のFE
Tの出力インピーダンスと後段の入力インピーダンスを
整合させるために整合回路を必要とする。また、マイク
ロ波増幅器自体の入出力端子のインピーダンスは50オ
ームに合わせる事が一般であり、多段増幅器の初段FE
Tの入力インピーダンスおよび最終段FETの出力イン
ピーダンスを50オームに変換する必要がある。このよ
うな状況から、FET自体の入出力インピーダンスを5
0オームに設定した内部整合形FETと呼ばれる電力増
幅用GaAsFETが開発されている。
2. Description of the Related Art A GaAs field effect transistor for power amplification (hereinafter referred to as GaAs) is used as a device for amplifying microwaves.
The FET is abbreviated as “FET”, and is widely used in place of the conventionally used traveling-wave tube type amplifier. A power amplification GaAs FET is generally an input / output lead in which a fine GaAs semiconductor chip having a source electrode, a drain electrode, and a gate electrode is mounted on an envelope made of metal or ceramic, and each electrode is provided on the envelope. It is connected to the terminals and the base metal for grounding with thin metal wires. Normally, a plurality of such GaAs FETs for power amplification are connected and used, but the input and output impedances of each FET have their respective impedances. Therefore, simply connecting them maximizes the ability of the FET. I can't pull it out. Therefore, the FE of the previous stage is placed between each FET stage.
A matching circuit is required to match the output impedance of T with the input impedance of the subsequent stage. Also, the impedance of the input / output terminals of the microwave amplifier itself is generally adjusted to 50 ohms.
It is necessary to convert the input impedance of T and the output impedance of the final stage FET to 50 ohms. From such a situation, the input / output impedance of the FET itself should be 5
A power amplification GaAs FET called an internal matching type FET set to 0 ohm has been developed.

【0003】上記内部整合形FETは、入力出力インピ
ーダンスがほぼ50オームになるように外囲器の内部に
整合回路を設けたFETである。以下に従来の内部整合
型FETの構成の平面図について図3を用いて説明す
る。図中の101はメタルウオール型外囲器と呼ばれる
容器でこの中に半導体チップを始めとするすべての部品
が格納される。この外囲器は通常、銅などの金属ベース
101aと外部回路との接続のために用いられる入出力
端子101b、およびこの端子を支えるセラミック小片
101c、気密封じをするためのキャップがつけられる
金属枠101dからなる。102はGaAsFETチッ
プで表面にソース電極、ドレイン電極、ゲート電極が設
けられている。103はチップコンデンサと呼ばれる容
量素子で、高誘電体基板の表裏に金電極が設けられてい
る。104は分布定数回路が設けられた絶縁性基板(ア
ルミナ基板)であり、分布定数回路はマイクロストリッ
プライン104a、オープンスタブ104bなどからな
る。そしてこれらの部品は金(Au)ワイヤにより接続
され内部整合型FETは機能する。図4に、この内部整
合形FETの等価回路を示した。Auワイヤによるイン
ダクタンス、チップコンデンサによるキャパシタンス、
アルミナ基板上に設けられたマイクロストリップライ
ン、オープンスタブによりGaAsFETチップそのも
のの数オームといった低いインピーダンスが50オーム
近いインピーダンスへ変換される。図5には一例として
Xバンドで出力5Wを有する内部整合形FETの入出力
インピーダンスをスミスチャート表示したものを示す。
図5(a)は入力側のインピーダンスを、図5(b)
は、出力側のインピーダンスを表示している。これらの
図において周波数は9GHzから12GHzまで変化さ
せている。図中fL,fM,fHと示している点は、本
FETの使用されるべき周波数帯域の低いバンド端f=
9.5GHz、バンド中心周波数f=10GHz、高い
バンド端f=10GHzである。電力用FETの場合に
は、出力インピーダンスは必ずしも50オームに設定せ
ずに出力が最大となるインピーダンスへ変換するのが好
ましい。一方入力インピーダンスは50オームに変換す
るのが好ましいが、入出力間の相互作用(フィードバッ
ク効果)や、外囲器のサイズからくる制限により、周波
数帯域全体にわたって、50オームにするのは不可能で
ある。このような理由に因り、現実の内部整合形FET
のインピーダンスは図5(a),(b)に示したような
インピーダンス軌跡をえがく事になる。この例では、f
L,fM,fHにおけるインピーダンスはZL=70+
j0Ω、ZM=30+j0Ω、ZH=50−j25Ωで
ある。
The internal matching type FET is a FET in which a matching circuit is provided inside the envelope so that the input output impedance is approximately 50 ohms. A plan view of the structure of a conventional internal matching type FET will be described below with reference to FIG. Reference numeral 101 in the figure is a container called a metal wall type envelope in which all parts including a semiconductor chip are stored. This envelope is usually an input / output terminal 101b used for connecting a metal base 101a such as copper to an external circuit, a ceramic piece 101c for supporting this terminal, and a metal frame provided with a cap for hermetically sealing. It consists of 101d. A GaAsFET chip 102 has a source electrode, a drain electrode, and a gate electrode on the surface. Reference numeral 103 denotes a capacitive element called a chip capacitor, in which gold electrodes are provided on the front and back of a high dielectric substrate. Reference numeral 104 denotes an insulating substrate (alumina substrate) provided with a distributed constant circuit, and the distributed constant circuit includes a microstrip line 104a, an open stub 104b, and the like. Then, these parts are connected by a gold (Au) wire and the internal matching type FET functions. FIG. 4 shows an equivalent circuit of this internal matching type FET. Inductance by Au wire, capacitance by chip capacitor,
The microstrip line and the open stub provided on the alumina substrate convert the low impedance of the GaAsFET chip itself, such as several ohms, into an impedance of nearly 50 ohms. FIG. 5 shows, as an example, a Smith chart representation of the input / output impedance of an internally matched FET having an output of 5 W in the X band.
5 (a) shows the impedance on the input side, and FIG.
Shows the impedance on the output side. In these figures, the frequency is changed from 9 GHz to 12 GHz. The points indicated by fL, fM, and fH in the figure are the band edges f = of the low frequency band to be used by this FET.
9.5 GHz, band center frequency f = 10 GHz, and high band edge f = 10 GHz. In the case of a power FET, it is preferable that the output impedance is not necessarily set to 50 ohms, but the output impedance is converted to the maximum impedance. On the other hand, it is preferable to convert the input impedance to 50 ohms, but it is not possible to make it 50 ohms over the entire frequency band due to the interaction between the input and output (feedback effect) and the limitation caused by the size of the envelope. is there. Due to such a reason, the actual internal matching type FET
The impedance of FIG. 5 can be traced the impedance locus as shown in FIGS. 5 (a) and 5 (b). In this example, f
The impedance at L, fM, and fH is ZL = 70 +
j0Ω, ZM = 30 + j0Ω, and ZH = 50−j25Ω.

【0004】[0004]

【発明が解決しようとする課題】上に述べたようなFE
Tを接続した場合には前段のFETと後段のFETの間
にはインピーダンス不整合が生じ、FET同士の間でマ
イクロ波の反射が生じる。この場合、反射されたマイク
ロ波は、前段FETの動作に影響を与え、単にFETを
接続することから期待される特性が得られないばかり
か、発振現象や、入力を増やすと利得が向上するといっ
た入出力特性の異常現象が見られることがある。この様
な現象を抑制する施策の一つとして、入力回路に抵抗を
挿入する方法がある。この方法を採ると、FETの入力
インピーダンスは抵抗を挿入しない場合のインピーダン
ス(抵抗を挿入した所からFET側をみたインピーダン
ス)にこの抵抗値が加わった値になる。例えば前記例に
おいて10オームの抵抗を簡単のために外囲器のリード
端子根元に挿入した場合を想定した場合、fLではZL
=80(=70+10)+j0Ω、fMではZM=40
(=30+10)+j0Ω、fHではZH=60(=5
0+10)−j25Ωとなり、定在波比rの帯域におけ
る最大値は抵抗を挿入しない場合のrmax =1.67か
らrmax =1.6になる。このように定在波比rが小さ
くなるため、FET同士の間でマイクロ波の反射が少な
くなり、より安定した動作が可能となる。しかしなが
ら、マイクロ波帯のなかでもX帯といった高い周波数帯
域においては、FETチップ、インダクタンスを形成す
るAuワイヤの長さのばらつきなどによりインピーダン
ス軌跡も個々のFETで異なる。このため、例えば図6
に示したようなインピーダンス軌跡を抵抗挿入前に有し
たFET(ZL=80+j0Ω、ZM=50+j0Ω、
ZH=40−j20Ω)において同様の抵抗を挿入した
場合を想定すると、fL,fM,fHにおけるインピー
ダンスはそれぞれ、ZL=90+j0Ω、ZM=60+
j0Ω、ZH=50−j20Ωとなり定圧波比rの帯域
における最大値はrmax =1.8になり、抵抗をいれな
かった場合のrmax =1.64に比べかえって悪くな
る。本発明は、上記欠点を除去するためになされたもの
で、個々のFETのばらつきがあった場合にも、安定し
た動作が可能となる内部整合形の電力増幅用マイクロ波
トランジスタを提供することを目的とする。
FE as described above
When T is connected, impedance mismatch occurs between the front FET and the rear FET, and microwaves are reflected between the FETs. In this case, the reflected microwave influences the operation of the preceding FET, and not only the characteristics expected from simply connecting the FET cannot be obtained, but also the oscillation phenomenon or the gain is improved by increasing the input. Abnormal phenomena of input / output characteristics may be seen. As one of the measures for suppressing such a phenomenon, there is a method of inserting a resistor in the input circuit. If this method is adopted, the input impedance of the FET becomes a value obtained by adding this resistance value to the impedance when the resistor is not inserted (impedance as seen from the FET side from the position where the resistor is inserted). For example, in the above example, assuming that a resistance of 10 ohm is inserted at the root of the lead terminal of the envelope for the sake of simplicity, ZL is fL.
= 80 (= 70 + 10) + j0Ω, ZM = 40 for fM
(= 30 + 10) + j0Ω, fH at ZH = 60 (= 5
0 + 10) -j25Ω, and the maximum value in the band of the standing wave ratio r is from rmax = 1.67 when no resistor is inserted to rmax = 1.6. Since the standing wave ratio r is thus reduced, the microwaves are less reflected between the FETs, and more stable operation is possible. However, in a high frequency band such as the X band among the microwave bands, the impedance locus also differs among individual FETs due to variations in the length of the FET chip and the Au wire forming the inductance. Therefore, for example, as shown in FIG.
FETs (ZL = 80 + j0Ω, ZM = 50 + j0Ω, which have impedance loci as shown in FIG.
ZH = 40-j20Ω), assuming a similar resistance, the impedances at fL, fM, and fH are ZL = 90 + j0Ω and ZM = 60 +, respectively.
Since j0Ω and ZH = 50−j20Ω, the maximum value in the band of the constant pressure wave ratio r is rmax = 1.8, which is worse than rmax = 1.64 when no resistance is added. The present invention has been made in order to eliminate the above-mentioned drawbacks, and it is an object of the present invention to provide an internal matching type power amplification microwave transistor capable of stable operation even when there are variations in individual FETs. To aim.

【0005】[0005]

【課題を解決するための手段】本発明に係る電力増幅用
マイクロ波トランジスタは、外囲器内に電界効果形トラ
ンジスタチップと、該トランジスタチップのインピーダ
ンスを所望の抵抗に整合するように変換するための整合
回路を有する内部整合形電力用電界効果型トランジスタ
において、前記整合回路が絶縁性基板上に良導電性金属
薄膜を設けた分布定数回路を少なくとも含み、この分布
定数回路を構成するマイクロストリップラインの少なく
とも2か所が抵抗薄膜で構成され、かつ前記2か所の抵
抗薄膜間のマイクロストリップラインの電気長が、使用
する周波数における波長の約1/4である事を特徴とす
る。
A microwave transistor for power amplification according to the present invention is for converting a field effect transistor chip in an envelope and an impedance of the transistor chip to match a desired resistance. In the internally matched power field effect transistor having the matching circuit, the matching circuit includes at least a distributed constant circuit in which a thin metal film having good conductivity is provided on an insulating substrate, and a microstrip line forming the distributed constant circuit. Is formed of a resistance thin film, and the electrical length of the microstrip line between the two resistance thin films is about ¼ of the wavelength at the frequency used.

【0006】[0006]

【作用】本発明による内部整合型FETでは、FETチ
ップ、Auワイヤ、チップコンデンサの容量値等のばら
つきによりインピーダンスが変動しても、安定して抵抗
挿入の効果が期待でき、安定なマイクロ波増幅装置を提
供する。
In the internal matching type FET according to the present invention, even if the impedance varies due to variations in the capacitance value of the FET chip, Au wire, and chip capacitor, the effect of stable resistance insertion can be expected, and stable microwave amplification can be expected. Provide the device.

【0007】[0007]

【実施例】以下、本発明の一実施例につき図面を参照し
て説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0008】図1は一実施例の内部整合型FETの構成
を示す平面図、図中従来と変わらない部分については従
来と同じ符号を付けて示し、説明を省略する。図の14
は分布定数回路が設けられた絶縁性基板(アルミナ基
板)である。この分布定数回路はマイクロストリップラ
イン14a、オープンスタブ14bなどからなる整合回
路を含んでいる。さらに本発明の特徴である抵抗14
c、14dが2か所に形成されている。これらの抵抗値
50Ωの特性インピーダンスをもつマイクロストリップ
ラインを形成するアルミナ基板上のメタライズ膜の最上
層の金(Au)を選択的に除去することで形成される窒
化タンタル薄膜からなる。そしてこれらの2個の抵抗は
共に抵抗値が5Ωに設定されており、使用する周波数の
マイクロ波の実効波長の約1/4の距離を隔てて設けら
れている。図2にはこの内部整合形FETの等価回路を
示した。
FIG. 1 is a plan view showing the structure of an internal matching type FET according to an embodiment. In the figure, parts that are the same as those of the prior art are designated by the same reference numerals and the description thereof is omitted. Figure 14
Is an insulating substrate (alumina substrate) provided with a distributed constant circuit. This distributed constant circuit includes a matching circuit including a microstrip line 14a and an open stub 14b. Further, the resistor 14 which is a feature of the present invention
c and 14d are formed in two places. The tantalum nitride thin film is formed by selectively removing gold (Au), which is the uppermost layer of the metallized film on the alumina substrate forming the microstrip line having the characteristic impedance of the resistance value of 50Ω. The resistance value of each of these two resistors is set to 5Ω, and they are provided at a distance of about ¼ of the effective wavelength of the microwave of the frequency to be used. FIG. 2 shows an equivalent circuit of this internal matching type FET.

【0009】本発明によるFETの効果を見るために、
従来例で説明した場合と同様なケースについて説明す
る。まずFET側の抵抗の直前のマイクロストリップラ
インからFET側を見込んだインピーダンスが周波数f
L,fM,fHでそれぞれZL=70+j0Ω、ZM=
30+j0Ω、ZH=50−j25Ωとする。これらの
インピーダンスはそれぞれ挿入された5Ωの抵抗により
ZL=75+j0Ω、ZM=35+j0Ω、ZH=55
−j25Ωに変換される。さらに電気長1/4λのマイ
クロストリップラインによる変換を受けZL=33+j
0Ω、ZM=71+j0Ω、ZH=38+j17Ωに変
換される。さらに挿入された2段目の5抵抗によりZL
=38+j0Ω、ZM=76+j0Ω、ZH=43+j
17Ωに変換される。すなわち、このケースでの定在波
比rの帯域における最大値はrmax=1.5となる。つ
ぎに従来例で説明した第2のケースについて試算する。
すなわち、FETチップ、インダクタンスを形成するA
uワイヤの長さのばらつきなどにより同様な回路である
にもかかわらず、FET側の抵抗の直前のマイクロスト
リップラインからFET側を見込んだインピーダンスが
周波数fL,fM,fHでそれぞれZL=100+j0
Ω、ZM=50+j0Ω、ZH=40−j20Ωとす
る。この場合、先に述べたのと同様に2つの抵抗、1/
4λのマイクロストリップラインによる変換を受けZL
=29+j0Ω、ZM=50+j0Ω、ZH=51+j
21Ωに変換される。すなわち、このケースでの定在波
比rは帯域における最大値はrmax =1.7となる。以
上を纏めると抵抗を一切使用しない従来の内部整合形F
ETにおいては、2つのケースについて定在波比の値は
それぞれの周波数において
In order to see the effect of the FET according to the present invention,
A case similar to the case described in the conventional example will be described. First, the impedance looking into the FET side from the microstrip line immediately before the resistance on the FET side is the frequency f
ZL = 70 + j0Ω, ZM = for L, fM, and fH, respectively.
30 + j0Ω and ZH = 50−j25Ω. These impedances are ZL = 75 + j0Ω, ZM = 35 + j0Ω, ZH = 55 due to the inserted 5Ω resistors.
Converted to -j25Ω. Furthermore, it is converted by a microstrip line with an electrical length of 1 / 4λ, and ZL = 33 + j
It is converted into 0Ω, ZM = 71 + j0Ω, and ZH = 38 + j17Ω. Furthermore, ZL is inserted by the inserted 5th resistance in the second stage.
= 38 + j0Ω, ZM = 76 + j0Ω, ZH = 43 + j
Converted to 17Ω. That is, the maximum value of the standing wave ratio r in the band in this case is rmax = 1.5. Next, a trial calculation will be made for the second case described in the conventional example.
That is, A forming the FET chip and the inductance
Although the circuit is similar due to the variation in the length of the u wire, the impedance of the FET side from the microstrip line immediately before the resistance on the FET side is ZL = 100 + j0 at frequencies fL, fM, and fH, respectively.
Ω, ZM = 50 + j0Ω, and ZH = 40−j20Ω. In this case, two resistors, 1 /
ZL converted by 4λ microstrip line
= 29 + j0Ω, ZM = 50 + j0Ω, ZH = 51 + j
Converted to 21Ω. That is, the maximum value of the standing wave ratio r in this case in the band is rmax = 1.7. In summary, the conventional internal matching type F that does not use resistors
In ET, the standing wave ratio values for the two cases are

【0010】[0010]

【表1】 [Table 1]

【0011】および[0011] and

【0012】[0012]

【表2】 [Table 2]

【0013】に(図5a、図6で示されたところの入力
インピーダンスをもつFETを例に本発明の効果をあら
わすための定在波比)を示すようになり、2つのケース
においての最大定在波比rmax は1.7,2.0とな
る。また同様に10Ωの抵抗を挿入しただけの従来の抵
抗挿入型内部整合FETでは2つのケースにおいての最
大定在波比rmax は1.6,2.2となる。また本発明
によるところの2つの抵抗を1/4λ隔てて設けた新規
なる抵抗挿入型内部整合FETでは2つのケースにおい
ての最大定在波比rmax は1.5,1.7となり従来の
ように逆効果を生じることはない。
(Standing wave ratio for expressing the effect of the present invention, taking the FET having the input impedance shown in FIGS. 5a and 6 as an example), the maximum constant in two cases is obtained. The standing wave ratio rmax is 1.7 and 2.0. Similarly, in the conventional resistance insertion type internal matching FET in which a resistance of 10Ω is simply inserted, the maximum standing wave ratio rmax in the two cases is 1.6 and 2.2. Further, in the case of the novel resistance insertion type internal matching FET according to the present invention in which two resistors are provided at a distance of ¼λ, the maximum standing wave ratio rmax in the two cases is 1.5 and 1.7, as in the conventional case. It has no adverse effect.

【0014】[0014]

【発明の効果】本発明による内部整合型FETによれ
ば、FETチップ、Auワイヤ、チップコンデンサの容
量値等のばらつきによりインピーダンスが変動しても、
安定して抵抗挿入の効果が期待でき、したがって安定な
マイクロ波増幅装置が実現できる。
According to the internal matching type FET of the present invention, even if the impedance varies due to variations in the capacitance value of the FET chip, Au wire, chip capacitor, etc.,
A stable effect of resistance insertion can be expected, and thus a stable microwave amplification device can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る内部整合型電力FETの一実施例
を示す平面図、
FIG. 1 is a plan view showing an embodiment of an internal matching type power FET according to the present invention,

【図2】[図1]に示した内部整合型FETの等価回路
図、
2 is an equivalent circuit diagram of the internal matching type FET shown in FIG. 1;

【図3】従来例の内部整合型電力FETの平面図、FIG. 3 is a plan view of an internal matching type power FET of a conventional example,

【図4】[図3]に示した内部整合型FETの等価回路
図、
FIG. 4 is an equivalent circuit diagram of the internal matching type FET shown in FIG.

【図5】(a)、および(b)はいずれも夫々が内部整
合型FETの入力および出力インピーダンスのスミスチ
ャート表示図、
5 (a) and 5 (b) are respectively Smith chart display diagrams of the input and output impedances of the internal matching type FET,

【図6】別の内部整合型FETの入力インピーダンスの
スミスチャート表示図。
FIG. 6 is a Smith chart display diagram of the input impedance of another internal matching type FET.

【符号の説明】[Explanation of symbols]

14…絶縁性基板 14a…マイクロストリップライン 14b…オープンスタブ 14c、14d…抵抗 101…外囲器 102…GaAsFETチップ 104…分布定数回路 14 ... Insulating substrate 14a ... Microstrip line 14b ... Open stubs 14c, 14d ... Resistor 101 ... Envelope 102 ... GaAsFET chip 104 ... Distributed constant circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 外囲器内に電界効果形トランジスタチッ
プと、該トランジスタチップのインピーダンスを所望の
抵抗に整合するように変換するための整合回路を有する
内部整合形電力用電界効果型トランジスタにおいて、前
記整合回路が絶縁性基板上に良導電性金属薄膜を設けた
分布定数回路を含み、この分布定数回路を構成するマイ
クロストリップラインの少なくとも二か所が抵抗薄膜で
構成され、かつ前記抵抗薄膜間のマイクロストリップラ
インの電気長が、使用する周波数における波長の約1/
4である事を特徴とする電力増幅用マイクロ波トランジ
スタ。
1. An internal matching type power field effect transistor having a field effect transistor chip in an envelope and a matching circuit for converting the impedance of the transistor chip to match a desired resistance, The matching circuit includes a distributed constant circuit in which a thin metal film having good conductivity is provided on an insulating substrate, and at least two microstrip lines forming the distributed constant circuit are formed of resistive thin films, and between the resistive thin films. The electrical length of the microstrip line is about 1 / wavelength at the frequency used.
4. A microwave transistor for power amplification, which is 4.
JP3299465A 1991-11-15 1991-11-15 Micro wave transistor for electric power amplification Pending JPH05136607A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3299465A JPH05136607A (en) 1991-11-15 1991-11-15 Micro wave transistor for electric power amplification

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3299465A JPH05136607A (en) 1991-11-15 1991-11-15 Micro wave transistor for electric power amplification

Publications (1)

Publication Number Publication Date
JPH05136607A true JPH05136607A (en) 1993-06-01

Family

ID=17872925

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3299465A Pending JPH05136607A (en) 1991-11-15 1991-11-15 Micro wave transistor for electric power amplification

Country Status (1)

Country Link
JP (1) JPH05136607A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009303027A (en) * 2008-06-16 2009-12-24 Mitsubishi Electric Corp Stabilization circuit and amplifier
JP2010135722A (en) * 2008-11-05 2010-06-17 Toshiba Corp Semiconductor device
JP2014179681A (en) * 2013-03-13 2014-09-25 Mitsubishi Electric Corp High frequency power amplifier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009303027A (en) * 2008-06-16 2009-12-24 Mitsubishi Electric Corp Stabilization circuit and amplifier
JP2010135722A (en) * 2008-11-05 2010-06-17 Toshiba Corp Semiconductor device
JP2014179681A (en) * 2013-03-13 2014-09-25 Mitsubishi Electric Corp High frequency power amplifier

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