JPS61121586A - Signal processing circuit in video signal recording reproducing device - Google Patents

Abstract

PURPOSE:To obtain an equal picture quality by a small number of bits (resolution) compared with the fact that an A/D converting is executed concerning the whole band of the reproducing sampling signal by installing a high-pass filter at an input side of the A/D converter. CONSTITUTION:A reproducing sampling signal removed from a reproducing video signal output terminal 14 of a recording reproducing device 11 is respectively supplied to a high-pass filter 15 and a low-pass filter 16, and the frequency band is divided into two. A high-pass frequency component separated and filtered from the reproducing sampling signal by the filter 15 is supplied to an A/D converter 17 and A/D-converted. In the high-pass frequency component supplied to the converter 17, the band is narrow and the level is also low compared with the conventional component in which a reproducing sampling signal of the whole band is inputted, and therefore, bit accuracy can be increased for the part, and for this reason, when a luminance signal as a whole is generally processed by using the AD converter and a DA converter, the picture quality equal to the conventional quality can be obtained by a smaller number of bits than necessary 7-8 bits.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a signal processing circuit connected to a video signal recording/reproducing device, and in particular, sampling of video signals such as luminance signals with a shift of 180° for each field. A signal in which only the high frequency components of the reproduced signal are subjected to the resampling when a wideband reproduced video signal is obtained by sampling in pulses and then recording on a recording medium, and then resampling using field correlation during reproduction. Regarding processing circuits.

Conventional technology In general, helical scanning VTRs record video signals on a moving magnetic tape using a rotating head.
The rotary head reproduces the recorded edge video signal. The above-mentioned video and signals have a wide band with an upper limit frequency of about 4.2 MHz, for example, and in order to frequency-modulate this wide-band video signal, record it on a magnetic tape, and play it back, it is necessary to adjust the relative relationship between the head and the tape. It is well known that it is necessary to increase the speed to a predetermined value or higher and to use a high-performance head that is highly sensitive in a high frequency region.

However, in the case of home-use VTRs, the relative speed between the tape and head has to be much lower than the above-mentioned predetermined value due to demands for lower prices, smaller devices, and lighter weights. The recording and reproducing band becomes narrower than the original band of the video signal, which poses a problem in reproducing higher quality video signals.

Therefore, the present applicant previously proposed in Japanese Patent Application No. 107379/1983 to sample and record the input video signal at a frequency slightly higher than the upper limit frequency of the required frequency band of the input video signal, and when playing back, the sampling frequency is approximately equal to and 180 degrees each other
We proposed a video signal recording and reproducing device that alternately samples signals with different phases.

According to this proposed device, even if the recording/reproducing device has a narrow recording/reproducing band, it is possible to obtain a reproduced video signal with a wider band.

Problems to be Solved by the Invention However, according to the above-mentioned video signal recording and reproducing apparatus proposed by the present applicant, in order to obtain two types of reproduced sampling signals having a time difference of one field from each other in the reproduction system, field A memory circuit is required, and if a random access memory (RAM) is used as the field memory circuit, an AD converter is required at its input stage, and a DA converter is required at its output stage. Here, generally, a wideband luminance signal is input as an input video signal to an AD converter and a DA converter.
When signal processing is performed using each converter, a 7-bit to 8-bit converter is required, the clock pulse is set at a high frequency of about 5 MHz, and a parallel comparison type AD converter is used. This parallel comparison type AD converter has the advantage of extremely fast AD conversion speed and no need for a sample and hold circuit, but on the other hand, the number of components such as comparators increases exponentially as the resolution increases, resulting in higher costs. There was also a problem in that the amount increased exponentially.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a signal processing circuit for a video signal recording/reproducing apparatus that solves the above problems by providing a high-pass filter on the input side of an AD converter.

Means for Solving the Problems The signal processing circuit in the video signal recording and reproducing apparatus according to the present invention divides the frequency band of the reproduced sampled signal reproduced from the recording medium into two using first and second filter circuits, and A first filter circuit is provided on the input side of the AD converter to pass one high frequency component of the reproduced sampled signal. The above-mentioned sampling signal is a signal obtained by sampling an input composite video signal such as a luminance signal using a sampling pulse whose phase is shifted by "iao" for each field.This sampling signal reproduced from a recording medium is the above AD converter.

Using a field memory and a DA converter, two types of reproduced sampling signals having a time difference of one field are obtained, and these two types of reproduced sampling signals are alternately used at a cycle that is 1/2 times the cycle of the sampling pulse. Re-sampling is performed to selectively output.

As a result, the circuit of the present invention adds the low frequency component of the reproduced sampled signal that has been filtered by the second filter circuit to the high frequency component obtained by resampling, without performing the resampling. This mixed signal is output as a reproduced composite video signal.

Effect The signals supplied to the above AD converter and DA converter are:
Only the high frequency component of the reproduced sampled signal is filtered by the first filter circuit, and the band of the input signal is narrower than when the entire band of the reproduced sampled signal is supplied.

In addition, the high frequency component supplied to the AD converter is, for example, the high frequency component of the luminance signal, but this is because the luminance signal originally transmitted from the television broadcasting station is the square of the frequency characteristic shown in Figure 4. Passed through a sine wave filter circuit,
As shown in the figure, -2.5dB at 1.5MHz,
-8dB attenuation at 2.5MHz. In addition, the above-mentioned high frequency components are attenuated by the VTR's recording and reproducing characteristics themselves, and furthermore, the
It is also attenuated by the white/dark clip circuit. This white/dark clipping circuit clips the overshoot and undershoot portions of large-amplitude high frequency components (edge portions) that would result in overmodulation if the pre-emphasized luminance signal was frequency modulated as is.

In other words, the high frequency components of the reproduced sampled signal supplied to the AD converter have a narrower band and a lower level compared to the conventional method, in which a reproduced sampled signal of the entire band is input. Therefore, the number of bits is smaller than the 7 to 8 bits that are generally required when processing the entire luminance signal using an AD converter or DA converter. image quality can be obtained. According to the inventor's experimental results, the detection limit is 6 pits,
The allowable limit is 5 bits.

Therefore, it is possible to use an AD converter and a DA converter having a smaller number of bits than conventional ones, for example, 5 bits. However, in this case, in a large area portion with a relatively low frequency, the C/N decreases at pit boundaries due to the influence of noise even if the number of bits is within the allowable limit. That is, the quantization error due to noise superimposed near the center level of the high frequency component of the reproduced sampled signal occurs over a long period of time in the large-area portion, and is therefore easily noticeable. Therefore, the AD converter and the DA converter are configured to perform weighting,
A high resolution of about 6 bits is set only in the vicinity of the center level, and a resolution of about 5 bits is set for the other levels.

Embodiments of the present invention will be described below with reference to FIGS. 1 to 3.

Embodiment FIG. 1 shows a circuit diagram of a video signal recording and reproducing apparatus having an embodiment of the circuit of the present invention. First, to explain the operation during recording, a composite iron image signal, such as a luminance signal, input to the input terminal 1 is supplied to the synchronization signal separation circuit 3 through the switch circuit 2 connected to the terminal R. After separating the horizontal synchronization signal and vertical synchronization signal at , the horizontal synchronization signal is supplied to a phase locked loop (PLL) 4 and a timing generator 5, respectively, and the vertical synchronization signal is supplied to the timing generator 5. The PLL 4 is phase sensitive to the horizontal synchronizing signal, and generates and outputs a sampling pulse with a sampling frequency [S] that is a natural number multiple of the horizontal scanning frequency "H" and satisfies the following equation.

[S→fL+fu, (1) (In equation (1), fL is a constant frequency of about 0.5 MHz to IMHz, and fU is the upper limit frequency of the required frequency band of the reproduced luminance signal) This sampling pulse is the timing generator 5 On the other hand, the signal is supplied to the terminal 6a of the switch circuit 6, and the phase of the signal is inverted by the inverter 7 (with a 180° phase difference), and the signal is supplied to the terminal 6b of the switch circuit 6. The switch circuit 6 is a recording/reproducing device 11 which will be described later.
The well-known head switching pulse, which is a symmetrical square wave with a two-field period, is branched and applied as a switching pulse from the output terminal 13, and is switched and connected for each field.

As a result, the switch circuit 6 has 180 pixels per field.
A switch circuit 8 alternately selects and outputs two types of sampling pulses with a frequency fS whose phases are different by degrees.
is supplied to the terminal 8a of the terminal 8a. A DC voltage element Vc is applied to a terminal 8b of the switch circuit 8. On the other hand, the timing generator 5 controls the horizontal blanking period and the vertical blanking period of the input composite video signal during recording. It generates a pulse that becomes the first logical value in phase synchronization with the start of the erasure period and becomes the second logical value during the other period, and outputs this to the switch circuit 8 as a switching pulse. As a result, the switch circuit 8 selectively outputs the input DC voltage Vcc of the terminal 8b to the switch circuit 9 during both the horizontal and vertical blanking periods to keep it on, and on the other hand, except during the blanking period. During the period (video period), the input sampling pulse of the terminal 8a is selectively outputted to the switch circuit 9.

As a result, the switch circuit 9 alternately turns on and off every half cycle of the sampling pulse during the video period of the input composite video signal, and applies the input composite video signal during the on period to the hold capacitor 10. . Therefore,
A sampled signal obtained by sampling the signal of the video period at the sampling frequency [S is taken out from the hold capacitor 10 and connected to the recorded video signal input terminal (existing V
The signal is supplied to the input terminal (input terminal) 12 of the luminance signal recording system of the TR.

Furthermore, since the switch circuit 9 is continuously on during the blanking period, at least the synchronization signal of the input composite video signal is supplied to the recording video signal input terminal 12 without being sampled.

Here, as is clear from equation (1) above, the sampling frequency fS is a frequency higher than the upper limit frequency ru of the required frequency band of the reproduced composite video signal by the frequency f, and this frequency "L" is the upper limit frequency. 0.5M HZ lower than ru
The frequency is approximately 1 MHz. Therefore, due to the above sampling, the aliasing frequency spectrum becomes the upper limit frequency fu
It mixes in the frequency range from 0 to frequency fL, but from 0 to r
There is no aliasing frequency spectrum in the frequency range up to L, and the signal is transmitted as it is without being interfered with by other signals. The above frequency "L" is the frequency that can ensure the minimum necessary vertical resolution, 0.5M Hz ~ 1
It is selected to be around MHz.

The recording and reproducing device 23 is an existing narrow band VTR with a horizontal resolution of, for example, about 240 lines, and the above-mentioned sampled signal is recorded on a magnetic tape through a well-known recording system, and is further reproduced from the magnetic tape.

The recording/reproducing device has a well-known configuration and is not directly related to the gist of the present invention, so a detailed illustration thereof will be omitted (if necessary, the detailed configuration can be found in Special G + 1984-14).
See No. 728'6. ).

Next, the operation during playback will be explained. The reproduced sampled signal is taken out from the reproduced video signal output terminal 14 and supplied to the synchronizing signal separation circuit 3 through the switch circuit 2 which is switched and connected to the terminal P side. The horizontal synchronization signals in the reproduced sampling signal are respectively supplied to the PLL 4° timing generator 5, and as in the case of recording, sampling pulses with a frequency fs that satisfies the above equation (1) at a frequency that is a natural number multiple of the horizontal scanning frequency rH are generated. occurs. Further, the timing generator 5, which is supplied with both horizontal and vertical synchronizing signals, generates pulses of different logic values during the blanking period and the video period of the reproduced sampling signal. Furthermore, the timing generator 5 generates a pulse with a frequency twice as high as the frequency "S" and a pulse with a vertical scanning period, and supplies them to the field memory circuit 19, which will be described later, as a write/read control pulse and a load pulse, respectively. .

Further, the reproduced sampled signal taken out from the reproduced video signal output terminal 14 of the recording/reproducing device 11 is supplied to a high-pass filter 15 and a low-pass filter 16, respectively, and its frequency band is divided into two. The reproduced sampled signal is separated and filtered by a high-pass filter 15, and the high-frequency components above frequency 11 are supplied to an AD converter 17, where they are analog-to-digital converted. At the same time, the low frequency components below the frequency fL, which are separated and filtered from the reproduced sampled signal by the low pass filter 16, are filtered out by the switch circuit 18.
is supplied to terminal 18b of.

The high-pass filter 15 and the AD converter 17 constitute a main part of one embodiment of the circuit of the present invention, and the AD converter 17 has a configuration as shown in FIG. 2, for example. In FIG. 2, an analog signal coming into input terminal 30 (i.e.
The number of high-frequency components of the reproduced sampled signal extracted from the high-pass filter 15 is 2m-1 (where l satisfies the formula 2+11=2'' when the resolution of the AD converter 17 is n bits). integer) comparators 311 to 312 m −
+ is supplied to each one input terminal. On the other hand, input terminal 3
2, 2111 resistors R+=R2tn are connected in series to the ground terminal, and this series circuit has a reference voltage VRE.
F is applied. As a result, the comparators 311 to 3
Each other input terminal of 12 m-+ has resistors R1 to R2.
21 reference levels having mutually different values obtained by resistor-dividing the reference voltage VRE t- are supplied by m.

Comparators 31+ to 312m-+ compare the levels of the input analog signals and the reference level, respectively, and the obtained high-level or low-level signals are supplied to the decoding circuit 33, where they are converted into n-bit digital signals. Output after conversion.

Here, if the reference voltage VRE F is divided into 21 equal parts by the resistors R1 to Rzm, the circuit shown in Figure 2 will have the configuration of a parallel comparison type AI) converter with a resolution of n bits, which is well known in the past, and the vertical axis When the input analog signal level and the value (quantization step number) indicated by the input signal of the decoding circuit 33 are plotted on the horizontal axis, a linear characteristic as shown by the solid line in FIG. 3 is shown.

On the other hand, the AD converter 17 uses the reference voltage VRE t:
The m-th resistor Rm, which determines the reference level at the midpoint of the voltage range of resistors Rm-+ and Rt from which the reference levels immediately above and below are taken out, for example.
A feature is that each value of n÷1 is selected to obtain a resolution greater than n bits of resolution. As a result, the input analog signal level vs. quantization step number characteristic of the AD converter 17 becomes as shown by the broken line ■ in FIG. Weighting is performed so that In Figure 3, the range from a to b has a resolution of n.
In the range of the number of quantization steps greater than bits, this varies by the number of resistors such as resistors RTn-+ to Rm, u whose values are chosen such that the resolution is greater than n bits. As a result, for example, in an AD converter where n is "5" and the resolution is 5 bits, if you want to obtain AD conversion characteristics with a resolution of 6 pits in two steps above and below the center reference level, the conversion rate will be 15.1.
6. The value of the 17th resistor Rm-+ to Rm+1 is selected to be 1/2 the value in the case of 5 bits.

Returning to FIG. 1 again, the output digital signal of the AD converter 17 is supplied to the field memory circuit 19, where it is delayed by one field and then supplied to the terminal 20b of the switch circuit 20. circuit 1
9 is supplied to the terminal 20a of the switch circuit 20 without passing through it. The field memory circuit is composed of a RAM, an address counter, and the like. The switch circuit 20 is applied with a sampling pulse of sampling frequency "S" taken out from the switch circuit 8 as a switching pulse.
The output signal (pixel data) of the AD converter 17 which enters the terminal 20a during the half cycle 1/(2fs)ffl and the terminal 2
The 1-field delay signal from one field memory circuit input to 0b is alternately selected and output.

As a result, the switch circuit 20 outputs data to each intermediate position of each pixel data (sample point) of the field currently being reproduced.
When each pixel data of one field before is inserted, that is, considering the field correlation, a pixel data string with a sampling frequency of 2 fs is substantially taken out, and the DA converter 21
supplied to

The signal is converted into an analog signal by the 0AVl converter 21, and a resampled signal substantially sampled at a sampling frequency of 2 fs is extracted and then supplied to the mixing circuit 24 through the buffer amplifier 22 and the switch circuit 23. .

On the other hand, the output pulse of the timing generator 5 is applied to the switch circuit 23, which is turned off during the blanking period and turned on during the video period, and is applied to the switch circuit 18 through the inverter 25.

Further, the playback signal taken out from the playback video signal output terminal 14 of the recording/playback device 11 is transmitted to the terminal 1 of the switch circuit 18.
8a, while the low pass filter 16 is supplied as described above.
is supplied to the terminal 18 of the switch circuit 18 after separating and filtering only the low frequency components below the frequency fL.
b. The switching circuit 18 is controlled by the output pulse of the inverter 25, and the terminal 18b is connected to the terminal 18b side during the video period, and the terminal 1 is connected to the terminal 18b side during the horizontal and vertical blanking periods.
They are respectively switched and connected to the 8a side. The output signal of the switch circuit 18 is supplied to the mixing circuit 24 through a delay circuit 26 for time adjustment. As a result, from the mixing circuit 24 to the output terminal 27, during the video period, the resampled signal of the high frequency component above the frequency fL is mixed with the low frequency component in which there is no aliased frequency spectrum due to sampling below the frequency "L". A signal is extracted, and a synchronization signal, etc., which is not sampled or resampled during both horizontal and vertical blanking periods, is extracted.

Note that the present invention is not limited to the above embodiments; for example, fs may be an odd multiple of fH/2, and sampling and resampling may be performed for the synchronization signal section.
Furthermore, various modifications are possible, such as integrating an external circuit of the recording/reproducing device 11 into the VTR. Furthermore, when combined with other types of VTRs (other than PS type), the biggest difference in emphasis is the white clip level.

Visually, the image quality can be improved by increasing the polygonal line of the characteristic curve shown in Figure 3 by 2 or 3 steps depending on the difference in dark clip level or the difference in tolerance for business use, etc. becomes possible. In this case, it goes without saying that by setting the bit precision to 6 bits or 7 bits, more fine-grained adjustment becomes possible.

Effects of the Invention As described above, according to the present invention, since a high-pass filter is provided on the input side of the AD converter, the number of bits ( It is possible to obtain equivalent image quality at the same resolution (resolution), and the center level (resolution) of the input reproduction sampling signal of the AD converter
Since the resolution near the DC level is weighted to be higher than that of other level parts, it is possible to reduce the influence of noise superimposed near the center level.
The D converter can be configured with an even smaller number of bits, and when the AD converter is configured as a parallel comparison type, the number of resistors and comparators can be reduced, resulting in an inexpensive configuration. It has the following.

[Brief explanation of drawings]

FIG. 1 is a circuit system diagram of a recording/reproducing apparatus equipped with an embodiment of the circuit of the present invention, FIG. 2 is a circuit system diagram showing an embodiment of the main part of the circuit of the present invention, and FIG. 3 is a diagram shown in FIG. 2. FIG. 4, which is a characteristic diagram for explaining the operation of the circuit system, is a frequency characteristic diagram of an example of a conventional filter. 1...Input terminal, 2, 6, 8, 9, 18, 20°23
...Switch circuit, 3...Synchronization signal separation circuit, 5.
... Timing generator, 10... Hold capacitor, 11... Recording and reproducing device, 12... Recorded video signal input terminal, 13... Head switching pulse output terminal, 14... Playback video signal output terminal, 15...
High-pass filter, 16...Low-pass filter, 17...A
D-weird! IA device, 1...Field memory circuit, 21
...DA converter, 24...Mixing circuit, 26...Delay circuit, 27...Reproduction composite video signal output terminal, 311
~312 m-+... Comparator, 33... Decoding circuit. Patent applicant: Victor Company of Japan Co., Ltd. Figure 3 Figure 4 Peripheral fluid number (MH2)

Claims (2)

[Claims] (1) Recording the sampled signal obtained by sampling an input composite video signal such as a luminance signal using a sampling pulse whose phase is shifted by 180 degrees for each field on a recording medium,
Two types of reproduced sampled signals having a time difference of one field from each other are obtained from the reproduced sampled signal reproduced from the recording medium using an AD converter, a field memory, and a DA converter, and these two types of reproduced sampled signals are The video signal recording and reproducing apparatus performs resampling of alternately selecting and outputting a signal at a period 1/2 times the period of the sampling pulse, wherein the frequency bands of the reproduced sampled signal reproduced from the recording medium are first and second frequency bands. The first filter circuit that divides the reproduced sampled signal into two by a second filter circuit and filters the high frequency component of the reproduced sampled signal is provided on the input side of the AD converter. The low frequency component of the reproduced sampled signal filtered by the second filter circuit is mixed with the high frequency component obtained without performing the resampling, and the mixed signal is used as a reproduced composite video signal. A signal processing circuit in a video signal recording and reproducing device, characterized in that the signal processing circuit is configured to output. (2) The AD converter is configured such that, among the number of reference levels corresponding to the number of bits of the AD converter, a reference level of 1/2 of the entire reference level range is approximately equal to the center level of the input analog signal. and at least two reference levels above and below the reference level are set to values based on a larger resolution than the remaining reference levels, and are configured to output a digital signal weighted with respect to the input analog signal. , the DA converter also converts the AD to the input digital signal.
2. A signal processing circuit in a video signal recording/reproducing apparatus according to claim 1, wherein the signal processing circuit is configured to output the same weighted analog signal as that of the converter.