JPS6194477A - Recording and reproducing device for video signal - Google Patents

Abstract

PURPOSE:To improve a horizontal resolution in a home VTR and to obtain a reproduction signal in a wide frequency band by changing an address in memory at every two field by certain value. CONSTITUTION:An input composite video signal is 1st signal generation means 2 into a signal whose phase is different by 180 deg. at every field sampled 3 by the converted output, then recorded on a recording medium through a recording means 4 and reproduced through a reproduction means 5. The reproduction signal is converted into picture element data by an A/D converter 6, and supplied to a memory 7. At this time an address designating means 8 gives alternately read and write addresses to the memory 7 and changes relatively the relation between respective high order lines in add and even fields and addresses by one address. Then different reproduction sampling signals are simultaneously generated 9 by picture element data and that delayed by one field in the memory 7. Moreover the signal similar to a conversion means 2 is generated 2nd signal generation means 11 and given to a re-sampling means 10 as a switching means, thereby introducing a composite video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video signal recording and reproducing device, and in particular to a sampling method obtained by sampling an input composite video signal at a frequency slightly higher than the upper limit frequency of its required frequency band. Two signals are recorded on a recording medium and have a time difference of one field from each other during playback.
The present invention relates to a video signal recording and reproducing apparatus that obtains a reproduced video signal by synthesizing reproduced sampled signals of different types alternately and time-series for each sample point.

Conventional technology In general, helical scanning VTRs record video signals on a moving magnetic tape using a rotating head.
The rotary head reproduces the recorded video signal. The above-mentioned video signal has a wide band with an upper limit frequency of about 4.2 MHz, for example, and in order to frequency-modulate this wide-band video signal, record it on a magnetic tape, and play it back, it is necessary to use a head.
It is well known that it is necessary to increase the relative speed between the tapes to a predetermined value or higher, and to use a high-performance head that is highly sensitive in a high frequency range.

However, in the case of home-use VTRs, the relative speed between the tape and head has to be much lower than the above-mentioned predetermined value due to demands for lower prices, smaller devices, and lighter weights. The recording and reproducing band becomes narrower than the original band of the video signal, which poses a problem in reproducing higher quality video signals.

Therefore, the present applicant previously proposed in Japanese Patent Application No. 107379/1983 to sample and record the input video signal at a frequency slightly higher than the upper limit frequency of the required frequency band of the input video signal, and when playing back, the sampling frequency is approximately equal to and 180 degrees each other
We proposed a video signal recording and reproducing device that alternately samples signals with different phases.

According to this proposed device, even if the recording/reproducing device has a narrow recording/reproducing band, it is possible to obtain a reproduced video signal with a wider band.

Problems to be Solved by the Invention However, in the above-mentioned proposed device, the reproducing system delays the reproduced sampled signal by one field using a field memory, and the reproduction system delays the reproduced sampled signal by one field. Alternately synthesizes (resamples) the reproduced sampled signal from one field before and the currently reproduced sampled signal for each sampling point in time series.
Because of this configuration, the edges of the image in the horizontal direction may become jagged for video signals without vertical correlation.

This is especially true when the field memory is specified as an absolute address for a line, that is, the lower address of the memory address specifies the address based on the number of samples per line, and the upper address corresponds one-to-one to the line. If this happens, whisker-like jagged edges may appear on the horizontal edges of a rectangular image with a brightness different from that of the background, or an image with no vertical correlation, such as diagonal lines.

For example, as shown in FIG. 14(A), the third . Each pixel data of the fourth line L3, L14 is black, and all the pixel data of the other lines of the odd field are white. As shown in (B), the second even field
Each pixel data of the 66th line L266 is black, and all the pixel data of the other lines of the even field are white. Therefore, as shown in FIG. 14(C), for the video signal of a black rectangular image with a white background, , when writing and reading are performed in a one-to-one correspondence between the upper addresses (line addresses) and lines of the field memory, the third line of the odd field is the 266th line one field before when the black pixel data of 3 is reproduced. It is added and synthesized alternately with the black pixel data of L266, and the fourth pixel data of the odd field, in L4.
When reproducing black pixel data, the 267th pixel of one field before
Since they are added alternately to the white pixel data of line L267, when the fourth line 3 is reproduced, white and black pixel data appear alternately, as shown in FIG. 15(A).

Similarly, when reproducing the 267th line L267 of an even field, the black pixel data of the fourth line L4 one field before is added and synthesized alternately for each sample point, so that the white and black pixel data appear alternately. As a result, the reproduced image appears to have jagged edges in the horizontal direction at lines 3.4, 266.267, as shown in FIG. 15(C).

Also, 1st. Second. FIG. 16(A) shows pixel data of six lines from the top of the third field.

In the case of video signals of diagonally shaded images as shown in (B) and (C), when each pixel data of the second field is synthesized alternately in time series, a pixel data string as shown in FIG. 17(A) is obtained. obtained, and the second. When each pixel data of the third field is synthesized alternately in time series, a pixel data string as shown in FIG. 17(B) is obtained. As shown in the figure, a large step-like pattern appears instead of a diagonal line.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a video signal recording and reproducing device that solves the above-mentioned problems by changing the write address or read address of the memory by a constant value once every two fields. do.

Means for Solving the Problems FIG. 1 is a block diagram showing the configuration of the apparatus of the present invention. In the figure, the composite video signal (
The luminance signal) is supplied to the first signal generating means 2 and the sampling means 3, respectively. The first signal generating means 2 generates a signal having a sampling frequency fS related to the horizontal scanning frequency fH of the input composite video signal, the phase of which is 1 of the input composite video signal.
A signal that differs by 180° is generated for each field. The sampling means 3 converts the input composite video signal into the first signal generating means 2.
sampled by the output signal of

The sampled signal taken out by the sampling means 3 is recorded on a recording medium by the recording means 4 and reproduced by the reproducing means 5. The recording means 4 and the reproducing means 5 have conventionally known configurations. Signal reproduced by the reproduction means 5 (reproduction signal)
is supplied to the addressing means 8 and the second signal generating means 11, respectively, and is also supplied to the AD converter 6, where it is analog-to-digital converted into pixel data, and then stored for one field. The signal is supplied to a memory circuit 7 having a capacity and a reproduced sampling signal generating means 9, which will be described later. The reproduction signal is also supplied to the addressing means 8, which alternately generates a write address and a read address and supplies them to the memory circuit 7. The relationship between the address and the line is generated so as to be relatively different by one address compared to the relationship between the upper address and the line of the same one of the read address and write address in the even field as described above.

The pixel data read out after being delayed by one field by the memory circuit 7 is supplied to the reproduced sampling signal generating means 9. The reproduced sampling signal generating means 9 simultaneously generates and outputs first and second reproduced sampling signals having a relative time difference of one field.

Further, the second signal generating means 11 generates from the reproduced signal a signal having the same frequency fS as the output signal of the first signal generating means 2 and having a phase different by 180° for each field of the reproduced signal. The resampling means 10 is supplied with the output signal of the second signal generating means 11 as a switching signal, and alternately outputs the first and second reproduced sampling signals from the reproduced sampling signal generating means 9 every half cycle. Selectively output to the output terminal 12. As a result, the output terminal 12 receives a reproduced composite video signal that has been resampled at a frequency of substantially 2fS.

The sampling frequency of the action reproduced composite video signal is substantially 2 rs
Therefore, a broadband reproduced video signal can be obtained.

In addition, according to the present invention, since the addressing means 8 makes the upper address corresponding to the line of the write address or read address in the odd field different from that in the even field by one address, the vertical correlation Since the jaggedness of the horizontal edges of the neutral image is reduced to one line, which is half of that of the conventional image, the jaggedness becomes almost invisible visually.

For example, as shown in FIG. 2(A), an odd field has two adjacent 3rd . The fourth line L3, L4 consists of all black pixel data, and the remaining lines L+, L2,
Each pixel data of Ls to L263 is an image in which all are white, and the even field is the 266th pixel data as shown in FIG. 2(B).
Line L266 consists entirely of black pixel data, and the remaining lines L264'+L265, L267~L
Assuming that all of the 525 pixel data are white images, the reproduced image will look like the image shown in FIG. 14(C). In this image, there is no vertical correlation between lines L265 and La, and there is no vertical correlation between lines L4 and L267. For the pixel data of such an image,
In the odd field, the addressing means 8 indicates that the upper address of the write address of the memory circuit 7 corresponds one-to-one with the line, A+ and A2 in FIG. 2(A).

..., as shown by A263, and in the even field, the upper address of the write address is one address added to the line as shown in FIG. 2(B) by A2, A3, ..., A263, A+. address of the value (for example, line L264 is the top line in an even field, and adding 1 to the original address A1 results in A2
becomes. ), and the read address is generated with its upper address corresponding to the line in one-to-one correspondence throughout all fields.

As a result, during the reproduction period of the sampled signal of line L266, the video signal of line L266 and the video signal of line L3, which is one field before this, are alternately selected to the output terminal 12 every period 1/(2fS). However, since the pixel data of both lines are both black, the image is entirely black during the reproduction period of that one line, as shown in FIG. During the period, the upper address of the read address of the memory circuit 7 is A4,
Black pixel data on line L4 written at address A4 one field ago is read out from memory circuit 7. On the other hand, since line L267 is white pixel data,
During the reproduction period of line L261, (La) is shown in Fig. 3 (A).
As shown by +1267, a white image on line L267 and a black image on line L4 appear alternately every period 1/(2fS).

Also, during the sampling signal reproduction period of each line L265, L268, the upper address of the read address of the memory circuit is A2, As, and from the memory circuit 7, the line L2. Since the pixel data of L5 is read out, a white image appears as shown in FIG. 3(A).

On the other hand, during the period of reproducing the sampling signal of line L3 of the odd field, the upper address of the read address of the memory circuit 7 is set to A3, and the pixel data of line L3 is black as shown in FIG. 2(A). On the other hand, since the pixel data of line 1265 (conventionally, this was 1266) one field before read from address A3 is white as shown in the same figure (B), during the sampling signal reproduction period of line L3 As shown by (L265)+13 in FIG. 3(B),
A black image on line L3 and a white image on line L265 appear alternately every period 1/(2fS).

Furthermore, during the reproduction period of the sampling signal of line L4, the upper address of the read address of the memory circuit 7 is set to A4, and the black pixel data of line 1266 written one field ago from the memory circuit 7 to address A4. is read out, a single horizontal black line appears on the playback screen, as shown by (1266)+La in FIG. 3(B). During the next sampling signal reproduction period of line L5, the upper address of the read address of memory circuit 7 is set to A5, so from memory circuit 7, the white of line L267 written one field ago to address pixel data is read out. Therefore, during this regeneration period, the lines Ls, L
267 images appear alternately every period 1/(2fS), but the line Ls.

Both images of L267 are white, so in Figure 3 (B) (12
A single horizontal white line appears on the playback screen as shown by 67>+Ls.

Therefore, the final reproduced image has lines 2 to Ls, 12
In the vicinity of 65 to 268, as shown in FIG. 4, alternating white and black images, ie whisker-like jagged edges, occur in one line each at the top and bottom of a black rectangle with a width of two lines. However, compared to the conventional one shown in FIG. 15(C), the width of this jagged line is only one line, which is half the width of the conventional one, and it is hardly noticeable visually.

In addition, as shown in FIGS. 5(A) and (B), FIG. 2(A)
, For the video signal (especially the luminance signal) of the same image as the image shown in (B), the upper address of the write address corresponds one-to-one to the line in both odd and even fields, while the read address The upper addresses of are At, A2 for lines Ll l L21..., L263 in odd fields.

..., one-to-one correspondence between A263 and the line, and
For even fields, lines 1264, 265,
....

A2. for L524 and L525. , A3 ,
..., A263.

Even if the relationship between Aa, the read address of the odd field, and the line is increased by one address, the same result as in the case of FIG. 2 will result. That is, during the sampling signal reproduction period of line L265 of an even field, the upper address of the read address of the memory circuit 7 is A3, and the address A
Since the black pixel data of line 3 is written in line 3, as shown by (L3)+1265 in FIG. 6(A),
A white image on line L265 and a black image on line L3 appear alternately. Also, lines 1266, 126
7, the upper addresses of the read addresses of the memory circuit 7 are Aa and As, and the line L
Since the pixel data of a, Ls is read out, as shown in Fig. 6 (
An image as shown in A) is reproduced.

On the other hand, odd field lines L2 and L3.

The upper address of the read address of the memory circuit 7 during each sampling signal reproduction period of L4 is as shown in FIG. 5(A).
They are A2, A3, and Aa. This address A2, A
3. Since the pixel data of the 2nd, 3rd, and 4th lines L265, L266, and L267 from the top of the even field are written in Aa, the lines Lz and L3
, L4 reproduction images during each sampling signal reproduction period are shown in Figure 6 (
The result will be as shown in B). Therefore, the final reproduced image will be the same as that shown in FIG.

Also, when only the upper address of the write address is reproduced in an even field, it is 1 more than when reproducing an odd field.
The number of addresses may be reduced, and only the upper address of the read address may be reduced by 17 addresses. In the former case, see Figure 6 (A).

The same reproduced image as in (B) is obtained; in the latter case, the image shown in Fig. 3 (
The same reproduced images as in A) and (B) are obtained.

Also, 1st. Second. If the pixel data of the six lines L+ to Ls (1264 to L269) from the top of the third field are video signals of images showing diagonal lines as shown in FIGS. , if only the upper address of the write address is increased by one address when reproducing an even field than when reproducing an odd field, an image as shown in FIG. 8 (A>) is obtained when reproducing the second field, and During field playback, an image as shown in (8) in the same figure is obtained, so the playback image for one frame is the 9th
As shown in the figure, the jagged edges on the whiskers are less noticeable than in the conventional image shown in FIG. Hereinafter, the present invention will be described in more detail along with examples.

Example FIG. 10 shows a circuit diagram of an embodiment of the device of the present invention.

In the figure, the same components as in FIG. 1 are given the same reference numerals. First, to explain the operation during recording, a composite video signal (for example, a luminance signal) input to the input terminal 1 is supplied to the synchronization signal separation circuit 15 through the switch circuit 14 connected to the terminal R, where it is horizontally After the synchronization signal and vertical synchronization signal are separated, the horizontal synchronization signal is supplied to a phase locked loop (PL, L) 16 and a timing generator 17, respectively, and the vertical synchronization signal is supplied to the timing generator 17.P L L , 16 is phase-synchronized with the horizontal synchronizing signal, and generates and outputs a sampling pulse with a sampling frequency fS that is a natural number multiple of the horizontal scanning frequency fH and satisfies the following equation.

fS'=fL+fu (1)
(However, in formula (1), f is 0.5M HZ to 1MH
(fU is the upper limit frequency of the required frequency band of the reproduced luminance signal) This sampling pulse is supplied to the timing generator 17, while the switching circuit 1
The signal is supplied to the terminal 18a of the switch circuit 18, and the phase is inverted by the inverter 19 (with a 180° phase difference), and the signal is supplied to the terminal 18b of the switch circuit 18. The switch circuit 18 is generated by a recording/reproducing device 23, which will be described later.
A well-known head switching pulse, which is a symmetrical square wave with a two-field period, is branched and applied as a switching pulse from the output terminal 25, and is switched and connected for each field.

As a result, the switch circuit 18 has 18
Sampling pulses with a frequency of ts, whose phases are different by 0°, are selectively outputted to the terminal 2 of the switch circuit 20.
Supply to 0a. A DC voltage +Vc is applied to the terminal 20b of the switch circuit 20. On the other hand, during recording, the timing generator 17 generates pulses that have a first logical value in phase synchronization with the horizontal blanking period and vertical blanking period of the input composite video signal, and have a second logical value in other periods. is generated and outputted to the switch circuit 20 as a switching pulse. As a result, the switch circuit 20 selectively outputs the input DC voltage Vcc of the terminal 20b to the switch circuit 21 during both the horizontal and vertical blanking periods to keep it on, and on the other hand, except during the blanking periods. During the period (video period), the input sampling pulse of the terminal 20a is selectively output to the switch circuit 21.

As a result, the switch circuit 21 alternately turns on and off every half cycle of the sampling pulse during the video period of the input composite video signal, and applies the input composite video signal during the on period to the hold capacitor 22. . Therefore, from the hold capacitor 22, a sampled signal obtained by sampling the signal of the video period at the sampling frequency ts is taken out from the recording video signal input terminal of the recording/reproducing device 23 (the luminance signal recording system of the existing VTR). input terminal) 24. Furthermore, since the switch circuit 21 is continuously turned on during the blanking period, at least the synchronization signal of the input composite video signal is not sampled and the recording video signal input terminal 24
supplied to

Here, as is clear from equation (1) above, the sampling frequency fS is a frequency higher than the upper limit frequency fU of the required frequency band of the reproduced composite video signal by the frequency fL, but this frequency fL is higher than the upper limit frequency fU. Also low 0.5M) I
The frequency is about z~IMH2. Therefore, due to the above sampling, the aliasing frequency spectrum is mixed into the frequency range from the upper limit frequency "U" to the frequency fL, but O
There is no aliasing frequency spectrum in the frequency range up to ``h'', and the signal is transmitted as is without being interfered with by other signals. 5M Hz~
It is selected to be around IMHz.

The recording and reproducing device 23 comprises a recording means 4 and a reproducing means 5, and is an existing narrow band [VTR] with a horizontal resolution of, for example, about 240 lines, and the above-mentioned sampled signal is recorded on a magnetic tape via a well-known recording system. is recorded and then played back.

Next, the operation during playback will be explained. The reproduced sampled signal is taken out from the reproduced video signal output terminal 26 and supplied to the synchronizing signal separation circuit 15 through the switch circuit 14 which is switched and connected to the terminal P side, and on the other hand, is supplied to the memory device 27 through the AD converter 6. supplied to The horizontal synchronization signal in the reproduced sampling signal is generated by PLL16. They are respectively supplied to the timing generators 17, and generate sampling pulses having a frequency fS that is a natural number multiple of the horizontal scanning frequency f and satisfies the above equation (1) in the same manner as during recording. Further, the timing generator 17 to which both horizontal and vertical synchronization signals are supplied generates pulses of different logic values during the blanking period and the video period of the reproduced sampling signal. Furthermore, the timing generator 17 generates a pulse with a frequency twice the frequency rs and a pulse with a vertical scanning period, and applies them to the input terminals 28+ and 282 of the memory device 27 as a write/read control pulse and a load pulse, respectively. Output.

That is, the circuit section from the switch circuits 14 to 20 is as follows:
The first signal generating means 2 and the second signal generating means 11
This is a circuit that shares both.

Further, a part of the timing generator 17 and the memory device 27 constitute a memory circuit 7 and an addressing means 8.

The memory device 27 is composed of a random access memory (RAM) that constitutes the memory circuit 7 and an addressing means 8 such as an address counter. In the case of specifying an address such that the relationship between the field and the even field is one address less, a configuration as shown in FIG. 11 is used. In the figure, the same components as those in FIG. 10 are denoted by the same reference numerals, and the explanation thereof will be omitted. The pulse of frequency 2 fS that enters the terminal 281 is sent to the RAM 6 as a write/read control pulse R/W through the inverter 65.
6. Also, the address counter 67 is connected to the terminal 28.
A pulse from 2 is applied as a load pulse, and
A sampling pulse is applied as a clock pulse from the switch circuit 20 via a terminal 284. As a result, the address counter 67 generates, for example, a 16-bit address signal, and supplies the upper 8 bits of the address signal (upper address) to the adder 68 and the selector 69, while the lower 8 bits of the address signal (lower address) is supplied to the RAM 66. The upper address of the address signal changes corresponding to the line, and the lower address changes corresponding to the pixel position (number of samples) in one line.

The adder 68 is a circuit that adds a constant -1 to the upper address (that is, subtracts 1), and supplies the obtained upper address to the selector 69. The selector 69 is supplied with the head switching pulse taken out from the terminal 25 via the terminal 283, and the output signal of an AND circuit 70 which takes a logical product with the clock pulse from the terminal 284 is applied as a select signal. Only during reproduction, the output signal of the address counter 67 and the output signal of the adder 68 are switched and outputted alternately every period 1/(2fS), and during even field reproduction, only the output signal of the address counter 67 is output, and the output signal of the address counter 67 is outputted. is applied as the upper address. As a result, the upper address of RAM 66 is
When reproducing an odd field, writing is one address less than when reading, and when reproducing an even field, the address is written.

The same value is obtained when reading. That is, inverter 6
The write/read control pulses supplied from 5 to the RAM 66 are shown in FIG. 12(A) for both odd and even fields.
As shown by W/R in (B), it is a symmetrical square wave with a period of 1/(2fS), and a high level indicates a read period and a low level indicates a write period.
The least significant bit of the upper address output to M66 changes at a cycle of 1/fS as shown by the LSB in Figure 12 (A) when playing an odd field, and changes by the LSB as shown in Figure 12 (B) when playing an even field. As shown, it changes with a period of 2/fS.

On the other hand, the pixel data read from the RAM 66 is supplied to the latch 71, where it is latched at the rising edge of a latch pulse from the gate circuit 72, for example. The gate circuit 72 outputs a high level signal only when the clock pulse from the terminal 284 is low level and the pulse from the terminal 281 is high level. Therefore, the latch pulse is an odd number.

FIG. 12 (A) when playing any even field.

As shown by the latch ck in (B), the pulse train has a cycle of 1/fS and rises within the high level period of the write/read control pulse. Therefore, the pixel data read from the RAM 66 after being delayed by one field is latched by the latch 71 every cycle 1/s, and then applied to the terminal 29b of the switch circuit 29.

Returning to FIG. 10 again, the switch circuit 29 is applied with the sampling pulse of the sampling frequency fS taken out from the switch circuit 20 as a switching pulse, and is input to the terminal 29a every half period 1/(2fS). The incoming output signal of the AD converter 6 and the one-field delayed signal from the memory device 27 entering the terminal 29b are alternately selected and output.

As a result, the switch circuit 29 outputs data to each intermediate position of each pixel data (sample point) of the field currently being reproduced.
When each pixel data of one field before is inserted, that is, taking field correlation into consideration, a pixel data string with a sampling frequency of 2 1 s is substantially taken out, and the DA converter 30
supplied to A resampled signal, which is converted into an analog signal by the DA converter 30 and sampled at a sampling frequency of 2 fS, is taken out and supplied to a high-pass filter consisting of a capacitor 35 and a resistor 36, where The high-frequency components having a frequency of 11 or more are separated into P waves and then supplied to a mixing circuit 33 through a buffer amplifier 37 and a switch circuit 31.

On the other hand, the output pulse of the timing generator 17 is applied to the switch circuit 31, which is turned off during the blanking period.
While the video period is on, the voltage is applied to the switch circuit 40 through the inverter 32.

Further, the playback signal taken out from the playback video signal output terminal 26 of the recording/playback device 23 is transmitted to the terminal 4 of the switch circuit 40.
0a, and a low-pass filter consisting of a resistor 38 and a capacitor 39, where the frequency fL
Only the following low frequency components are separated into P waves and then supplied to the terminal 40b of the switch circuit 40. switch circuit 40
is switched and controlled by the output pulse of the inverter 32, and is switched and connected to the terminal 40b side during the video period, and to the terminal 40a side during the horizontal and vertical blanking periods. The output signal of the switch circuit 40 is supplied to the mixing circuit 33 through the delay circuit 34. As a result, from the mixing circuit 33 to the output terminal 41, during the video period, the resampled signal of the high frequency component with a frequency of 11 or more is mixed with the low frequency component where there is no aliased frequency spectrum due to sampling of a frequency of 11 or less. A signal is extracted, and during both the horizontal and direct blanking periods, a synchronization signal, etc., which has not been sampled or resampled, is extracted.

In this embodiment, only the high frequency components are resampled, so the number of bits of the AD converter 6 and the DA converter 30 is
It has been confirmed that 5 bits, which is approximately half the number of bits (8 bits) required for the AD converter 27 and DA converter 30, is sufficient when resampling is performed for the entire band. Further, the storage capacity of the RAM in the memory device 27 is only 5/8 of the storage capacity when resampling is performed for the entire band.

Incidentally, when an existing helical scanning type VTR is used as the recording/reproducing device 23, terminals are provided as shown in FIG. In the figure, the same components as those in FIG. 10 are denoted by the same reference numerals, and the explanation thereof will be omitted. Figure 13 shows an existing VTR with VT and R recording video signal input terminals 8.
Y/C separation circuit 4 from the composite color video signal inputted at 0
The luminance signal obtained by separation at step 2 enters input terminal 1. Also, the luminance signal input to the input terminal 24 is sent to the pre-emphasis and clip circuit 43 inside the VTR. Clamp circuit 44
．． FM modulator 45. The carrier color signals are supplied to an adder circuit 47 through high-pass filters 46, and separated by a Y/C separation circuit 42. The color signal recording process circuit 48 converts the carrier color signals into a signal form suitable for magnetic recording and reproduction. For example, it is frequency division multiplexed with a low-pass converted carrier color signal.

The multiplexed signal taken out from the adder circuit 47 is sent to the recording amplifier 4.
The signal is supplied to the recording head 50 via the magnetic tape 9 and recorded on the magnetic tape 51. During this recording, the recording head 50
A head switching pulse synchronized in phase with the rotation of the recording head 50 is outputted to the output terminal 25 from a drum motor control 53 that controls the rotation of a rotating drum to which a recording head 50 is attached.

The recorded edge multiplexed signal of the magnetic tape 51 is reproduced by a reproduction head 52 whose rotation is controlled based on the output signal of a drum motor control 53 and is supplied to a head switch 54 . As is well known, two reproducing heads 52 are provided, for example, on a rotating drum, facing each other at 180°, and the magnetic tape 51 is wound around the rotating drum over an angular range of just over 180° while running. The reproduction signals alternately taken out from the two reproduction heads 52 are cut into continuous signals by a head switching pulse from the drum motor control 53 that is supplied to the head switching device 54. The reproduced multiplexed signal taken out from the head switch 54 is sent to a preamplifier 55. The luminance signal is supplied to a high-pass filter 57 via an equalizer 56, where the frequency-modulated luminance signal is separated into P waves, and then supplied to an FM demodulator 58 to produce a reproduced luminance signal.

This reproduced luminance signal is outputted to the output terminal 26 via the de-emphasis circuit 59. On the other hand, the output reproduction multiplexed signal of the equalizer 56 is supplied to the color signal reproduction process circuit 60, where the low frequency conversion carrier color signal is separated into P waves and then subjected to known signal processing to restore the original phase in the original band. The signal is converted into a reproduced carrier color signal and further supplied to the Y/C mixer 61.

The Y/C mixer 61 mixes this reproduced carrier color signal with the reproduced luminance signal taken out from the output terminal 41 shown in FIG. Output to terminal 63.

Note that the present invention is not limited to the above embodiments; for example, rs may be an odd multiple of b+/2, sampling and resampling may be performed for the synchronization signal section, and Various modifications are possible, such as integrating the external circuit of the recording/reproducing device 23 into the VTR.

Effects of the Invention As described above, according to the present invention, a narrowband recording/reproducing device (
For example, horizontal resolution of about 240 lines) can be used to improve the horizontal resolution to about 300 lines or more, and in one of the odd and even fields, the upper bits of the write address and read address of the memory circuit are The relationships between the lines and lines are the same, and in the other field, one of the upper bits of the write address and read address is specified to be relatively different by one address than the other, so an image with no vertical correlation is created. It is possible to improve the jaggedness of the horizontal edges of the video signal (especially the luminance signal) to the extent that it is almost invisible, and for images with diagonal lines, the jaggedness of the stepped diagonal lines can be improved to the extent that it is almost invisible. It has the advantage that it can be improved to a certain degree.

[Brief explanation of drawings]

Figure 1 is a block system diagram showing the configuration of the device of the present invention;
5 and 7 are diagrams showing each pixel data of the write address or read address line of each embodiment of the device of the present invention for each field, and FIG. 3, FIG. 6, and FIG. Figure 2, respectively. Figures 5 and 7 show the pixel data of each line field by field when the pixel data is read out from the memory circuit; Figures 4 and 9 represent the pixels in Figures 3 and 8, respectively; 10 is a circuit system diagram showing an embodiment of the device of the present invention; FIG. 11 is a circuit system showing an embodiment of the memory device in the circuit system shown in FIG. 10. 12 is a signal waveform diagram for explaining the operation of the circuit system shown in FIG. 11, FIG. 13 is a block system diagram showing an example of a recording/reproducing device in the circuit system shown in FIG. 10, and FIGS.
The figure is a diagram showing the relationship between pixel data to be written and lines and a display image, FIG. 15(A). (B) and FIG. 17 are diagrams showing each pixel data read out from the memory circuit by the conventional device, and FIG. 15 (C) and FIG. 18 are diagrams each showing the main parts of the reproduced image by the conventional device. It is. DESCRIPTION OF SYMBOLS 1... Composite video signal input terminal, 2... First signal generation means, 3... Sampling means, 4... Recording means, 5.
... Reproduction means, 6. AD converter, 7. Memory circuit, 8. Addressing means, 9. Reproduction sampling signal generation means, 10. Re-sampling means, 11.・Second
12... Reproduction composite video signal output terminal, 15... Synchronization signal separation circuit, 16... Phase
Locked loop (PLL), 17... timing generator, 22... hold capacitor, 23...
・Recording/reproducing device, 27...Memory device, 30...
DA converter, 33... Mixing circuit, 41... Playback composite video signal output terminal, 66... Random access memory (RAM), 67... Address counter, 68...
...Adder, 69...Selector, 71...Latch. Patent applicant: Victor Japan Co., Ltd. -N-Bian -j -u'nee -J

Claims (1)

[Claims] In a video signal recording and reproducing device that records an input composite video signal such as a luminance signal on a recording medium and reproduces the same, a signal having a sampling frequency f_S related to the horizontal scanning frequency f_H of the input composite video signal, a first signal generating means for generating a signal whose phase differs by 180° for each field of the input composite video signal; and sampling the input composite video signal using the output signal of the first signal generating means. a recording means for recording a sampled signal extracted from the sampling means on a recording medium, a reproduction means for reproducing a previously recorded signal on the recording medium, and a reproduction signal extracted from the reproduction means. an AD converter that converts the A into pixel data;
A memory circuit that writes output pixel data of the D converter and reads it with a delay of one field is supplied with at least the playback signal, alternately generates a read address and a write address and supplies it to the memory circuit, and The relationship between the upper address of one of the read address and write address in the field and the line is compared with the relationship between the upper address of the read address and write address in the even field and the line, and the relative and a reproduction sampling signal for obtaining first and second reproduction sampling signals having a time difference of one field from each other from input pixel data and output pixel data of the memory circuit. a second signal generating means for generating a signal from the reproduced signal that is equal to the sampling frequency f_S and whose phase differs by 180° for each field of the reproduced signal; and the second signal. A reproduced composite video signal in which the output signal of the generating means is supplied as a switching signal, and the first and second reproduced sampled signals are alternately selected and output every half period of the switching signal, thereby being resampled at a frequency of substantially 2f_S. 1. A video signal recording and reproducing device comprising: resampling means for obtaining a video signal.