JPH06105288A - Time axis correcter for still video device - Google Patents

Abstract

PURPOSE:To attain the jitter correction of a picture signal with high accuracy. CONSTITUTION:A color difference signal FM-modulated by an M modulating circuit 32a, luminance signal FM-modulated by an FM modulating circuit 32b, and DPSK modulated signal (pilot signal) outputted from a DPSK modulating circuit 42 are frequency-multiplexed by a synthesizing circuit 44, and recorded in a magnetic disk 54. At the time of reproduction of this signal, the color difference signal and the luminance signal are FM-demodulated by FM demodulating circuits 84a and 84b, ID information is DPSK-demodulated by a DPSK demodulating circuit 64, and the pilot signal is reproduced by a carrier reproducing circuit 62. The pilot signal is multiplied by a PLL circuit 70, a pulse signal is obtained, and a clock signal is prepared by a writing clock generating circuit 80 based on the pulse signal. The luminance signal and the color difference signal are A/D converted by the clock signal, and written in memories 93a and 93b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still video device for correcting a time axis of an image signal by using a pilot signal.

[0002]

2. Description of the Related Art Conventionally, there is a still video camera as a still image signal recording / reproducing apparatus for recording a still image signal read from an image pickup device such as a CCD on a magnetic disk.
Still image signals (video signals) recorded in such a still video camera are luminance signals and color difference signals (RY, B).
-Y) and FM with carrier waves having different center frequencies
It is modulated and multiplexed. This FM-modulated signal is further frequency-multiplexed with ID information such as the shooting date and recorded on the track of the magnetic disk.

The signal reproduced from the magnetic disk is obtained by extracting the amplitude signal of each pixel using a sampling pulse generated based on the horizontal synchronizing signal and the vertical synchronizing signal recorded at the time of recording on the disk, and then temporarily storing it in a memory or the like. Stored as digital data in. The data stored in this memory is read out according to a predetermined reference clock, converted into an analog signal again, and output to a display device or the like.

[0004]

A magnetic disk of a still video camera is rotationally driven by a spindle motor, and its rotation has some rotational irregularity. Further, the rotation center axis of the spindle motor and the rotation center axis of the magnetic disk do not always match. Due to the uneven rotation and the deviation of the rotation axis, the signal read from the magnetic disk contains a considerable amount of jitter on the time axis. Moreover, this jitter is not always constant in one track and changes over time, so that the amplitude signal of each pixel is not accurately sampled, and the entire playback screen is visually distorted left and right.

An object of the present invention is to provide a time base correction device for a still video device which can perform jitter correction with high accuracy.

[0006]

According to a first aspect of the present invention, there is provided a time base correction apparatus for a still video apparatus, wherein the time axis correction apparatus frequency-modulates a frequency-modulated video signal and a frequency domain of the frequency-modulated video signal. Means for DPSK-modulating a low-frequency pilot signal, means for synthesizing a frequency-modulated video signal and a DPSK-modulated pilot signal, means for recording an output signal from the synthesizing means on a recording medium, and a recording medium A means for extracting a pilot signal from the signal read from the device, means for generating a clock signal from the pilot signal, and means for performing time axis correction of the frequency demodulated video signal based on the clock signal. It is characterized by that.

A time base correction apparatus for a second still video apparatus according to the present invention comprises means for frequency-modulating a video signal,
Means for DPSK modulating a pilot signal having a frequency lower than the frequency domain of the frequency-modulated video signal, means for synthesizing the frequency-modulated video signal and the DPSK-modulated pilot signal, and an output signal from this synthesizing means Is recorded on a recording medium.

The time base correction apparatus of the third still video apparatus according to the present invention records a frequency-modulated video signal by DPSK-modulating a pilot signal having a frequency lower than the frequency domain of the video signal and combining the pilot signal with the pilot signal. A means for extracting a pilot signal from the recorded recording medium, a means for generating a clock signal from the pilot signal, and a means for correcting the time axis of the frequency-demodulated video signal based on the clock signal. Is characterized by.

[0009]

The present invention will be described below with reference to illustrated embodiments. FIG. 1 is a block diagram of a still video camera according to an embodiment of the present invention. In this figure, a color difference signal (RY, BY) and a luminance signal (Y + S) are input from an image sensor (not shown). The color difference signal is sent to the FM via the line sequentializing circuit 31.
The modulation signal is FM-modulated by the modulation circuit 32a, and the luminance signal is FM-modulated by the FM modulation circuit 32b.
4 is input. The DPSK modulation signal having a predetermined frequency used as a pilot signal is input to the synthesis circuit 44 from the DPSK modulation circuit 42. To the DPSK modulation circuit 42, a carrier generator 43 that generates a carrier wave used for DPSK modulation and an encoder 40 that encodes ID information are connected. The system controller 24 is connected to the encoder 40, and the display 25, the operation switch 22 and the decoder 66 are connected to the system controller 24.

The system controller 24 is composed of a microcomputer and the like, and performs system control of the entire electronic still camera. For example, magnetic disk 5
The system controller 24 controls the connection switching of the video switch 48 when recording the video signal to the recording medium 4 or reading the video signal from the magnetic disk 54.

In the synthesizing circuit 44, the color difference signal FM-modulated by the FM modulating circuit 32a and the FM signal by the FM modulating circuit 32b are used.
The modulated luminance signal and the pilot signal output from the DPSK modulation circuit 42, that is, the DPSK modulation signal are frequency-multiplexed. These signals are amplified to a predetermined level by the recording amplifier 46, and then output to the recording / reproducing head 50 via the REC terminal of the video switch 48 and recorded on each track of the magnetic disk 54. The magnetic disk 54 is rotationally driven by a spindle motor 58 at a predetermined rotational speed during recording and reproduction.

The PB terminal of the video switch 48 is connected to the reproducing amplifier 56, and the signal read from the magnetic disk 54 during reproduction is amplified by the reproducing amplifier 56. The signals output from the reproduction amplifier 56 are input to the FM demodulation circuits 84a and 84b, the DPSK demodulation circuit 64, and the carrier reproduction circuit 62, respectively.

The carrier reproducing circuit 62 reproduces the carrier wave of the DPSK modulated signal and outputs it to the DPSK demodulating circuit 64. The DPSK demodulation circuit 64 demodulates the DPSK signal, and the demodulated signal, that is, the ID information is decoded and decoded by the decoder 66. This ID information is displayed on the display 25 under the control of the system controller 24.

The output signal of the carrier reproducing circuit 62 is PL
It is input to the L circuit 70. The PLL circuit 70 includes a phase comparator 72, a low pass filter (hereinafter referred to as LPF) 74,
It is composed of a voltage controlled oscillator (hereinafter referred to as VCO) 76 and a frequency dividing circuit 78, and has a well-known configuration. This PLL
By inputting the pilot signal output from the carrier reproduction circuit 62 to the circuit 70, the PLL circuit 70 outputs a pulse signal of a predetermined frequency that is synchronized with the phase of the reproduced pilot signal.

In the write clock generation circuit 80, the PLL
The clock signal S1 and the clock signal S2 are generated based on the pulse signal input from the circuit 70, and output to the A / D converters 92a and 92b and the write address counter 82. That is, the A / D converters 92a and 92b operate by the clock signal S1, and the write address counter 82 operates by the clock signal S2. The A / D converter 92a receives the luminance signal (Y + S) demodulated by the FM demodulation circuit 84a, and the A / D converter 92b receives the color difference signals (RY, BY) demodulated by the FM demodulation circuit 84b. ) Is input, and these signals are sampled by the clock signal S1 and converted into digital signals.
The digitized luminance signal and color difference signal are input to the memories 93a and 93b, and the write address counter 8
According to the memory address value input from 6, the data is sequentially written in the memory address.

The memory 93a includes a read address counter 86 and a D / A converter 88a, and the memory 93b.
Read address counter 86 and D / A converter 8
8b is connected. Read address counter 86
And the D / A converters 88a and 88b are operated by the clock signals S3 and S4 input from the read clock generator 94, and these clock signals S3 and S4 are read by the reference clock generator 90 in the read clock generator 94.
It is generated based on the clock signal output from. The clock signal output from the reference clock generator 90 has almost the same period as the pulse signal output from the PLL circuit 70.

In the memory 93a, the luminance signal is sequentially read from the address specified by the memory address value input from the read counter 86, and the D / A converter 88a is read.
Is output to. The luminance signal (Y + S) converted into the analog signal by the D / A converter 88a has its high frequency component removed by the LPF 96a, and is input to the encoder 100. Similarly, in the memory 93b, the color difference signals are sequentially read from the address designated by the memory address value input from the read counter 86 and output to the D / A converter 88b. The color difference signals (RY, BY) converted into analog signals by the D / A converter 88b have high frequency components removed by the LPF 96b, and are input to the encoder 100 via the synchronization circuit 98.

In the encoder 100, the luminance signal (Y +
S) and the color difference signals (RY, BY) are combined to form a composite video signal, which is output to a video output terminal or the like (not shown).

Next, the operation of the apparatus of this embodiment will be described. The signal reproduced from the magnetic disk 54 includes the magnetic disk 5
Due to the influence of the rotation unevenness of 4, the signal includes jitter that is slightly deviated in the time axis direction. Therefore, the FM demodulated composite video signal also contains jitter. Therefore, if the clock signal S1 is generated from the pilot signal multiplexed and recorded in the reproduced signal having the jitter, each pixel signal can be accurately sampled without being affected by the jitter.

The PLL circuit 70 generates a clock signal which is phase-synchronized with the pilot signal and has a highly accurate frequency. More specifically, the pilot signal input to the phase comparator 72 is phase-compared with the output signal of the VCO 76 that has been frequency-divided by the frequency dividing circuit 78 to 1 / N. A control voltage signal corresponding to the phase difference is generated by the phase comparator 72 and further input to the VCO 76 through the LPF 74. The VCO 76 generates an oscillation signal according to the control voltage signal, outputs the oscillation signal to the frequency dividing circuit 78, and feeds it back to the phase comparator 72.

The oscillation signal output from the VCO 76 is input to the write clock generation circuit 80, and the magnetic disk 5
A clock signal S1 synchronized with the luminance signal and the color difference signal read out from No. 4 is generated. This signal S1 is input to the A / D converters 92a and 92b. Further, the clock signal S2 delayed by a predetermined phase from the clock signal S1 is
It is generated by the write clock generation circuit 80 and output to the write address counter 82. This clock signal S1,
The phase difference of S2 takes into consideration the analog / digital conversion delay of the A / D converters 92a and 92b.
The clock signal S2 is used to sequentially increment the memory address value output to the memories 93a and 93b in the write address counter 82.

In the A / D converters 92a and 92b, the data for each pixel of the demodulated luminance signal and the color difference signal input from the FM demodulation circuits 84a and 84b are accurately sampled by the clock signal S1 and converted into digital signals. It The digitized luminance signal and chrominance signal are sequentially written in the addresses of the memories 93a and 93b designated by the memory address value input from the write address counter 86. As described above, the luminance signal and the color difference signal are A / D converted by the clock signal S1 and the clock signal S2 generated based on the pilot signal and stored in the memories 93a and 93b.
The influence of the jitter is suppressed on the luminance signal and the color difference signal on 3b.

FIG. 2 shows a magnetic disk 54 according to this embodiment.
2 shows an example of frequency allocation of a signal multiplexed and recorded on a disc. As shown in this figure, in this embodiment, the pilot signal is the DPSK modulated signal itself used for recording ID information such as the shooting date. The DPSK modulation signal is a frequency signal of 13 × fH (204.5 kHz). Here, fH is the frequency of the horizontal synchronizing signal of 15.73 kHz. The luminance signal (Y-FM) and the color difference signal (C-FM) are recorded in the same frequency range as the conventional device.

As described above, the pilot signal is originally
DP used for recording ID information such as shooting date
The SK signal is used. Therefore, the pilot signal is
It is reliably taken out by a low-pass filter provided in a conventional still video camera, which allows the jitter correction of the image signal to be performed with sufficient accuracy.

In each of the above-mentioned embodiments, the video signal has NT.
Although the SC system is used, the present invention is also applicable to recording a video signal of the PAL system or the like on the magnetic disk 54.

The DPSK signal may serve as a mere pilot signal without being modulated with the ID information (that is, in the unmodulated state).

[0027]

As described above, according to the present invention, the same jitter as that of the read signal, which is generated when the signal recorded on the recording medium such as the magnetic disk is read, is generated in the pilot signal. From which a sampling signal is generated. Therefore, even if each pixel signal shifts in the time axis direction, the pixel signal can be sampled more accurately, and distortion in the horizontal direction of the screen can be prevented. In addition, this pilot signal is
Since the DPSK signal used for recording information is used, it is not necessary to newly install a signal generator for time base correction, and since a relatively large DPSK signal is used, the pilot signal Is less affected by noise, and an image with a predetermined accuracy can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing frequency allocation of signals multiplexed and recorded on a magnetic disk.

[Explanation of symbols]

 44 Compositing Circuit 54 Magnetic Disk 58 Spindle Motor 70 PLL Circuit

Claims (3)

[Claims] 1. A means for frequency modulating a video signal, a means for DPSK modulating a pilot signal having a frequency lower than the frequency domain of the frequency modulated video signal, a frequency modulated video signal and a DPSK modulated pilot signal. And a means for recording the output signal from the combining means on a recording medium, a means for extracting a pilot signal from the signal read from the recording medium, and a means for generating a clock signal from the pilot signal. And a means for correcting the time axis of the frequency-demodulated video signal based on the clock signal, and a time axis correction device for a still video device. 2. Means for frequency modulating a video signal, means for DPSK modulating a pilot signal having a frequency lower than the frequency domain of the frequency modulated video signal, frequency modulated video signal and DPSK modulated pilot signal And a means for recording an output signal from the combining means on a recording medium, and a time axis correction apparatus for a still video device. 3. A means for extracting a pilot signal from a recording medium recorded by DPSK-modulating a frequency-modulated video signal with a pilot signal having a frequency lower than the frequency range of the video signal and combining the pilot signal, and the pilot. A time axis correction device for a still video device, comprising: a means for generating a clock signal from a signal; and a means for correcting the time axis of a frequency-demodulated video signal based on the clock signal.