JPH0686229A - Time base corrector for still video camera - Google Patents

Abstract

PURPOSE:To perform jitter correction on an image signal with high accuracy. CONSTITUTION:The frequency division multiplex of a black-and-white video signal frequency-modulated by a frequency modulation circuit 45, ID information DPSK-modulated by a DPSK modulation circuit 42, and a pilot signal outputted, from a pilot signal generation circuit 47 is performed at a synthesis circuit 44, and a synthesized signal is multiplex-recorded on a magnetic disk 54. When the signal is reproduced, the black-and-white video signal is frequency- demodulated at a frequency demodulation circuit 84, and the ID information is DPSK-demodulated at a DPSK demodulation circuit 64, and the pilot signal is reproduced through a pilot signal reproduction circuit 68. A pulse signal can be obtained by multiplying the pilot signal at a PLL circuit 70, and a clock signal can be generated at a write clock generation circuit 80 based on the pulse signal. The black-and-white video signal is A/D-converted by the clock signal, and it is written on memory 93. Therefore, it is possible to accurately sample a picture element signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a still video camera for correcting a time axis of an image signal by using a pilot signal.

[0002]

2. Description of the Related Art Conventionally, there is a still video camera as a still image signal recording / reproducing apparatus for recording a still image signal read from an image pickup device such as a CCD on a magnetic disk.
Still image signals (video signals) recorded in such a still video camera are luminance signals and color difference signals (RY, B).
-Y) and FM with carrier waves having different center frequencies
It is modulated and multiplexed. This FM-modulated signal is further frequency-multiplexed with ID information such as the shooting date and recorded on the track of the magnetic disk.

The signal reproduced from the magnetic disk is obtained by extracting the amplitude signal of each pixel using a sampling pulse generated based on the horizontal synchronizing signal and the vertical synchronizing signal recorded at the time of recording on the disk, and then temporarily storing it in a memory or the like. Stored as digital data in. The data stored in this memory is read out according to a predetermined reference clock, converted into an analog signal again, and output to a display device or the like.

[0004]

A magnetic disk of a still video camera is rotationally driven by a spindle motor, and its rotation has some rotational irregularity. Further, the rotation center axis of the spindle motor and the rotation center axis of the floppy disk do not always match. Due to the uneven rotation and the deviation of the rotation axis, the signal read from the magnetic disk contains a considerable amount of jitter on the time axis. Moreover, this jitter is not always constant in one track and changes over time, so that the amplitude signal of each pixel is not accurately sampled, and the entire playback screen is visually distorted left and right.

In particular, in a monochrome video camera in a black-and-white mode in which a wide band luminance signal can be recorded on a magnetic disk so that a high quality image can be obtained, the reproduced image is deteriorated unless the jitter correction is performed with high accuracy. Therefore, it is not possible to fully exert the function of widening the band.

An object of the present invention is to provide a time base correction apparatus for a still video camera which can perform jitter correction with high accuracy.

[0007]

SUMMARY OF THE INVENTION A time base correction apparatus for a still video camera according to the present invention includes means for frequency-modulating only a frequency-modulated black-and-white video signal and a frequency domain for the frequency-modulated black-and-white video signal. Means for generating a pilot signal having a low frequency, means for synthesizing a black-and-white video signal and a pilot signal, means for recording an output signal from the synthesizing means on a recording medium, and a signal read from the recording medium It is characterized in that it is provided with means for taking out a pilot signal, means for generating a clock signal from this pilot signal, and means for performing time axis correction of the frequency-demodulated black-and-white video signal based on this clock signal.

[0008]

The present invention will be described below with reference to illustrated embodiments. 1 is a block diagram of a still video camera according to a first embodiment of the present invention. In this figure, a monochrome video signal input from an image pickup device (not shown) is FM-modulated in the FM modulation circuit 45 and input to the synthesis circuit 44. The DPSK modulation signal is input from the DPSK modulation circuit 42 and the pilot signal of a predetermined frequency is input from the pilot signal generation circuit 47 to the combining circuit 44. DP
To the SK modulation circuit 42, a carrier generator 43 that generates a carrier wave used for DPSK modulation and an encoder 40 that encodes ID information are connected. The system controller 24 is connected to the encoder 40, and the display 25, the operation switch 22 and the decoder 66 are connected to the system controller 24.

The system controller 24 is composed of a microcomputer or the like, and controls the system of the entire electronic still camera. For example, magnetic disk 5
The system controller 24 controls the connection switching of the video switch 48 when recording the video signal to the recording medium 4 or reading the video signal from the magnetic disk 54.

In the synthesizing circuit 44, F in the FM modulating circuit 45.
M-modulated video signal and pilot signal generation circuit 4
The pilot signal input from 7 and the DPSK modulation signal input from the DPSK modulation circuit 42 are frequency-multiplexed. These signals are amplified to a predetermined level by the recording amplifier 46, and then output to the recording / reproducing head 50 via the REC terminal of the video switch 48 and recorded on each track of the magnetic disk 54. The magnetic disk 54
Is rotated by a spindle motor 58 at a predetermined rotation speed during recording and reproduction.

The PB terminal of the video switch 48 is connected to the reproducing amplifier 56, and the signal read from the magnetic disk 54 during reproduction is amplified by the reproducing amplifier 56. The signal output from the reproduction amplifier 56 is input to the FM demodulation circuit 84, the DPSK demodulation circuit 64, the carrier reproduction circuit 62, and the pilot signal reproduction circuit 68, respectively.

The carrier reproducing circuit 62 reproduces the carrier wave of the DPSK modulated signal and outputs it to the DPSK demodulating circuit 64. The DPSK demodulation circuit 64 demodulates the DPSK signal, and the demodulated signal, that is, the ID information is decoded and decoded by the decoder 66. This ID information is displayed on the display 25 under the control of the system controller 24.

The pilot signal reproduction circuit 68 extracts a pilot signal from the signal input from the reproduction amplifier 56 and outputs it to the PLL circuit 70. PLL circuit 70
Is a phase comparator 72, a low pass filter (hereinafter referred to as LPF) 74, a voltage controlled oscillator (hereinafter referred to as VCO) 76.
And a frequency dividing circuit 78, and has a well-known configuration. The PLL circuit 70 is connected to the pilot signal reproducing circuit 6
By inputting the pilot signal output from the PLL circuit 8, the PLL circuit 70 outputs a pulse signal having a predetermined frequency synchronized with the phase of the reproduced pilot signal.

In the write clock generation circuit 80, the PLL
The clock signal S1 and the clock signal S2 are generated based on the pulse signal input from the circuit 70 and output to the A / D converter 92 and the write address counter 82.
That is, the A / D converter 92 operates by the clock signal S1, and the write address counter 82 operates by the clock signal S1.
It works by 2. A monochrome video signal demodulated by the FM demodulation circuit 84 is input to the A / D converter 92, and the monochrome video signal is sampled by the clock signal S1 and converted into a digital signal. The digitized black-and-white video signal is input to the memory 93 and sequentially written in the memory address according to the memory address value input from the write address counter 86.

A read address counter 86 and a D / A converter 88 are connected to the memory 93. The read address counter 86 and the D / A converter 88 include a clock signal S3 input from the read clock generator 94.
Operated by S4, these clock signals S3, S4
Is generated in the read clock generator 94 based on the clock signal output from the reference clock generator 90. The clock signal output from the reference clock generator 90 has almost the same period as the pulse signal output from the PLL circuit 70.

In the memory 93, the black and white video signal is sequentially read from the address designated by the memory address value input from the read counter 86, and the D / A converter 8 is used.
8 is output. The black-and-white video signal converted into an analog signal by the D / A converter 88 has a high-frequency component removed by the LPF 96 and is output to a video output terminal or the like not shown.

Next, the operation of the apparatus of this embodiment will be described. The signal reproduced from the magnetic disk 54 includes the magnetic disk 5
Due to the influence of the rotation unevenness of 4, the signal includes jitter that is slightly deviated in the time axis direction. Therefore, the FM demodulated video signal also contains jitter. Therefore, if the clock signal S1 is generated from the pilot signal multiplexed and recorded in the reproduced signal having the jitter, each pixel signal can be accurately sampled without being affected by the jitter.

In the pilot signal reproducing circuit 68, a pilot signal is extracted from the reproduced signal of the magnetic disk 54 by a bandpass filter or the like and output to the phase comparator 72 of the PLL circuit 70. The PLL circuit 70 generates a clock signal which is phase-synchronized with the pilot signal and has a highly accurate frequency. More specifically, the phase comparator 7
The frequency of the pilot signal input to 2 is 1 /
The phase is compared with the output signal of the VCO 76 divided by N. A control voltage signal corresponding to the phase difference is generated by the phase comparator 72, and is further passed through the LPF 74 to the VCO.
It is input to 76. The VCO 76 generates an oscillation signal according to the control voltage signal, outputs the oscillation signal to the frequency dividing circuit 78, and feeds it back to the phase comparator 72.

The oscillation signal output from the VCO 76 is input to the write clock generation circuit 80, and the magnetic disk 5
A clock signal S1 synchronized with the black and white video signal read out from 4 is generated. This signal S1 is input to the A / D converter 92. Further, a clock signal S2 delayed by a predetermined phase from the clock signal S1 is generated by the write clock generation circuit 80 to generate a write address counter 82.
Is output to. The phase difference between the clock signals S1 and S2 takes into consideration the analog / digital conversion delay of the A / D converter 92 and the like. The clock signal S2 is used by the write address counter 82 to sequentially increment the memory address value output to the memory 93.

In the A / D converter 92, the FM demodulation circuit 84
The data for each pixel of the demodulated black-and-white video signal input from is accurately sampled by the clock signal S1 and converted into a digital signal. The digitized black-and-white video signal is sequentially written in the address of the memory 93 designated by the memory address value input from the write address counter 86. In this way, the monochrome video signal is A / D converted by the clock signal S1 and the clock signal S2 generated based on the pilot signal, and the memory 9
Since it is stored in memory 3, the black and white video signal on the memory 93 is not affected by the jitter at all.

FIG. 2 shows the magnetic disk 5 in the first embodiment.
4 shows an example of frequency allocation of signals multiplexedly recorded in No. 4 of FIG. As shown in this figure, the pilot signal is a frequency signal of f _SC × 4 ÷ 16≈895 kHz, and the DPSK modulated signal is 13 × f _H (204.5 kHz).
z) frequency signal. Here, f _SC is the frequency of the subcarrier of the image signal, 3.58 MHz, and f _H is the frequency of the horizontal synchronizing signal, 15.73 kHz. On the other hand, the luminance signal is 7.7 MHz at the sync tip and 9.7 M at the white peak.
It is a signal of Hz, and it is lower than the conventional range (1.0M
Hz) and the bandwidth is 8 MHz.
Further, in the case of this embodiment, if the frequency division ratio of the frequency divider circuit 78 in FIG. 1 is set to 1/16, the frequency of the clock signal output from the VCO 76 becomes 4f _SC , which is a commonly used sampling frequency. .

That is, the pilot signal is formed in the frequency domain which is conventionally used for recording the color signal. Further, since the frequency region of the pilot signal is extremely narrow, the luminance signal is used up to a frequency region lower than the conventional one, and the bandwidth is wide as described above. Therefore, according to the present embodiment, the jitter correction can be performed with sufficient accuracy as described above, and the resolution of the luminance signal can be improved.

FIG. 3 shows a second embodiment. The second embodiment is different from the first embodiment shown in FIG.
A still camera that does not record information (DPSK signal) on the magnetic disk 54 is shown. That is, this configuration is shown in FIG.
Encoder 40, DPSK modulation circuit 42, carrier generator 43, decoder 66, DPSK demodulation circuit 64
The carrier reproducing circuit 62 is not provided. The functional operations of the other circuits are all the same except that the frequency of the pilot signal is different.

FIG. 4 shows an example of frequency allocation of signals multiplexed and recorded on the magnetic disk 54 in the second embodiment. As shown in this figure, the pilot signal is a frequency signal of f _SC × 4 ÷ 64≈224 kHz, and the luminance signal is a signal of 7.7 MHz at the synchronization tip and 9.7 MHz at the white peak, and the low frequency region is 0.5KH
z is used up to a bandwidth of 8.5 [MHz]. In the case of this embodiment, if the frequency dividing ratio of the frequency dividing circuit 78 in FIG. 1 is set to 1/64, the frequency of the VOC output signal becomes 4f _SC .

As described above, the second embodiment lowers the frequency of the pilot signal as compared with the first embodiment, and
The frequency range of the luminance signal is further expanded. From the viewpoint of jitter correction, it is preferable that the frequency of the pilot signal is high in order to improve the accuracy of the clock signals S1 and S2. Therefore, the accuracy of jitter correction is better in the first embodiment, but in the resolution of the luminance signal, the second embodiment is better.

In each of the above embodiments, the video signal is NT
Although the SC system is used, the present invention is also applicable to recording a video signal of the PAL system or the like on the magnetic disk 54.

[0027]

As described above, according to the present invention, the same jitter as that of the read signal, which is generated when the signal recorded on the recording medium such as the magnetic disk is read, is generated in the pilot signal. Since the sampling signal is generated from the pixel signal, the pixel signal can be more accurately sampled even if each pixel signal is deviated in the time axis direction, and distortion in the horizontal direction of the screen can be prevented. Further, since the color difference signal is not recorded in the video signal in a multiplex manner, the band of the luminance signal can be widened and a more precise image can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing frequency allocation of signals multiplexed and recorded on a magnetic disk in the first embodiment.

FIG. 3 is a block diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 4 is a diagram showing frequency allocation of signals multiplexed and recorded on a magnetic disk in a second embodiment.

[Explanation of symbols]

 44 Compositing Circuit 47 Pilot Signal Generating Circuit 54 Magnetic Disk 58 Spindle Motor 68 Pilot Signal Reproducing Circuit 70 PLL Circuit

Claims (1)

[Claims] 1. A means for frequency-modulating only a monochrome video signal, a means for generating a pilot signal having a frequency lower than the frequency range of the frequency-modulated monochrome video signal, a frequency-modulated monochrome video signal and a pilot signal. And a means for recording the output signal from the combining means on a recording medium, a means for extracting a pilot signal from the signal read from the recording medium, and a means for generating a clock signal from the pilot signal. And a time axis correction device for a still video camera, comprising means for correcting the time axis of the frequency-demodulated monochrome video signal based on the clock signal.