JPS61121490A - Electronic component mounting apparatus - Google Patents

Electronic component mounting apparatus

Info

Publication number
JPS61121490A
JPS61121490A JP24363784A JP24363784A JPS61121490A JP S61121490 A JPS61121490 A JP S61121490A JP 24363784 A JP24363784 A JP 24363784A JP 24363784 A JP24363784 A JP 24363784A JP S61121490 A JPS61121490 A JP S61121490A
Authority
JP
Japan
Prior art keywords
soldering
solder
chip
circuit board
chip component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24363784A
Other languages
Japanese (ja)
Inventor
菅沢 和彦
田村 好史
河本 登
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP24363784A priority Critical patent/JPS61121490A/en
Publication of JPS61121490A publication Critical patent/JPS61121490A/en
Pending legal-status Critical Current

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は電子部品が配線取付けされる配線回路基板の取
付装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a mounting device for a printed circuit board on which electronic components are wired.

従来例の構成とその問題点 配線回路基板を用いて、配線回路部の半田付ランドに電
子部品、特にチップ部品を装着取付して半田接続を行な
う方法は大きく2通りの方式が用いられる。1つは半田
付ランド間の基板面上にチップ部品の非半田付部を使っ
て接着剤により、配線回路基板に固定した後、半田噴流
槽を用いて、チップ部品の電極と配線回路基板の半田付
ランドと半田付するフローソルダーリング方式で、他の
1つは、配線回路基板の半田付ランド部にクリーム半田
を印刷、またはデイスペンサーにより、塗布した後、チ
ップ部品を装着して、クリーム半田の粘着性を利用して
、仮保持された状態で、半田が溶融する温度以上に設定
されたりフロ一槽を用いて半田付するリフローンルダリ
ング方式が用いられる。
Conventional Structures and Problems There are broadly two methods for attaching electronic components, particularly chip components, to soldering lands of a wired circuit section and making solder connections using a wired circuit board. One is to use the non-soldered parts of the chip components on the board surface between the soldering lands to be fixed to the printed circuit board using adhesive, and then use a solder jet bath to connect the electrodes of the chip components to the printed circuit board. The other method is the flow soldering method, in which soldering is performed on the soldering land of the printed circuit board.The other method is to print or apply cream solder to the soldering land of the wiring circuit board, then apply it with a dispenser, attach the chip parts, and then apply the cream solder to the soldering land of the circuit board. A reflow soldering method is used in which the adhesiveness of the solder is used to temporarily hold the solder at a temperature higher than that at which the solder melts, or to solder using a flow bath.

本発明は後者の方法に関するもので、従来例を第1図〜
第4図に示す。
The present invention relates to the latter method, and the conventional example is shown in FIGS.
It is shown in Figure 4.

第1図は、配線回路基板1に形成された配線回路部2と
半田付ランド3の1例を示す図で、斜線部4は配線回路
上にオーバーコートされた半田レジストを示す。第2図
は半田付ランドにクリーム半田5が塗布された状態の図
、第3図はチップ部品らが装着された図を示す。
FIG. 1 is a diagram showing an example of a wired circuit portion 2 and a soldering land 3 formed on a wired circuit board 1, and a hatched portion 4 indicates a solder resist overcoated on the wired circuit. FIG. 2 shows a state in which cream solder 5 is applied to the soldering land, and FIG. 3 shows a state in which chip components are attached.

第3図において、半田付ランド3に塗布されたクリーム
半田5は、チップ部品6を装着することにより、チップ
部品6の電極の厚み人、半田付ランド3の厚み已により
発生するチップ下面と、配線回路基板1上面の空間Cに
押し流された状態となる。
In FIG. 3, the cream solder 5 applied to the soldering land 3 is formed by attaching the chip component 6 to the bottom surface of the chip, which is generated due to the thickness of the electrode of the chip component 6 and the thickness of the soldering land 3. It is in a state where it is swept away into the space C on the upper surface of the printed circuit board 1.

以上の状態でリフロ一槽により、半田付された時、第4
図て示すように溶融した半田が、半田付ラッド3へ充分
戻りきらずにチップ部品6の下面部にボール状の半田子
が残ることによってチップ部品6の電極間が半田ボール
7により、短絡することがあった。
When soldered in one reflow tank under the above conditions, the fourth
As shown in the figure, the molten solder does not fully return to the soldering rad 3 and a ball-shaped solder remains on the bottom surface of the chip component 6, causing a short circuit between the electrodes of the chip component 6 due to the solder ball 7. was there.

発明の目的 本発明の目的は前記従来の問題点に鑑み、リフロ一方式
に基づいて、配線回路基板へのチップ部品の半田付にお
ける半田付品質の改善を図ることにある。
OBJECTS OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to improve the soldering quality in soldering chip components to printed circuit boards based on the reflow one-way method.

発明の構成 この目的全達成するために本発明は、チップ部品の電極
部が半田接続される半田付ランド間の基板面上にこの基
板上に配置されたチップ部品の下面までの高さより高い
寸法の絶縁層を形成したもので、この構成により、チッ
プ電極間の半田ボールの発生′f!:なくしたものであ
る。
Structure of the Invention In order to achieve all of these objects, the present invention provides a dimension that is higher than the height to the bottom surface of the chip component placed on the substrate surface between the soldering lands to which the electrode portion of the chip component is soldered. This structure prevents the formation of solder balls between the chip electrodes. :It's something I lost.

実施例の説明 以下本発明の一実施例について図面を参照しながら説明
する。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

第5図は従来例の第2図に対応した本発明の一実施例に
基づく断面図、第6図は第5図において、チップ部品全
装着した状態の断面図を示す。
FIG. 5 is a sectional view based on an embodiment of the present invention corresponding to FIG. 2 of the conventional example, and FIG. 6 is a sectional view of FIG. 5 with all chip components attached.

第5図において、斜線部は同じく半田付ランド間に印刷
塗布してオーバーコートされた半田レジスト8を示し、
装着されたチップ部品6の下面と配線回路基板1の上面
間に空間が発生しない厚み、すなわち第3図に示すC寸
法より大きい厚みで形成されている。
In FIG. 5, the shaded area shows the solder resist 8 which is also overcoated by printing between the soldering lands.
The thickness is such that no space is created between the lower surface of the mounted chip component 6 and the upper surface of the printed circuit board 1, that is, the thickness is larger than the dimension C shown in FIG.

第6図の配線回路基板1上にチップ部品6金装着した時
、第6図に示すように塗布されているクリーム半田5は
、チップ部品6を装着することにより、チップ部品6の
下部に押し流されるが、半田レジスト8の上面がテップ
部品6の下面と当接することによって、半田レジスト8
の端面9でクリーム半田6の流れは止まる。
When the chip component 6 gold is mounted on the printed circuit board 1 shown in FIG. 6, the cream solder 5 applied as shown in FIG. However, since the upper surface of the solder resist 8 comes into contact with the lower surface of the tip component 6, the solder resist 8
The flow of cream solder 6 stops at end face 9 of .

以上の状態でリフロ一槽により半田付されることにより
、チップ部品6の下面におけるチップ部品6の電極間の
半田ボールによる短絡の発生を防止することができる。
By performing soldering in one reflow bath in the above state, it is possible to prevent short circuits caused by solder balls between the electrodes of the chip component 6 on the lower surface of the chip component 6.

発明の効果 以上のように本発明によれば、配線回路基板の半田付ラ
ンド部に塗布するクリーム半田において、塗布量、半田
付ランドに対する塗布位置ズレが従来以上に発生しても
、半田付ランド間の半田レジストによりチップ部品下面
へのクリーム半田流れを防止でき、作業上における精度
に対する余裕度も併せて持たすことができ、チップ部品
の電極間の短絡を防止して半田付品質の改善を図ること
ができる。
Effects of the Invention As described above, according to the present invention, in the cream solder applied to the soldering land portion of a printed circuit board, even if the amount of application and the application position with respect to the soldering land occur more than before, the soldering land can be easily maintained. The solder resist in between prevents cream solder from flowing to the bottom surface of the chip component, and also provides margin for work accuracy, preventing short circuits between the electrodes of the chip component and improving soldering quality. be able to.

また、チップ部品の電極間の短絡、チェック検査、短絡
時の修正といった修正2作業工数も削減され、工数削減
を図ることができることになる。
In addition, the number of man-hours required for corrections such as short circuits between electrodes of chip components, check inspections, and corrections in the event of short circuits is also reduced, making it possible to reduce the number of man-hours.

また、本発明の他の実施例として、例えばアルミナ基材
を用いて、銀または銀合金、その他の金属ペーストを印
刷、焼成することによりアルミナ基材に配線回路部と半
田付ランドを形成し、半田付ランド以外の回路部をガラ
スコートしたアルiす配線基板においても、チップ部品
の電極部を半田接続するための半田付ランド間のアルミ
ナ基材面上にガラスコートe施すことにより、アルミナ
配線基板においても同じように構成し効果を出すことが
できる。
In addition, as another embodiment of the present invention, for example, using an alumina base material, a wiring circuit part and a soldering land are formed on the alumina base material by printing and firing silver or silver alloy or other metal paste, Even in aluminum wiring boards where the circuit parts other than the soldering lands are coated with glass, alumina wiring can be achieved by applying glass coating on the surface of the alumina base material between the soldering lands for soldering the electrodes of chip components. The same effect can be achieved on the substrate as well.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電子部品の取付装置における配線回路基
板を示す平面図、第2図は同基板の断面図、第3図は第
2図の基板上にチップ部品を装着した状態ヲ示す断面図
、第4図は第3図のりIJ −ム半田を硬化させた状態
を示す断面図、第5図は本発明の一実施例による電子部
品の取付装置における配線回路基板を示す断面図、第6
図は同基板にチップ部品を取付けた状態を示す断面図で
ある。 1・・・・・・配線回路基板、3・・・・半田付ランド
、4゜8・・・・・半田レジスト、5・・・・・クリー
ム半田、6・・・・・チップ部品。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第4図 第 5 図
Figure 1 is a plan view showing a printed circuit board in a conventional electronic component mounting device, Figure 2 is a cross-sectional view of the same board, and Figure 3 is a cross-section showing a state in which chip components are mounted on the board in Figure 2. 4 is a cross-sectional view showing a state in which the IJ-mu solder shown in FIG. 3 has been hardened. FIG. 6
The figure is a sectional view showing a state in which chip components are attached to the same board. 1... Wired circuit board, 3... Soldering land, 4°8... Solder resist, 5... Cream solder, 6... Chip parts. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] チップ部品の電極部が半田接続される半田付ランド間の
基板面上に、この基板上に配置されたチップ部品の下面
までの高さより高い寸法の絶縁層を形成したことを特徴
とする電子部品の取付装置。
An electronic component characterized in that an insulating layer having a dimension higher than the height to the bottom surface of the chip component placed on the substrate is formed on the substrate surface between the soldering lands to which the electrode portion of the chip component is soldered. mounting device.
JP24363784A 1984-11-19 1984-11-19 Electronic component mounting apparatus Pending JPS61121490A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24363784A JPS61121490A (en) 1984-11-19 1984-11-19 Electronic component mounting apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24363784A JPS61121490A (en) 1984-11-19 1984-11-19 Electronic component mounting apparatus

Publications (1)

Publication Number Publication Date
JPS61121490A true JPS61121490A (en) 1986-06-09

Family

ID=17106779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24363784A Pending JPS61121490A (en) 1984-11-19 1984-11-19 Electronic component mounting apparatus

Country Status (1)

Country Link
JP (1) JPS61121490A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0440568U (en) * 1990-07-31 1992-04-07

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5678189A (en) * 1979-11-30 1981-06-26 Matsushita Electric Works Ltd Electric circuit block
JPS56144596A (en) * 1980-04-10 1981-11-10 Tokyo Shibaura Electric Co Method of soldering chip carrier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5678189A (en) * 1979-11-30 1981-06-26 Matsushita Electric Works Ltd Electric circuit block
JPS56144596A (en) * 1980-04-10 1981-11-10 Tokyo Shibaura Electric Co Method of soldering chip carrier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0440568U (en) * 1990-07-31 1992-04-07

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