JPS61121392A - Manufacture of multilayer wiring - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing multilayer wiring used in various solid-state devices including semiconductor integrated circuits.

[Conventional technology]

Conventionally, this type of multilayer wiring has been formed by the Hiko method as follows. That is, taking 2r- wiring as an example, first a first layer of gold (F%) is deposited by sputtering or the like, and then the first layer is deposited using photolithography or reactive ion etching (RIE).
Wiring layer? Form. Subsequently, an insulating film is deposited using a vapor phase reaction method or the like, and connection holes (so-called through holes) are formed using photolithography or reactive ion etching. Finally, a second metal layer is deposited and patterned to form a second wiring layer.

[Problems to be Solved by the Invention J However, when attempting to miniaturize through holes and thicken interlayer insulating films, which are necessary for higher density and higher speed of HlLSI, using such conventional methods, However, there are some difficulties as described below.

The first point is that as the through hole becomes smaller and deeper, the processing to form the through hole in the insulating film becomes more difficult. Metal is not deposited sufficiently in the small and deep through-holes, and as a result, the connection resistance between the first wiring layer and the second wiring layer becomes large, and in extreme cases, a situation may occur where no connection occurs.

[Means for solving the problem] In order to solve these problems, this gA has developed interlayer insulation! In this embodiment, an interlayer connection portion for connecting one upper wiring layer to another upper wiring layer is formed independently before forming the upper wiring layer.

[Effect]

By forming the interlayer connection portion first, there is no need for the process of forming a small and deep through hole in the interlayer insulating film, or the difficult process of digging a conductor into the through hole.

〔Example〕

FIG. 1 shows -! of the present invention. J! 6 with process cut-out diagrams showing examples
9. The following will be explained in order.

A first wiring layer 2 is formed on a substrate 1, and then an interlayer metal layer 3f is deposited (FIG. 1(a)). In this case, the conditions that the first wiring layer 2 and the interlayer metal layer 3 should satisfy are that the first wiring M2 is not etched except for the etching of the interlayer metal layer 3;
Wiring layer 2f: At (or red alloy, hereinafter the same), interlayer metal layer 3tMo (or Mo alloy, hereinafter the same), Mo
It can be obtained by processing using cFa+02 plasma.

In Rurui, the first wiring layer 2 is made of At and M with Mo as the top layer.
It is also possible to form a laminated structure with gold, and use At gold as the interlayer metal layer 3, and process AA using 5iC2t metal or CC24 reactive ion etching. In the latter example, from the etching conditions, it goes without saying that the entire first wiring layer may be set as oo and At may be used as the first metal layer 3, but AtO has higher conductivity than Mo. The first wiring layer 2 has a multilayer structure with AA instead of Mo alone. In particular, only the top layer of the first wiring layer 2 is
.

The other parts including the interlayer connection part and the second wiring layer are made of A4.The following example can be said to be a desirable example in terms of low resistance.

After forming the interlayer metal layer 3 in this way, a resist i is applied on the interlayer metal layer 3 by a known method, exposed to light and 3J
A resist pattern 4 is formed by imaging. Then,
Using this pattern 4 as a mask, the interlayer metal layer is selectively processed by subsequent etching using the above-mentioned 92 gases,
An interlayer connection portion 5 that serves to connect the first wiring layer 2 and the second wiring layer is formed (FIG. 1(b)). When forming through holes in interlayer insulating films, it is difficult to supply sufficient etching gas to small and deep holes, so miniaturization and
Although it was difficult to make the film thicker, when forming the above-mentioned connection between 1 and 2, the processing becomes easier because sufficient etching gas is supplied around it, and there is no need to fill the t7t through hole with a metal layer. , miniaturization and thickening of the film.

Next, a heat-resistant organic coating film, such as polyimide, is spin-coated as the interlayer insulating film 6, and is stabilized by annealing at an appropriate temperature for 7 times (FIG. 1(C)). Thereafter, the entire surface of the interlayer insulating film 6 is etched to expose the upper surface of the interlayer connection portion 5 (FIG. 1(d)). The entire surface etching may be done by wet method or dry method, and in the case of dry method, 02RIE, O
F, RIE is used. Further, the interlayer insulating film 6 is not limited to a heat-resistant organic coating film, and may be a silicon nitride film or a combination of a silicon oxide film and an organic coating film. What is important is that the shape after the interlayer insulating film is formed and after the entire surface is etched is nearly flat.

Thereafter, a metal layer such as Alt is deposited, and a second wiring layer 7 is formed by photolithography and etching (
Figure 1(e)).

When trying to form a multilayer interconnection made of At, for example, by the conventional method, if a through hole is formed that completely crosses the first interconnection m', then more ht is deposited on top of the throughhole and the second interconnection is formed. When performing layer patterning, there is no problem if the second wiring layer is formed to completely cover the through hole, but due to misalignment, for example, the through hole may be perpendicular to the second wiring layer. If the positional relationship is such that the first wiring layer is exposed, the exposed portion will also be removed by etching, resulting in a disconnection. In order to avoid this, it was necessary to make the through hole sufficiently smaller than the wiring layer and to prevent it from protruding from the wiring layer; conversely, it was necessary to increase the width of the wiring layer. On the other hand, in the present invention, as described above, the uppermost part of the first wiring layer is made of a material that is not etched when etching the interlayer connection part, so when patterning the second wiring layer made of the same material as the interlayer connection part, However, even if the through hole is not completely covered, the first
A situation in which the wiring layer is disconnected can be avoided. Therefore, it is possible to make the interlayer connection portion 5 and the first wiring layer 2 have the same pattern width, which is also suitable for miniaturization.

The above is the basic process of the present invention. If terminals (pads) for power supply and signal input/output are to be provided only on the second wiring layer, the above basic process is sufficient, but if such terminals are also provided directly on the first wiring layer, The following problems arise.

That is, when an organic polymer layer is applied as an interlayer insulating film, for example, the organic polymer layer becomes thicker on the interconnection area where the pattern size is large, such as a pad area, than on the fine pattern. As a result, as shown in FIG. 2, the upper surface of the connecting portion 5 is not exposed due to etching, and the first wiring layer and the second wiring layer are not connected at that portion. To solve this problem, the following two methods are effective.

In the first method, as shown in Fig. 3, a large connection point such as a pad part is divided into interlayer connection parts 5A with small pattern dimensions, and the thickness t of the applied organic polymer is made uniform. . In addition, the broken line in the figure shows the expansion after applying the organic polymer layer.
The solid line shows the shape after etching the entire surface.

The second method, as shown in FIG. 4, uses photolithography after forming an organic coating film to create
Therefore, the problem can be solved by removing the thick part of the organic polymer film in advance. In this case, it is necessary to embed the metal in this portion when depositing the second wiring metal layer, but since the pattern size is originally large, it can be made relatively shallow and there is no problem.

In particular, if a wet etching method is used, the edges of the pattern can be sloped, making embedding easier. For example, polyimide as an organic polymer layer,
When a negative resist is used as the resist, by appropriately selecting the baking temperature, the polyimide can be etched by the resist developer, and the resist can be removed without affecting the organic polymer layer. In the figure, the broken line shows the shape after the polyimide is wet-etched and the resist is removed, and the solid line shows the shape after the entire surface of the polyimide gold is etched. This method uses wet etching, but as mentioned above, it is applied only to portions with originally large pattern dimensions, so it does not pose a hindrance to increasing the thickness of the interlayer insulating film.

The above description has been made using two-layer wiring as an example, and it goes without saying that by repeating the same process, it is also possible to manufacture wiring such as 3/il, 4/ii, etc. In addition, in combination with all conventional techniques of the present invention, through-holes may be used for subsequent connections at interlayer connection points with large pattern dimensions, and the present invention may be applied to form interlayer connection portions for fine connection points.

〔Effect of the invention〕

As explained above, according to the present invention, by forming the interlayer connection portion that fully connects the lower wiring layer and the upper wiring layer before forming the interlayer insulating film, fine through holes are not required. There are many benefits mentioned.

First, it frees us from the difficulties associated with processing fine through-holes and embedding metal into the through-holes, which makes it possible to use thick insulating films to create multilayer wiring, which increases the speed of LSIs.
Densification may also be an issue.

Furthermore, since the interlayer insulating film is also planarized, disconnections and short circuits in the wiring layer are eliminated, and the lead time and reliability are improved.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing one embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views for explaining other embodiments of the present invention, and FIG. 4 is a process sectional view showing another embodiment of the present invention. A cross-sectional view showing an example. DESCRIPTION OF SYMBOLS 1...Substrate, 2...1st wiring layer, 3.080 interlayer metal layer, 4***Resist pattern, 5.5A...
. . . Interlayer connection portion, 6 . . . Interlayer insulating film, 7 . . . Second wiring layer.

Claims (3)

[Claims] (1) Following the formation of the lower wiring layer, a process of depositing a conductor layer, a process of selectively patterning this conductor layer by photolithography and etching to form interlayer connections, and forming an interlayer insulating film A method for manufacturing a multilayer interconnection comprising the steps of: etching the entire surface of the interlayer insulating film to expose the upper surface of the interlayer connection portion; and subsequently forming an upper interconnection layer. (2) Claims characterized in that in the step of selectively patterning the conductor layer to form the interlayer connection portion, the interlayer connection portion is formed by a plurality of patterns for each required connection location. 2. The method for manufacturing multilayer wiring according to item 1. (3) A step of depositing a conductive layer following the formation of the lower wiring layer, a step of selectively patterning this conductive layer by photolithography and etching to form an interlayer connection, and forming an interlayer insulating film. a step of selectively patterning this interlayer insulating film by photolithography and etching, a step of etching the entire surface of this interlayer insulating film to expose the upper surface of the interlayer connection portion, and subsequently forming an upper wiring layer. A method for manufacturing a multilayer wiring, comprising the steps of: