JPS61120519A - Pulse width modulating circuit - Google Patents

Abstract

PURPOSE:To supply a transfer signal LD automatically without executing any instruction by providing a logical circuit which is actuated with the write signal of the latch circuit of the 1st stage and generates a transfer signal by ANDing a signal of every period of the latch circuit of the 2nd stage. CONSTITUTION:When one is set in a logical circuit 16, the contents of an 8-bit latch circuit 1 and a 6-bit latch circuit 2 are transferred to a 14-bit PWM circuit 3 and when zero is set, data is not transferred even in one period of a 14-bit binary counter 5. A write signal WR2 which sets zero and one makes it possible to judge whether data set in the 8-bit latch circuit 1 and 6-bit latch circuit 6 is set in the 14-bit PWM circuit 3 or not. A transfer signal LD is controlled by a logical circuit 6, so even if a noise generated in the 14-bit PWM circuit 3 during the setting of the data, there is no influence after the alteration of the data.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is a pulse width modulation (hereinafter referred to as PWM) circuit controlled by a microcomputer (hereinafter referred to as a microcomputer), etc., which is equipped with an 8-bit 1,000-tube microcomputer. [Prior Art] Figure 2 is a block diagram of a conventional data center device for a PWM circuit, in which 1 is an 8-bit latch circuit connected to a microcomputer's data bus. , 2 are 6-bit latch circuits that are also connected to the data bus, and these constitute the first stage latch circuit. 3 is a 14-bit PWM circuit to which data is set by the 8-bit latch circuit 1 and 6-bit latch circuit 2, which is the second stage latch circuit, and 4 is a data bus. The write signals WR,,wl, are each 8
This is for setting the 8-bit latch circuit 1, 6-bit latch circuit 2Vc data t from the bit data bus 4, and the transfer signal LD is to transfer 14-bit data from the 8-bit latch circuit 1, 6-bin latch circuit 2 to the 14-bit PWM circuit 3. It is a fancy transfer signal when it is transferred.

The conventional 14-bin PWM circuit is configured as described above, and when the 14-bit PWM circuit 3 & t data Z cents, the data bus 4 is 8 bits, so it is not necessary to set 14 bits of data at a time. Therefore, 8 bits, 6
I try to set the bit twice, but in the meantime,
The data output from the 14-bit PwM circuit 3 results in an error.

Therefore, the first stage latch circuit of 8-bit latch circuit 1 and 6-bit latch circuit 2 is provided in the middle, and the transfer signal LD is used to transfer 14 bits of data at once to the second stage latch circuit (14 bits) PWM. Cent to circuit 3. Conventionally, this transfer signal LD was supplied when a certain command was executed by a program.

[Problems to be Solved by the Invention] In the conventional PWM circuit as described above, the transfer signal LD is not supplied from the 8-bit latch circuit 1 and the 6-bit latch circuit 2 to the 14-bin PWM circuit 3 for data entry. Since this is done by executing certain instructions by a program, there are problems in that the program becomes large and complex, and the preparation for driving becomes complicated.

The present invention was made to solve this problem, and the transfer signal LD is automatically output without executing a command.
The purpose is to obtain a PWM circuit that can supply 1k.

[Means for solving problems]

The PWM circuit according to the present invention is provided with a logic circuit that is activated by the write signal of the first stage latch circuit and generates a transfer signal by ANDing the signals of the second stage latch circuit every cycle. .

[Effect]

In this invention, the logic circuit is activated by a write signal when data is written to the first stage latch circuit from the data bus in multiple batches, and one cycle of the second stage latch circuit is activated. The transfer signal is created by ANDing with each signal, so the transfer signal is automatically supplied.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.
4 indicates the same as the conventional example in FIG.
The 14 signals output from the digitizer 5 are also supplied to the PWM circuit 3. Qz+ is a signal obtained by AND processing these signals U 1 '-014, and 14
It is periodic with one period of the bit binary quanta 5. UO is a clock signal for the 14-bit PWM circuit 3, and 6 is a logic circuit forming a clock, which is the main element of the present invention.

It also outputs to the internal data bus. W.R.

is a write signal that sets the 6-bit latch circuit 2t and sends the logic circuit By1), and 7 indicates the logic circuit 6.
8 is also an AND circuit, which outputs the transfer signal LDY from the output of the signal Qz+ and the clock signal U.
Take the AND with O.

In FIG. 1 configured as described above, data t is transferred from the 8-bit data bus 4 to the 8-bit latch circuit 1 and the 6-bit latch circuit 2 using write signals WR, WR1Y.
Set each. After that, 8-bit latch circuit 1,
The data latched in the 6-bit latch circuit 2 is
Bin) The PWM circuit 3Vl is set, and the logic circuit 6 controls the transfer signal LDY supplied at that time. In the case of setting the logic circuit 6, the write signal WR2 is used when setting data l to the 6-bit latch circuit 2, and in the case of resetting, the signal Qz+ and the clock signal UO are generated every cycle of the 14-bit binary counter 5. are executed respectively. When the logic circuit 6VC “B” is sent,
When the contents of the 8-bit latch circuit 1 and 6-bit latch circuit 2 are transferred to the 14-bit PWM circuit 3 and '0'' is set, even if it is one period of the 14-bit binary counter 5, the data is There is no transfer. That is, the transfer signal LD is not supplied. "0" I for this logic circuit 6VC
The write signal WR, which is centered on IIP+, uses a 6-bit latch circuit (over 20 upper bins) Y, so 8
Bit latch circuit 1. 6-bin latch circuit 2Vc It can be determined whether the sent data is set in the 14-bit PWM circuit 3 or not. Furthermore, since the transfer signal LD is controlled by the logic circuit 6, when setting data,
14) Even if noise appears in the PWM circuit 3, it will have little effect after the data has been changed.

In the above embodiment, the 14-bin PWM circuit 3 has been particularly explained, but the PWM circuit 3 with other bit lengths in this set
A similar circuit can be used for the circuit.

〔Effect of the invention〕

As explained above, the present invention includes a logic circuit activated by a write signal from a data bus corresponding to a first stage latch circuit, and transfers data from the first stage latch circuit to the second stage latch circuit. signal t.

1' □
This saves the trouble of issuing signals for transfer when the program is busy, and has the effect of simplifying software processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data center device for a PWM circuit having a circuit that automatically supplies an LD signal according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional data set device for a PWM circuit. be. In the figure, 1 is an 8-bit latch circuit, 2 is a 6-bit latch circuit, and 3 is a 14-bit PWM circuit. 4 is data/(s), 5 is a 14-bit binary kakunta, 6 is a logic circuit, and 7.8 is an AND circuit. In addition, the same symbols in each figure indicate the same or equivalent parts. Agent Masutai Oiwa ( 2 others] Figure 2 Procedural Amendment (Voluntary) 1. Indication of the case Patent Application No. 59-241707 2,
Title of the invention Pulse width modulation circuit 3, Relationship to the case of the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation 5, Specification subject to amendment Detailed Description of the Invention Column and Drawing 63 Amendment Contents (1) "5 is a 14-bit binary counter" on page 5, line 4 of the specification is changed to "5 is a 14-bit binary counter that uses the input clock UO." to correct. (2) Similarly, on page 5, line 10, "-periodically." is corrected to "-periodically." (3) Also, replace “flag” on page 5, line 12 with “flag”
and correct it. (4) Similarly, on page 5, lines 14 and 15, "write signal that sets the logic circuit 6" is corrected to "write signal that sets the output Q of the logic circuit 6." (5) Similarly, on page 5, lines 15-16, "output of logic circuit 6" is corrected to "output Q of logic circuit 6". (6) Similarly, on page 5, line 18, insert the following after "Take an AND.""The output Q is an inverted signal of the output Q." (7) Similarly, "Set of logic circuit 6" on page 6, line 7 is corrected to "Set of output Q of logic circuit 6." (8) Amend Figure 1 of the drawing as shown in the attached sheet. that's all

Claims (2)

[Claims] (1) The number of bits of the output setting data is greater than the number of bits of the bus line, the latch circuit is configured in two stages, the first stage and the second stage, and the latch circuit of the first stage is connected to the bus line. Data is written multiple times, and after the total number of bits is written to the first stage latch circuit, the data is written from the first stage latch circuit to the second stage latch circuit using a transfer signal. In a pulse width modulation circuit that transfers data, a logic circuit that is activated by a write signal of the first stage latch circuit and generates the transfer signal by ANDing with a signal of each cycle of the second stage latch circuit. A pulse width modulation circuit characterized by being provided with. (2) The pulse width modulation according to claim (1), wherein the first stage latch circuit is 8 bits and 6 bits, and the second stage latch circuit is 14 bits. circuit.