JPS61120259A - Executing system for input and output instruction - Google Patents

Abstract

PURPOSE:To deliver simply an I/O instruction by checking a bus connected with an instruction executing priority bus and an I/O device and requesting the processing to a channel processor CHP of another system by means of an inter-CHP communication function in case the instruction is related with another system. CONSTITUTION:An instruction execution cue is set at an LS, for example, of channel processors CHP0 and CHP1 respectively. The central processors CPU0-CPU3 always produce the I/O instructions only for the CHP0 and CHP1 of their own systems. Receiving these I/O instructions, both processors CHP0 and CHP1 check the buses to which I/O devices DA and DB are connected as well as an instruction execution priority bus. If those instructions are related with other systems, both processors CHP0 and CHP2 use an inter-CHP communication function to request the processing to channel processors of other systems.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input/output instruction execution method in a computer system having a plurality of processors and channels [Prior art] A computer system having a plurality of processors and channels, It is constructed as shown in FIG. CPU0-CPU3 are multiple central control units, CHPO, CHP in this example.
In this example, 41 channel elements CHE are assigned to each channel element CHE, and a plurality of input/output devices (110 devices>DA , DB is connected. In the figure, C
CU for each CHE of HpQ, CHPI.

Although only the I10 device is shown, the same applies to other CHEs. Channel processors CHPO and CHPI preside over multiple input/output channels CHE, and CHPO
HUO, CPUI and main storage MSU, and also CHP
1 is CPU2. It is connected to the CPU 3 and MSU via system control units 5CUO and 5CUI. S.C.U.

The CHPs are connected by transmission lines ll and β2 and can communicate with each other.

CHPO, CHE, CU, DA and CHP 1°CHE
, CU, DB, etc. are called channel subsystems, and are of dynamic type in this example.

That is, the CPU communicates with the target device via SCU, CHP, CHF, CtJ, for example, CPU0 communicates with 5CUO, CH.
It connects to DA via PO, CHE, and CU, but this connection route is not fixed and connects to CPU0, 5 as shown by the dotted line.
CUO, CHPO, ll.

It may be a route such as CHPI, CHE, CU, or DA.

In other words, a variable route method is used in which if a certain route (path) is busy, another route is checked, and if it is an empty route, the target device is accessed through that route. Each device has a large number of paths, for example 8 paths, and the order in which the devices move if the device is busy is predetermined. This path also includes other CHPs, and the CHP determines the path. Furthermore, this system employs an asynchronous release type in which the CPU issues instructions as necessary, regardless of the processing status.

The instructions used in this channel subsystem are Dyna
mic channel subsystem function R
esume 5ubchannel instruction, 5Lart
5ubchannel instruction, Halt 5ubchan
nel instruction, C1ear 5ubchannel instruction,
and Re5etChannel Path commands, etc. When the CPU issues these commands, it returns a condition code and leaves the subsequent processing to the CHP. This method is very efficient from the CPU's point of view, but
From the perspective of the CHP, the next instruction is issued even though it is still being processed, so it is necessary to have an instruction queue.

[Problem that the invention seeks to solve]

Start 5ubc when the CPU boots the device
hannel instruction is issued, but the channel processor CHP
If there are multiple processors, the problem is which processor to pass the instruction to. In other words, it is better to pass the boot target device to the processor to which it belongs, but in order to do this, the CPU must know which device belongs to which processor and select the processor based on that. Then C.P.
The U exclusive time becomes long and the advantages of the asynchronous push-off type are diminished.

Another issue is where the instruction execution queue should be placed.

In a dynamic channel subsystem where the I10 device that is the target of the I10 instruction has paths to multiple CHPs, if it is busy when attempting to start up on one path, it is necessary to try starting up on another path. This requires a design that can be executed by two CHPs. The above requirements can be met by placing the instruction execution queue in an area that can be accessed by multiple CHPs (and CPUs), that is, in the MSU, but this method takes a long time to access, and the overhead of exclusive control with other devices is high. Large and disadvantageous.

The present invention has been devised in view of these points, and is intended to enable a CPU to easily issue input/output instructions, and to enable easy and quick access to an instruction execution queue.

[Means for solving problems]

The present invention provides an input/output instruction execution method for a computer system comprising a plurality of central processing units and a plurality of processor control channel devices, the channel processors having a mutual communication function, and configuring a dynamic channel subsystem.
Each channel processor is provided with an instruction execution queue, the central processing unit issues input/output instructions to its own channel processor, the channel processor enqueues the input/output instruction to its own instruction execution queue, and The present invention is characterized in that the path to the target input/output device is checked, and if the target input/output device belongs to another system, the communication function is used to enqueue the input/output instruction to the instruction execution queue of the other system channel processor.

In the present invention, the CPU always issues the I10 instruction to its own CHP.
Do this only for In response to this, the CHP checks the command execution priority path and the path to which the corresponding I10 device is connected, and if the command is related to another system, the CHP communicates with the other system and sends the process to the CHP of the other system. Make a request. In this way, the CPU can easily issue the I10 instruction, and the advantages of the asynchronous push-off type can be maintained.

Further, since the instruction execution queue exists independently in each CHP, the enqueue/dequeue operation of the I10 instruction can be performed easily and quickly.

〔Example〕

In a multiprocessor, multichannel computer system as shown in FIG.
Local Storage), and the CPU is I1
0 instruction is simply passed to the own CHP and enqueued (e
nqueue). Figure 2 shows CHPO.

The configuration of the instruction execution queue placed in CHP I is shown.

For each instruction execution queue where QO is placed in CHPO and Ql is placed in CHPI, selector SO,
The I10 instruction from the own system CPU is enqueued via the SL. The enqueued 10 instructions are dequeueed when they reach the top of the queue.
When the I10 instruction is about to be executed, it is checked whether the I10 instruction is for the own system I10. If it is the own system, it will be used for execution, if it is not the own system's Ilo, it will be sent to the other system's CHP.
The instruction is enqueued to the instruction execution queue Q1.

In this method, the CPU simply sends the r10 instruction to its own system CHP.
The burden is reduced because the I10 command is passed to the CHP.
If the instruction is an I10 instruction of another system, it is transferred to the other system's CHP upon execution, making queue access easier and faster than when the queue is placed in an MSU or the like.

If it is a 110 instruction of another system, the process of transferring it to the CHP of another system may be performed at the stage of enqueuing the I10 instruction from the CPU to the queue bottom. However, since this enqueue is performed as part of the start subchannel command, there is a problem in that adding the own system/other system discrimination and transfer processing to the other system is a heavy load. Generally, dequeue requires more processing steps than enqueue.

When the instruction execution queue is placed in the local storage LS of the channel processor CHP, the head pointer, bottom pointer, etc. of the queue can be placed in the LS, and the pointers can be referenced and updated easily. If the queue is placed in the main memory MSU, pointers will also be placed in the MSU, and each pointer reference/update will be performed by accessing the MSU.
Since many devices such as LS access the device, a lock byte is required to prevent other devices from accessing the device when the device is in the middle of accessing the device, but if it is placed in the LS and only the device itself is accessing it, the lock byte is not necessary.

〔Effect of the invention〕

As explained above, according to the present invention, a multiprocessor,
Enqueue/dequeue operations of ■/○ instructions in multi-channel systems can be performed with less burden on the CPU and on the MSU.
It is possible to perform necessary operations that require time, such as access, and is extremely effective.

[Brief explanation of drawings]

1 and 2 are block diagrams showing embodiments of the present invention. In the drawing, CPtJ is a central processing unit, CHP is a channel processor, 12 is a communication function, and Ql and Q2 are instruction execution queues. Figure 1 cpu eP dog handling rv, t4 placed MSU: Sat3koaCtC) IP Shiyanelp Ot-Nosa
L2: Through line DA, DB input/output thorns

Claims (1)

[Claims] In the input/output instruction execution method of a computer system that includes a plurality of central processing units and a plurality of channel processors, the channel processors have mutual communication functions, and constitutes a dynamic channel subsystem, each channel processor An instruction execution queue is provided, the central processing unit issues an input/output instruction to its own channel processor, the channel processor enqueues the input/output instruction to its own instruction execution queue, and also enqueues the input/output instruction to the target input/output device of the input/output instruction. 1. An input/output instruction execution control method, characterized in that the path to the input/output instruction is checked, and if the input/output instruction belongs to another system, the communication function is used to enqueue the input/output instruction to an instruction execution queue of a channel processor of the other system.