JPH021044A - Memory access control system - Google Patents

Abstract

PURPOSE:To improve the memory through-put of an information processor by constituting the information processor being capoable of outputting a bus right request from a storage control device to a bus arbiter when a request exists in the storage control device. CONSTITUTION:At the time of requiring the bus right of an S bus 300, bus requesters in instruction processors 10-a, 10-b, I/O processors 10-c, 10-d, and the storage control device 100 send bus right request signals 12-a to 12-d to the bus arbiter 20 in the device 100. The bus arbiter 200 waits the idle state of the bus and receives a request with the highest priority at a point of time corresponding to a bus idle cycle. The requester obtaining the bus right sends a request through the S bus 300. The device 100 checks whether a request address is included with the address setting range of the device 100 itself or not and receives only a request fitted to the address range. Thus, a memory access request is processed at a memory access time pitch, so that the through- put is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory access control system, and in particular to a method for controlling memory throughput of an information processing device in which an instruction processing device, an input/output processing device, and a storage control device are connected in the form of a bus. The present invention relates to a memory access control method suitable for increasing the number of users.

[Conventional technology]

First, the instruction processing device and input/output processing bag R (hereinafter collectively referred to as requester and io
A memory access procedure in an information processing device in which a storage control device (b) and a storage control device are connected in the form of a bus will be described.

FIG. 2(a) shows a read request procedure in a conventional memory access procedure. The requester sends a bus rights request (B) to the bus arbiter that arbitrates bus access rights.
USREQ) signal. Upon receiving this, the bus arbiter waits for a vacant bus and receives BUSRE requests from multiple requesters.
Among the Q signals, 1 is selected according to a predetermined priority order.
A bus request acceptance (BUSACP) signal is sent to one requester. The requester that received the BUSACP signal:
For example, as detailed information of a memory access request to the bus,
It sends out the memory address (SAB), a signal for distinguishing whether it is a read request or a write request, the data length, and write data in the case of a write request. Storage control unit ff (hereinafter referred to as rscU)
J, here assuming a 4-wafer interleaved configuration) receives the above detailed information from the bus and
A memory access procedure is started in steps O-3. When the memory access procedure is completed, the SCU sends a completion notification signal and detailed information on the completion to the bus, and the requester receives this. The detailed information is, for example, read data (Do"Ds on the SDR bus) in the case of a read request.

The SAB indicated by a broken line in FIG. 2(a) indicates a read request that is processed primarily. In the conventional SCU, once bus arbitration is completed and one requester acquires the bus right, the bus right is not released until the memory read or write is completed, and the primary access request is not accepted. In this way, continuing to monopolize the bus from the beginning of the bus transfer until the return of the bus transfer result has hindered the improvement of memory throughput and has become a bottleneck in improving the performance of the entire device.

As a method for eliminating the above-mentioned drawbacks and processing the next request at the timing shown by the broken line in FIG. It is being This technology has multiple buffers inside the SCU and requester, which hold bus access information, and attempts to accept the next request while the SCU is accessing memory. It is something.

[Problem to be solved by the invention]

However, the above-mentioned conventional technology does not specify what mechanism is used to accept the next request while the SCU is accessing the memory, and in particular, the SCU and multiple requesters are connected in the form of a bus. Bus rights arbitration, which is required when
It cannot be applied to improving the memory throughput of information processing devices connected in a bus format.

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in conventional memory access control systems, and to provide information processing in which the above-mentioned SCU and CPU are connected in the form of a bus. An object of the present invention is to provide a memory access control method that makes it possible to improve the memory throughput of a device.

(Means for Solving Eight Problems) The above-mentioned object of the present invention is to connect a requester such as an instruction processing device or an input/output processing device and a storage control device in the form of a bus, and to use a bus arbiter to control bus rights between the devices. In an information processing device that performs reception and reception, a buffer (a memory access waiting buffer between a memory access request accepted by the bus interface circuit and memory access control) is provided between a memory access circuit in the storage control device and a bus interface circuit. , and a bus output wait buffer between the memory access request processed by the memory access circuit and waiting to be transferred to the requester and the bus interface, and if there is a request in the bus output wait buffer, the corresponding The bus output wait buffer outputs a bus request different from the bus request from the requester to the bus arbiter, and the bus arbiter receives and receives the bus request based on these bus requests. This is achieved using a characteristic memory access control method.

Further, adding a signal indicating the number of bus usage cycles and a signal indicating the bus usage pattern to the bus request is also effective in improving bus throughput by accepting the next request at an early timing.

Furthermore, providing two bus control signal systems, one for request transfer and one for result transfer, is also effective in improving path throughput.

[Effect]

The above buffer is a buffer for requests waiting for memory access or bus output.

This buffer makes it possible to use this buffer to wait for a request to proceed when the memory is being accessed by a preceding request or when the bus is in use, allowing memory accesses and bus transfers to be performed as separate stages. It becomes possible.

Furthermore, in addition to the bus request from the requester to the bus arbiter, a bus request from the bus output waiting buffer is provided, and if there is a request in the bus output waiting buffer in the storage control device, the bus arbiter is sent from the storage control device to the bus arbiter. The bus arbiter receives the bus request from the storage controller.

By selecting other bus rights requests, the bus rights for sending the bus termination notification signal are obtained. As a result, the next request is accepted during the memory access, and the next memory access is started while the completion notification signal is being sent, and the memory access is performed at the memory access time pitch (or bus transfer cycle pitch). The request will be processed.

As a result, throughput is significantly improved.

In addition, in the bus request, a signal indicating the number of bus usage cycles,
By adding a signal indicating the bus usage pattern, the bus arbiter is notified of the bus type used and the number of bus cycles used from the requester, so it can perform bus arbitration based on this and accept requests for bus availability. B that corresponds to the predicted free cycle for the next request.
Can send USACP signals. This further improves the bus throughput.

Note that the most essential thing for producing the above effect is a bus request signal from within the storage control device.

This made it possible to separate the bus cycle and memory cycle stages. The buffer is important because it has the function of making the operation timing of this stage flexible.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block configuration diagram of an information processing device showing one embodiment of the present invention. The information processing device shown in this embodiment employs a multiprocessor configuration, and includes two instruction processing devices (I Po) 10-a.

(IPx) 10-b, two input/output processing units (IOPo
) 10-c, (IOPl) 10-d, 1 storage control bag [(SCU) 100 and 1 RAM (RAM) 30
A basic processing unit ff (BPU) 20 is configured by connecting the two through an S bus 300.

Command processing bag! (IPo) 10-a and (IPt) 10-b
, input/output processing bag R (IOPo) 10-a and (IOPr)
10-d, and the bus requester (request management 50o) in the SCU 100 sends bus request signals (BUSREQ) 12-a to 1 when the bus right of the S bus 300 is required.
2d and 12-r (described later) are sent to the bus arbiter 200. Bus arbiter 200 is here implemented inside SCU 100. The bus arbiter 200 waits for a bus to become vacant, and accepts the request with the highest priority when the bus becomes vacant. The requester who obtained the bus right.

Request (address.

Detailed information such as write data or read/write information) is sent.

The main memories of the BPU 20 (7), R and AM 30, have a 4-way interleave configuration and are assigned consecutive addresses. 5cutoo, the request address is the own SC
Checks whether the address is within the implementation range of U, and accepts only requests that match the address range.

FIG. 1 shows an example of the configuration of the 5CU 100. In the embodiment shown in FIG. 1, memory access control units 700-0 to 3
There are four RAMs 30-0 to 30-3, which operate in parallel as a 4-way interleave.

Ways O to 3 of the SCU shown in FIGS. 2 and 5 indicate that accesses to the RAMs 30-0 to 3 are performed in parallel for the 5CU 100 in the six implementations.

Bus arbiter 200 and S bus 300 perform bus rights arbitration
A bus interface 400 that interfaces with
, a request management unit 500 that synchronizes requests decomposed into four wafer interleave, a queue management unit 600-0 to 600-3 that is a buffer for requests for each way (hereinafter referred to as queues), and a queue management unit 600-0 to 600-3 for each way. Memory access control unit 700-0 to perform memory access of
It is shown as an LSI consisting of 700-3. However, some of the components, for example, the bus arbiter 200, may be
It may be taken outside the SI.

Before explaining the details of the 5CU 100 in FIG. 1, the S bus and the bus transfer signal will be explained with reference to FIG.

These interface signals are transmitted to the requester 10-i
(i=a, b, c, d, the same applies hereinafter) is defined between the request management 500, which will be described later, and the bus arbiter within the SCU 100. The requester 10-i includes a bus requester block (BR) 8-i, a bus interface block (BI) 6-1, etc. 6 First, a group of bus right transfer signals will be explained. A space request signal (
BUSREQi”r) 12-i-r indicates the existence of a no(space rights request) and its detailed information (i.e.
Request bus type signal (OUSTYPi”r) 14-
i to r and the requested bus usage cycle number signal (BUSCNTi
``r) 16-i = information on r) is valid.

Request bus type signal (BUSTYPi=r) 14-
i = r means that the bus request is data bus 5DB3
Data bus 5DB320 indicating whether or not 20 is used.
If it is used, it is a lie 1~request, and if it is not used, it is a read request. Request bus usage cycle number signal (BUSC
NTi~r)16-i=r is the data bus 5Dr332
Indicates the number of usage cycles of 0.

The bus arbiter 200 receives these bus request signals and sends a bus request acceptance signal (BUSACPi) depending on the bus usage status and the priority of the request.
=r) 20-i''r is returned to the requester 10-1.

When a bus right request is accepted, the request information is transferred using the S bus 300. In this embodiment, the S bus 300 is used to transfer the request information.
The usage of the bus 300 is classified into memory access request transfer and memory access result transfer. In the following explanation, the former will be referred to as a start-related bus procedure, and the latter will be referred to as an end-related bus procedure. a start-related control signal group 302 for controlling the address bus 5; an end-related control signal group 304 for controlling the end-related bus procedure;
It is composed of AB310, data bus 5DB320, and flag bus 5FB322. In addition, 5FB322
is the auxiliary information of data bus 5DB320, and 5DB32
This signal indicates which byte of the 4 bytes of 0 contains valid data.

Start-related bus procedures include read request transfer and write request transfer. For lead request transfers.

The read address is transferred by the address bus 5AB310, and at the same time by the start system control signal group 302.

Forward request details. In the case of write request transfer, write address and write data are transferred to address bus 5.
AB310 and data bus 5DB320, and at the same time, detailed information of the request is transferred using start-related control signal group 302.

Similar to the start system, the end system bus procedure includes read result transfer and write result transfer. For lead result transfer,
Transfer read data via data bus 5DB320,
At the same time, detailed information of the request is transferred using the end system control signal group 304. In the case of write result transfer, only the detailed information of the request is transferred using the end system control signal group 304.

The start system control signal group 302. consists of a command signal BSACT330 that indicates whether valid information is carried in the start-related signal group, a BSRD332 that indicates whether it is a read request or a write request, and whether it is a normal read or write request or another bus use request. Type signal BSTYP334 indicating the type of data bus, B indicating the number of data bus usage cycles
SCNT336, BS that identifies the requesting unit
UNT338 request source request check number BS
It is composed of CHK340. BSLINT33
8゜BSCHK340 is information attached to the request, SC
When the process ends at U, similar signals in the end system control information group at the time of end transfer (BEUNT, BECHK described later)
Based on BEUNT, the request source determines whether the termination notification is for its own device or not, and B E CHK.
Based on this, the end notification is made to recognize which request among the plurality of unconfirmed requests issued by the own device is sent. The bus interface 6-i of the request 10-1 is BE
If UNT matches the number of the own device, a termination notification is captured.

Next, the end system control signal group 302 is a command signal BE indicating whether or not valid information is carried on the end system signal group.
ACT350, B indicating read request or write request
ERD352, BE indicating the number of data bus usage cycles
CNT354, BEUNT indicating the requesting unit
356. It is composed of BEC11K358.

FIG. 5 shows the timing relationship between the S bus 300 and the bus transfer signal explained in FIG. 4. In the case of read and write, 5CLI is set according to the start bus procedure.
Transfer the request to 100, and RAM3 with 5CU100
Reading or writing to 0 is performed, and the result of the request (read data, write completion notification, etc.) is transferred to the request source according to the end-related bus procedure, and the process ends.

In the case of the read shown in FIG. 5(a), in the start-related bus procedure, the requester that has acquired the bus right sends the start-related control signal group (indicated by BSACT330) and the address (S
AB310) is sent. Furthermore, in the end system bus procedure, when the processing (read) within the 5CU 100 progresses to a certain point, a bus request signal BUSREQr12-r is sent to the bus arbiter 200, and after acquiring the bus right, the SCU 100 sends a group of end system control signals. (BEACT3
50) and data (SDB320) are sent.

In the case of the write shown in FIG. 5(b), in the start-related bus procedure, the requester sends out a start-related control signal group, an address (SAB 310), and data (SDB 320). Furthermore, in the end system bus procedure, the 5CU 100 sends out a group of end system control signals.

The bus arbiter 200 in FIG.
(i = a ” d, the same applies hereinafter) and a bus request signal (BLISREQi) from the request management unit 500.
)12-i, (BUSREQr)12-r
and other signals (BUSTYPi, BUSTYPr,
BUSCNTi, R11SCNTr), performs bus arbitration and sends a bus request acceptance signal (BUSACPi) 20- to the accepted request source.
i, (BUSACPr) 20- returns r.

The bus interface 400 is an interface unit with the S bus 300, and accepts requests and transfers memory access results. At the request reception, the start bus procedure is accepted, the request management unit 500 sends the helicopter construction reception notification signal TRUP 830, and the queue management units 600-0 to 38 receive the queue reception notification signal TQ (0 to 3).
) Send detailed information such as tJP 820-0 to 3, addresses 840-0 to 3, data 842-0 to 3, etc. In addition, when transferring memory access results, the request management unit 500
Upon receiving the end system bus request signal RUSOUT82g, the queue management units 600-0 to 600-3 send the BUSOUT
Sends O~3834-0~3 and receives output information (fetch data, etc.) 844-0~3. Bus interface 4
00 receives this and starts the end system bus procedure.

The memory access control units 700-0 to 700-3 are RAM 30-
This block performs read or write access procedures for 0 to 3, and addresses 850-0 to 3 sent from the queue management unit 600-0 to 600-3 and store data 85-3.
2-0 to 3 and the control information, the access operation is started using the ACCREQ signals 836-0 to 3 as activation signals, and the fetch data 854-0 to 3 etc. are started using the ACCEND signals 838-0 to 3 as completion notification signals. Queue management section 6
This block, which returns to 0-3, is similar to the conventional memory access control method.

The queue management units 600-0 to 600-3 are connected to the bus interface 4
00 and the memory access control unit 700-0 to 3 or the memory access control unit 700
It exists between the bus interface 400 and the bus interface 400, and serves as a buffer. Therefore, the bus procedure and memory access procedure do not necessarily need to be processed as continuous operations fixed in time. In other words, bus procedures and memory access procedures can be run as separate stages, and furthermore,
It becomes possible to perform pipeline operation. As mentioned above, the memory access control unit 700-0 of 5cutoo
3 are 4-way interleaved, so there are four queue management units 600-0 to 600-3, which are buffers with the bus interface 400. A request accepted by the bus interface 400 is decomposed according to the lower two bits of its BSCNT 336 and 5AB 310, and is sent to the four queue management units 600-0 to 3 described above.
will be queued. Queue management section 600-0 to 3
manages queued requests that are decomposed into each way (hereinafter simply referred to as a "queue" in contrast to the "request queue" of the request management unit 500).

The queue management units 600-0 to 600-3.

TQ (0 to 3) UP signals 832-0 to 3 are used as instruction signals to send queues from the bus interface 400 (specifically, addresses 840-0 to 3. store data 842-0 to
3 and detailed information) and latch it. Sends the received queues to the memory access controllers 700-0 to 700-3 in the order of reception,
Using the BUSOUT signals 834-0 to 834-3 from the bus interface 400 as instruction signals, the queue received from the memory access control sends the fetch data 844-0 to 3, etc. to the bus interface 400 in the order of reception. A request accepted by the bus interface 400 is sent to the queue management 60 when the memory access control 700-0 to 3 is busy.
Buffered from 0-0 to 3, but memory access control 7
When 00-0 to 3 become free, they are transferred and memory access is performed. If the bus cannot be output immediately after access is completed,
It is buffered by the queue management 600-0 to 600-3, but is transferred when bus output becomes possible, and is transferred to the bus interface 400-3.
is output from.

The progress status of each of the queue management units 600-0 to 600-3 described above progresses independently without synchronization with other queue management units. For this reason, memory access control units 700-0 to
It is possible to eliminate the waste that occurs in the case of a synchronization method, where a part of queue 3 is busy, so other queues are waiting for processing even though there are subsequent queues. memory throughput. On the other hand, there is a synchronization problem when outputting the requests decomposed to each of the queue management units 600-0 to 600-3 via the bus.

The request management 500 is in charge of this synchronization function. In large machines, the SCU sends data to the IP without synchronization, and synchronizes it on the IP side.1 In the case of processors connected in a bus format, which is the subject of the present invention (in the case of small machines),
SC synchronization is preferable to the method of sending out to the bus with synchronization information.
The method of taking and sending data within the U has a simpler bus interface, easier IP control, and relatively easier control within the SCU. This synchronization method will be explained below.

The synchronization of disassembled requests that progresses independently in each queue management unit 600-0 to 600-3 is such that when the SCU receives a request, the request management unit 500 assigns an identifier (token) unique to the request to each disassembled queue. In addition, when the memory access is completed, it is necessary to detect whether or not all the tokens of each decomposed queue are present (matching is detected), and if they are complete (matching is established), the bus right is granted. This is possible by requesting the bus arbiter 200 and outputting a termination notification to the S bus 300 based on the end bus procedure. These tokens are request order numbers (token numbers) that are added to requests received by the SCU 100 in the order of reception, and are, for example, four numbers from O to 3. This token number is 0, 1, 2, 3.
The processing of each request, which operates cyclically in the order of O, . The block that manages this token number and synchronization is the aforementioned request management section 500.

First, the operation of adding tokens to each decomposed queue will be described. As mentioned above, the bus interface 400
When receiving a request, sends a request acceptance notification signal T
The RLIP 830 is sent to the request management section 500. In response to this, the request management unit 500 issues a token number (T
R), and registers the received request information (details will be described later) at the last tail of the request queue, and at the same time sends a new TR to the queue management units 600-0 to 600-3 using TRNUM874.

Next, matching detection at the end of memory access and bus request operation will be described. Request management 500
sends a signal (MQN) of the token number (MQ) of the queue whose memory access has been completed from the queue management units 600-0 to 600-3.
UM O~3) 872-0~3, and compares this with the request information and token number in the request management section 500.

When the token numbers of all disassembled queues match the token numbers in the request management 500 (when matching is established), MATCHO~3 (870-0~3)
* is sent to the corresponding queue management section 600-0 to 600-3. Queue management O~3 (600-0-3) is MATCHO~3
(870-0-3), the pointer indicating the matched queue is counted up. When a new matching is established (including when matching is established but there is a request waiting for bus output), the request management unit 500 sends a BUSR to the bus arbiter 200.
EQr signal 12-r is sent. Bus arbiter 200 to B
Upon receiving the USACPr signal 20-r, the bus interface 400 outputs the previous u8 US OUT signal 82.
Send 8. As described above, upon receiving this, the bus interface 400 transfers the memory access result.

As mentioned above, each Wayi that is proceeding independently can be
t, 5 It becomes possible to synchronize and complete memory access within the CU 100.

Next, a detailed configuration example of each block of the 5CTJ that performs the operations described so far will be described.

FIG. 6 is a configuration diagram of the bus arbiter 200.

The bus arbiter 200 shown in this embodiment has requesters (IPo1O-a, IPlo-b, IPo1O-b and IPlo-b shown in FIG.
OP o 10-c, etc.) compatible reception judgment circuit 210
-i (i=a-d, as mentioned above), request management 50
0-compatible reception determination circuit 210-r.

In acceptance determination circuits 210-i and 210-r.

Start bus procedure, end bus procedure, data bus 5
Counter latch (STARTc) indicating how many cycles the DB 320 has already been accepted for use 232. (EN
DC) 234.

(SDBC) 236 exists, and the value is updated every cycle by subtractors 222, 224, and 226 until the value becomes O. The latches 232 and 234 are connected to a data bus (SOB).
) 320 is used, the number of usage cycles of the SDB is set, and when not used, "1" is set. Among the values of these latches, the bus request signal (BUSREQi
, BUSREQr, BUSTYPi, BUSTY
Pr.

BUSCNTi, BUSCNTr) requires funds (
If each control signal 5DB320) indicates O (vacant), the bus availability signal RESFREEi-r 2
50-i or 250-r is turned ON.

The priority determination circuit 260 selects a plurality of bus availability signals (RESFREEi=
r) Bus use permission signal (from among 250-i-r)
BLISACPi"r) 20-i-r is determined, and the corresponding signal 20i"r is turned on. In order to shorten the request processing time, end-related requests (requests from inside the SCU) are given top priority, and below, start-related requests from external requesters 10PO (10-c) are given top priority.

l0PI (10-d), IPO (10-a).

The order is IPI (10-b). Therefore, RESFR
If the EEr signal 250-r is on, the BUS is unconditionally
ACPr signal 20-r is turned on. If some of the start bus availability signals (RESFREEi) 250-i are on, the one with the highest priority is set to RESFR.
It will be expressed as EEip. RESFREEr signal 2
50- If r is off, and RESFREEr signal 2
Even if 50-r is on, if both 5DB320 are not used (more specifically, if the end-related request is a read request and the start-related request is a write request; this is the case when the BUSTYPi”r signal 14-i 5LlsAcPip signal 2O-ip is turned on. This priority determination circuit 260
As a result, as long as requests do not collide when using the 5DB 320, it becomes possible to accept start-related requests and end-related requests simultaneously, and the throughput of the bus is greatly improved.

Counter latch 5 TARTC232, ENDC234,
5DBC 236 is updated as follows. The priority determination circuit 260 accepted (BUSACPi=t, 20
It is necessary to update the value of the counter latch (STARTC232, etc.) used by the request (i"r turned on) to the number of accepted cycles.Set counter selection circuit 2
70 is the BUSACPi-r signal 20i-r and B
An update instruction signal 274 is sent to the latch to be updated based on the USTYPi-r signal 14 i = r. The selector switching signal 276 is.

If the latch value (value of signal 278) is zero, it instructs to select the output signal from counter set value selection circuit N272, and if it is other than zero, it instructs to select the output of subtracters 222, 224° 226. Counter set value selection circuit 272
is the BUSACPi”r signal 20- i = r and BU
Based on the STYPi-r signal 14-i''r, the BIJSCNTi=r signal 16 corresponding to the latch to be updated.
- When sending the value indicated by i ” r or rlJ 6 “1”, in the case of a request that does not use 5DB320, that is, the BUSTYPi~r signal 14-i ” r
is zero or more, the counter latch 23
When accepting a new request, the value of 2,234,236 is updated to the cycle reserved for use, and non-zero counter latches are decremented by 1 every cycle. As a result, the counter latch holds a value indicating how many remaining cycles are reserved for use.

FIG. 7 is a configuration diagram of the bus interface 400.
In the figure, BSACTB430. BSRDB432
゜BSTYPB434. BSCNTB436. B.S.
LINTB438 is a launch signal control signal for start signals. Also, 5ABB410 is the latch of 5AB310, 5DBB420 is the latch of 5DB320, BEACT
B450. BERDB452. BECNTB454
．． BEUNTB 456 are each latches for end signal control signals.

First, we will discuss start system reception. The start system signal control signal is the latch 430, 432, 434°436
．． 438 and the decoder 460
If 434 is a request other than cancel access, signal 461 is turned on. Further, the comparator 464 has 5 AB
The address latched in B410 is 5CU100
If it exists in the address range that should be handled by
Turn on. Furthermore, if the BSACTB 430 is ON, the TRUP signal 830 is turned ON and the request is accepted.

The control circuit 462 sends a queue acceptance notification signal TQ (0 to 3) UP832-0 to the queue management units 600-0 to 600-3.
At the same time as ~3, address 840-〇~3, data 842
-0 to 3 and control signals 841-0 to 841-3. This queue acceptance notification signal TQ (0 to 3) UP832-0 to 3
together with the TRUP signal 830, the request management unit 5
00 is also sent and latched together with the detailed request information 831.

Next, the end system transmission will be described. BtlSOIJT82g and detailed information 8 from the request management unit 500
29, the control circuit 466 controls the queue management unit 60
For 0-0~3, BUSOUT O~3 (834-
0 to 3). Queue management unit 600-0 that received this
When fetch data 844-0 to 3 is sent from ~3,
The control circuit 466 starts the end system bus procedure, switches the selector 470, and closes the end system control signal latches 450, 4.
Controls 52,454°456 and outputs the bus.

FIG. 8 is a configuration diagram of the request management section 500. The request management unit 500 shown in this embodiment includes a control information table 530 in which request control information is stored,
A latch HR5LO that holds this control information table 530 management address (using the token number);
TR512゜MR514 and matching unit 56
Consists of 0. The control information table 530 is made up of four registers 540, 542, 544 and 546. Adder 516.51
8,520 is used for counting up pointer information.

TR512 and HR510 are latches that hold the token numbers of the last and first accepted requests in the request management unit 500, respectively.

MR 514 is a latch that holds the token number of the next request to be matched. The control information table 530 includes LINT530-a, CHK53
0-b, Way (0-3) 530-c, C
It consists of 5 fields: NT530-d and RD530-e. Way (0-3) 530-c is
The queue control number (Way number) where the queue exists, indicating which Way queue control the request was divided into.
110 I+ is present, and 111 I is present where it does not exist.
+ are respectively latched (the logical meaning is reversed).

Explain request latching. When the bus interface 400 accepts a start-related request, it sends a count-up signal TRUP 830 of the TR 512 to the request management section 500. In response to this, the TR 512 counts up, and the decoder 532 indicates the position of the control information table 530 corresponding to the token number indicated by this TR 512.

In the register in the control information table 530 pointed to by this decoder 532, control information of the new request, that is, detailed information 831 of the request, Way (0 to 3), and queue acceptance notification signal TQ (0 to 3) UP832-0
~3 is latched.

Next, the matching mechanism will be explained based on FIG. When the processing in the memory access control units 700-0 to 700-3 is completed, the queue management units 600-0 to 600-3 transmit the talk number MQNUM O of the next queue to be matched.
~3 (872-0~3) is sent. This MQNUM
O~3 (872-0~3) compares the value of the token number with the token number value of the MR 514 through the comparators 550 and 552.
, 554, 556, and if there is a match, 111 I+
Output. This output and the way information (530-c) of the register of the control information table 530 output by the selector 572 with the number pointed to by the MR 514 are logically ORed by the OR circuit 580°582, 548, 586, and the corresponding queue is When all processing is completed, the signal 562 turns ON.
becomes. As a result, the MATCHO~3 signal (
870-0~3) are sent.

Count up MR514.

Next, the process of terminating the request, that is, acquiring the bus right,
Sending request information to the bus interface 400 and starting the end-system bus procedure will be explained. MR51
4 is counted up, etc., the above HR5
10 and the value of MR514, which means that there is a request for which matching has been established but no completion notification has been output to the bus. ) turns ON.

When the response signal eUsAcPr (20-r) in response is sent from the bus arbiter 200, the HR510 is counted up, and among the information in the control information table 530 output by the selector 570 corresponding to the value of this HR510, UNT530- a, CHK530-b
.

CNT530-d and RD530-e are BUSO
Pi interface 400 in synchronization with UT signal 828
sent to. The bus interface 400 latches these and starts the end system procedure based on the instruction of the BLISOUT signal 828.

FIG. 9 is a configuration diagram of the queue management units 600-0 to 600-3. The queue management units 600-0 to 3 transmit or receive information to or from the memory access control units 700-0 to 700-3 (i.e., address 630-a, store data 630-b, control information 630-c, fetch data 630-e). , a queue information table 630 that holds the token number 600-d), and a latch HQ 616. that holds the management address of this queue information table 630. MQ614. AQ6L
2 and TQ610. Note that the queue information table 630 includes four registers, 640
, 642, 644 and 646.

TQ610. HQ616 is a queue management section 60〇-0～
0MR614, which is a latch that holds the queue numbers of the last and first accepted queues among the three queues, is
Next is a latch that holds the queue number of the queue for which matching is to be established.

The AR612 currently has the memory access control unit 700-〇~
This is a latch that holds the queue number being processed by the memory access controllers 700-0 to 700-3, or the queue number to be processed next if the memory access control units 700-0 to 700-3 are not processing.

First, let's talk about cue latching. When TQj and tJP832-i are sent from the bus interface 400, TQ610 is counted up, and the queue information table indicated by the decoder 622 indicates the position of the queue information table 630 corresponding to the queue number indicated by TQ610. The new queue information is stored in the register in 630, i.e. address 840-1p store data 8.
42-1. Control information 841-i is latched.

TQ610 is counted up and there is a difference between it and AQ612, or the memory access control unit 700-
When ACCENDi 838-i is sent from AQ 612, the control circuit 670 latches the data 854-0 to 854-3 to the fetch data 630-e pointed to by the decoder 624 that received the signal from AQ 612, and then outputs the signal 672. According to
The AQ 612 counts up, and the queue control table 6 selected by the selector 674 is sent to the memory access control units 700-0 to 700-3 in synchronization with the ACCREQi 836-i.
30 information 850-i and 852-i are sent.

Next, the matching mechanism on the queue control side will be explained. The token number 630-d of the queue selected by the selector 676 according to the value of MQ614 is MQNUMi87.
2-i is sent to the request control unit 500. When the request control unit 500 receives MATC)li870-i indicating that matching has been established, M
The value of Q614 is counted up and the token number of the queue to be matched next is MQNUMi872-i.
send to

Finally, the termination procedure will be explained.

When 8υ5OUTi834-i is received, the value of HQ616 is counted up. With this updated value, the end information (fetch data 630-e) of the queue information table 630 selected by the selector 678 is changed to the data signal 844.
-i to the bus interface 400.

Although one embodiment of the present invention has been described above, further embodiments as described below can be easily realized.

First, when transferring block fetch target data to the bus, by performing the transfer in the first cycle, IP
The number of processing waiting cycles on the side can be reduced. This means that in the bus interface 400 that receives the request, information indicating the way of the generated target data is held in the request control unit as part of the control information, and when outputting from the bus,
Send to bus interface 400. This can be realized by receiving this and controlling the bus interface 400 to send the target data in the first cycle.

Second, the bus interface 40 that accepted the request
0, bus output order information of each queue is sent as control information to queue control units 600-0 to 600-3, and based on this information, queue control units 5oo-o to 3 select queue control units 600- with a later bus output order. By sending the MQNUMi 872-i early in accordance with the sequence order, unnecessary matching waiting cycles can be prevented from occurring and the average number of access cycles can be reduced.

Further, in the above embodiment, the case where the data bus width is 4 bytes and the number of ways is 4 is given as an example, but the present invention is not limited to this, and for example, the memory access control unit It is possible to easily configure a 2-way mode in which the request control unit has 2 ways of queue control units, and when each way completes fetching 4 bytes twice, or a similar I-way mode, which reduces costs. It is possible to provide memory throughput accordingly.

In addition, in the above embodiment, only a few ScUs are connected to the S bus, but in addition to the 5CU100, an additional 5C with a built-in requester that requests end-system bus rights without an arbiter is also available.
A configuration in which U102 is connected to the S bus can also be easily realized.

In this example, 5CU100 and additional SCU are:
Receives a start request from the S bus, checks the address range in the bus interface block,
The bus arbiter 20 of 5 CU 100 separates requests and handles end-system bus rights requests from additional SCUs.
0 is accepted in the same way as an end-system bus right request from within the 5CU 100. This additional SCU enables more flexible memory expansion.

〔Effect of the invention〕

As described above, according to the present invention, in an information processing device in which a memory access request such as an IP or IOP and an SCU are coupled in a bus format, and a bus arbiter transfers bus rights between the devices, the SCU A memory access wait buffer is provided between the memory access circuit and the bus interface circuit in the bus interface circuit between the memory access request accepted by the bus interface circuit and memory access control, and a memory access wait buffer is provided between the memory access request accepted by the bus interface circuit and memory access control. A bus output waiting buffer is provided between a memory access request and a bus interface, and when a request exists in the bus output waiting buffer, a request is sent from the bus output waiting buffer to the bus arbiter, and from the requester to the bus arbiter. Since the configuration is configured to output a bus right request different from the bus right request, a memory access control method that makes it possible to improve the memory throughput of an information processing device to which the aforementioned SCU and requester are connected in the form of a bus is implemented. This has the remarkable effect of being achievable.

[Brief explanation of the drawing]

FIG. 1 shows an SCU of an information processing device showing an embodiment of the present invention.
2 is a comparison time chart of the conventional method and the method of the present invention, FIG. 3 is a block diagram of an information processing device showing an embodiment, and FIG. 4 is a diagram showing the S bus and bus right reception/transfer. Explanatory diagram of the issue, Figure 5 is the time chart of the S bus,
6 is a configuration diagram of the bus arbiter shown in FIG. 1, FIG. 7 is a configuration diagram of the bus interface, FIG. 8 is a configuration diagram of the request management section, and FIG. 9 is a configuration diagram of the queue management section. . 10-a, 10-b-instruction processing bag [(IP), 10-
c, 10-d-Population processing unit (IOP), 2
0--Basic processing bag fff (BPU), 30-RAM
, 100...Storage control unit (SCU), 200...
- Bus arbiter, 300... S bus, 400... Bus interface, 500... Request management section, 6
0o-〇~3... Queue management department, 700-0~3...
・Memory [Omotekata Ujitomi 2 Figure (Mu2 Figure 2 (b) S bus ay 3 2:::X2] Figure 2θ Tomi Figure b Figure ■ Prisoner

Claims (1)

[Claims] 1. A requester device that generates a request for memory access and a storage control device that processes the request are coupled in the form of a bus, and a bus arbiter controls the transfer of bus rights between the devices. In the information processing device that performs the above processing, if there is a request waiting to be output to the bus in the storage control device, a request for bus right from the storage control device to the bus arbiter, and a bus right request from the requester device to the bus arbiter, is made. A memory access control system characterized in that it is configured to output a bus right request. 2. The storage control device has a bus interface circuit and a memory access circuit, a bus output waiting buffer is provided between the bus interface circuit and the memory access circuit, and an access end signal from the memory access circuit is provided;
2. The memory access control method according to claim 1, wherein a signal indicating the presence of a bus output wait request from within the bus output wait buffer is used as the bus request signal. 3. The memory access control system according to claim 1, characterized in that a signal indicating the number of bus usage cycles is added to the bus right request. 4. The memory access control method according to claim 1, wherein a signal indicating a bus usage mode is added to the bus right request in addition to a signal indicating the number of bus usage cycles.