JP2718702B2 - Memory access control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control system, and in particular, to a memory throughput of an information processing device in which an instruction processing device, an input / output processing device, and a storage control device are connected in a bus format. The present invention relates to a memory access control method suitable for improving the memory access control method.

[Conventional technology]

First, a description will be given of a memory access procedure in an information processing device in which an instruction processing device or an input / output processing device (hereinafter, collectively referred to as a requester) which is a memory access request source and a storage control device are connected in a bus format. .

FIG. 2A shows a read request procedure in a conventional memory access procedure. The requester sends a bus right request (BUSREQ) signal to a bus arbiter that arbitrates the bus access right. Upon receiving the request, the bus arbiter waits for an empty bus, and sends a bus request acceptance (BUSACP) signal to one of the requesters in accordance with a predetermined priority from among the BUSREQ signals from the plurality of requesters. BUSACP
Upon receiving the signal, the requester sends to the bus, for example, a memory address (SA
B), a signal for discriminating between a read request and a write request, a data length, and in the case of a write request, write data and the like are transmitted. The storage controller (hereinafter referred to as "SCU"), which assumes a 4-wafer interleave configuration, receives the above detailed information from the bus, and activates a memory access procedure in Ways 0-3. When the memory access procedure is completed, the SCU
Sends an end notification signal and detailed end information to the bus, and the requester receives this. For more information, for example, in the case of a read request, and the like (D ₀ to D ₃ of SDB on the bus) read data.

The SAB indicated by a broken line in FIG. 2A indicates a read request to be processed next. Conventional SCUs do not release a bus right after a bus arbitration is completed and one requester acquires the bus right until the memory read or write is completed.
The next access request has not been accepted. in this way,
Keeping the bus occupied from the beginning of the bus transfer until returning the result of the bus transfer prevents memory throughput from improving,
In addition, it has been a net to improve the performance of the entire apparatus.

As a method for processing the next request at the timing shown by the broken line in FIG. 2 (b) by eliminating the above-mentioned disadvantages, a technique disclosed in Japanese Patent Application Laid-Open No. 55-97655, "Memory Access Method" is known. Have been. This technology has multiple buffers inside the SUC and the requester, respectively, which holds bus access information and makes it possible to accept the next request while the SCU is performing memory access. It is.

[Problems to be solved by the invention]

However, the above-mentioned prior art does not specify what mechanism accepts the next request while the SCU performs memory access, and in particular, the SCU and a plurality of requesters are connected in a bus form. Since the arbitration of the bus right required in the case of the above has not been solved, it cannot be applied to the improvement of the memory throughput of the information processing apparatus connected in the bus form.

The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above-described problem in the conventional memory access control method, and to deal with information processing in which the above-described SCU and CPU are connected in a bus format. It is an object of the present invention to provide a memory access control method capable of improving a memory throughput of a device.

[Means for solving the problem]

The above object of the present invention is to provide an information processing apparatus in which a requester such as an instruction processing device or an input / output processing device and a storage control device are connected in a bus format, and a bus arbiter transfers a bus right between the devices. Between the memory access circuit and the bus interface circuit in the storage controller, a buffer (a memory access waiting buffer between the memory access request accepted by the bus interface circuit and the memory access control) and a process performed by the memory access circuit Buffer for waiting for a bus output between a memory access request waiting for transfer to the requester and the bus interface)
When a request is present in the bus output waiting buffer, a bus right request different from the bus right request from the requester to the bus arbiter is output from the bus output waiting buffer to the bus arbiter, The bus arbiter is achieved by a memory access control system characterized in that the bus arbiter is configured to transmit and receive a bus right based on the bus right request.

It is also effective to add a signal indicating the number of bus use cycles and a signal indicating the bus use mode to the bus right request in order to receive the next request at an early timing and improve the bus throughput.

Providing two systems of bus control signals for request transfer and result transfer is also effective in improving bus throughput.

[Action]

The above-mentioned buffer is a buffer for a request for a memory access wait or a bus output wait. By using this buffer, when the memory is being accessed by a preceding request or the bus is being used, the progress of the request can be made to wait by using this buffer, and the memory access or bus transfer can be operated as an independent stage. Will be possible.

Further, a bus right request from a bus output waiting buffer is provided separately from the bus right request from the requester to the bus arbiter. If a request is present in the bus output waiting buffer in the storage controller, the storage controller sends the bus right request to the bus arbiter. A bus right request is sent, and the bus arbiter selects a bus right request from the storage control device and another bus right request to obtain a bus right for transmitting a bus end notification signal. As a result, the next request is accepted during the memory access, and the next memory access is started while the end notification signal is being sent, and the memory access time pitch (or bus transfer cycle pitch) is used for the memory access. The request will be processed. As a result, the throughput is greatly improved.

Also, by adding a signal indicating the number of bus use cycles and a signal indicating the bus use form to the bus right request, the bus arbiter is notified of the used bus type and the used bus cycle number from the requester. Bus arbitration can be performed based on the request, and it is possible to predict the availability of the bus at the time of receiving the request,
A BUSACP signal corresponding to the predicted idle cycle can be sent for the next request. Thereby, the bass throughput is further improved.

The most indispensable signal for producing the above operation is a bus request signal from the storage control device, which makes it possible to divide the stages of the bus cycle and the memory cycle. The buffer is important as having the function of making the operation timing of this stage flexible.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram of an information processing apparatus according to an embodiment of the present invention. The information processing device shown in the present embodiment
A multi-processor configuration is adopted, and two instruction processing units (IP ₀ ) 10 -a, (IP ₁ ) 10 -b and two input / output processing units (IOP ₀ ) 10 -c, (IOP ₁ 10) -d, one storage control unit (SCU) 100 and one RAM (RAM) 30 are connected by an S bus 300 to form a basic processing unit (BPU) 20.

Instruction processor (IP ₀₎ 10-a and (IP ₁₎ 10-b, output processor (IOP ₀₎ 10-c and (IOP ₁₎ 10-d, and SCU100
The bus requester (request management 500) is S bus 300
When the bus right is required, the bus right request signal (BUSREQ) 12
-A to 12d, 12-r (described later) are sent to the bus arbiter 200. Here, the bus arbiter 200 is realized inside the SCU 100. The bus arbiter 200 waits for a bus vacancy, and accepts a request with the highest priority at a time corresponding to a bus vacancy cycle. The requester that has obtained the bus right sends a request (detailed information such as address, write data or read / write) using the S bus 300.

The RAM 30, which is the main memory of the BPU 20, has a 4-way interleave configuration and is addressed by continuous addresses. SCU100
Checks whether the request address is within the address implementation range of its own SCU and accepts only requests whose address range matches.

FIG. 1 shows an example of the configuration of the SCU 100. In the embodiment shown in FIG. 1, the memory access control units 700-0 to 700-3 and R
There are four AM30-0 to AM30-3, and they operate in parallel as a 4-way interleave. Way0 of SCU shown in Fig.2 and Fig.5
# 3 to # 3 indicate that accesses to the RAMs 30-0 to 30-3 are being performed in parallel. The SCU 100 in the present embodiment includes a bus arbiter 200 for arbitrating bus rights, a bus interface 400 for interfacing with the S bus 300, a request management unit 500 for synchronizing requests decomposed into four wafer interleaves, and a Queue management unit 600-0 to 600-, which is the buffer of the request (hereinafter referred to as the queue)
3, and an LSI comprising memory access control units 700-0 to 700-3 for performing memory access for each way. However, a part of each component, for example, the bus arbiter 200 may be put out of the LSI.

Prior to the detailed description of the SCU 100 in FIG. 1, the S bus and the bus grant signal will be described with reference to FIG. These interface signals are sent to the requesters 10-i (i =
a, b, c, d. The same applies to the following.)
And the bus arbiter in the SCU 100.
Requester 10-i is a bus request block (BR) 8
-I and a bus interface block (BI) 6-i.

First, the bus right receiving / receiving signal group will be described. The bus right request signals (BUSREQi-r) 12-i-r indicate the presence of the bus right request and detailed information thereof (that is, the requested bus type signal (BUSTYPi-r) 14-i-r and the requested bus use cycle). The number signal (BUSCNTi-r) 16-i-r indicates that it is valid. Request bus type signal (BUSTYPi ~
r) 14-i to r indicate that the bus request is a data bus SDB3
Indicates whether to use 20. When the data bus SDB320 is used, it is a write request, and when not used, it is a read request. Requested bus use cycle number signal (BUSCNTi to r) 16-
i to r indicate the number of use cycles of the data bus SDB320.

The bus arbiter 200 receives these bus right request signals, and according to the bus usage state and the priority of the request,
The bus right request is accepted and the bus right request acceptance signal (BUSACPi ~
r) Return 20-i to r to the requester 10-i.

When the bus right request is accepted, the request information is transferred using the S bus 300. In this embodiment, S
The mode of use of the bus 300 is classified into a memory access request transfer and a memory access result transfer. In the following description, the former is referred to as a start bus procedure, and the latter is referred to as an end bus procedure. The S bus 300 includes a start system control signal group 302 for controlling a start system bus procedure, an end system control signal group 304 for controlling an end system bus procedure, the address bus SAB310, the data bus SDB320, and the flag bus SFB322. I have. The SFB322 is auxiliary information of the data bus SDB320, and is a signal indicating which of the four bytes of the SDB320 is loaded with valid data.

The start bus procedure includes a read request transfer and a write request transfer. In the case of the read request transfer, the read address is transferred by the address bus SAB310, and at the same time, the detailed information of the request is transferred by the start control signal group 302. In the case of a write request transfer, a write address and write data are transferred by an address bus SAB310 and a data bus SDB320, and at the same time, detailed information of the request is transferred by a start system control signal group 302.

Similarly to the start system, the end system bus procedure includes read result transfer and write result transfer. In the case of the read result transfer, the read data is transferred by the data bus SDB320, and at the same time, the detailed information of the request is transferred by the end system control signal group 304. In the case of the write result transfer, only the detailed information of the request is transferred by the end system control signal group 304.

The configuration of the start system control signal group 302 includes a command signal BSACT330 indicating whether valid information is on the start system signal group, and a BS indicating whether a read request or a write request is present.
RD332, a type signal BSTYP334 indicating a normal read or write request or another bus use request, BSCNT336 indicating a data bus use cycle number, BSUNT338 identifying a request source unit, a request source request check number BSCHK340. I have. BSUNT338, BSCHK34
0 is the information accompanying the request, and when the processing is completed in the SCU,
It is transmitted on a similar signal (BEUNT, BECHK described later) in the end system control information group at the time of the end transfer, and whether or not the end notification is to the own device based on the request or BEUNT, and BECH
Based on K, it is made to recognize which of the plurality of unconfirmed requests issued by its own device is the end notification.
The bus interface 6-i of the request 10-i is
When T coincides with the number of the own device, an end notification is taken.

Next, the end-system control signal group 302 includes a command signal BEAC indicating whether or not valid information is on the end-system signal group.
T350, BERD352 to indicate read request or write request,
It is composed of BECNT 354 indicating the number of data bus use cycles, BEUNT 356 and BECHK 358 indicating request source units.

FIG. 5 shows the timing relationship between the S bus 300 and the bus grant signal described in FIG. In the case of read, in the case of write, the request is transferred to the SCU100 by the start bus procedure, and the SCU100 reads or writes to the RAM 30, and the end bus procedure sends the request result (read data, write end) to the request source. Notification etc.) is transferred and the process ends.

In the case of the read shown in FIG. 5A, in the start system bus procedure, the requester that has acquired the bus right receives a start system control signal group (shown by BSACT330) and an address (SAB310).
Is sent. In the end system bus procedure, when the processing (read) in the SCU 100 progresses to a certain point, the SCU 100 sends a bus request signal BUSREQr12-r to the bus arbiter 200 and acquires the bus right. (Shown in BEACT350) and data (SDB320).

In the case of the write shown in FIG. 5B, in the start system bus procedure, the requester sends a start system control signal group, an address (SAB310), and data (SDB320). In the end system bus procedure, the SCU 100 sends an end system control signal group.

The bus arbiter 200 shown in FIG.
= A to d, the same applies hereinafter), the bus right request signals (BUSREQi) 12-i, (BUSREQr) 12-r from the request management unit 500 and other signals (BUSTYPi, BUSTYPr, BUSCNTi, BUSCNTr) Bus arbitration is performed, and a bus request request acceptance signal (BUSACPi) 20-i,
(BUSACPr) Returns 20-r.

The bus interface 400 is an interface with the S bus 300, and accepts requests and transfers memory access results. In the request reception, the start bus procedure is received, a request reception notification signal TRUP830 is sent to the request management unit 500, and the queue management units 600-0 to 600-3 are received.
To, queue acceptance notification signal TQ (0-3) UP820-0-3,
It sends detailed information such as addresses 840-0 to 840 and data 842-0 to 842. In transferring the memory access result, the request management unit 500 sends an end bus procedure request signal BUSOUT828.
BUSOUT0 to the queue management units 600-0-3
Sends 3834-0 to 3834 and outputs information (such as fetch data)
844-0 to 3 are received. In response to this, the bus interface 400 starts an end bus procedure.

The memory access control units 700-0 to 700-3 are RAMs 30-0 to 3
A block for performing a read or write access procedure, based on the addresses 850-0 to 3 sent from the queue management units 600-0 to 3, the store data 852-0 to 3, and the control information. , The access operation is started using the ACCREQ signals 836-0 to 8-3 as start signals, and the ACCEND signal 838-0 is started.
-3 to -3 as end notification signals.
Are returned to the queue management units 600-0 to 600-3. This block is similar to the conventional memory access control system.

The queue management units 600-0 to 600-3 are connected to the bus interface 400.
Request received by the memory access control unit 700
−0 to 3, or memory access control units 700 to 0 to 3
Exists between the request processed by the server and the bus interface 400, and serves as a buffer. For this reason, the bus procedure and the memory access procedure do not always need to be processed as continuous operations fixed in time. In other words, the bus procedure and the memory access procedure can be operated as separate stages, and furthermore, a pipeline operation can be performed. As described above, SCU1
Since there are four memory access control units 700-0 to 700-3 in the 4-way interleave, there are four memory access control units 700-0 to 3, so the queue management unit 600-0 which is a buffer between the memory access control unit 700-0 and the bus interface 400 is provided.
There are also 4 to 3. The request accepted by the bus interface 400 is decomposed according to the lower two bits of the BSCNT 336 and the SAB 310, and the above four queue management units 600
It is queued to -3. Queue management unit 600-0
3 manages requests that have been decomposed into queues and queued (hereinafter simply referred to as “queues” for “request queues” of the request management unit 500).
The queue management units 600-0 to 600-3 output a TQ (0 to 3) UP signal 832-
0 to 3 as instruction signals from the bus interface 400 to the queue (specifically, addresses 840-0 to 3 and store data 8
42-0 to 3 and detailed information) and latch. The received queues are sent to the memory access controls 700-0 to 700-3 in the order of reception, and the queues received from the memory access control are sent to the fetched data 844-0 to 3-3 using the BUSOUT signals 834-0 to 834 from the bus interface 400 as instruction signals. Are sent to the bus interface 400 in the order of reception. The request accepted by the bus interface 400 is the memory access control 700-0.
If .about.3 is busy, buffering is performed in queue management 600-0.about.3, but when memory access controls 700-0.about.3 are free, transfer is performed and memory access is performed. If the bus cannot be output immediately after the access is completed, the queue management unit 600-0
The data is buffered at .about.3, but is transferred when the bus output becomes possible, and is output from the bus interface 400.

The progress status of each of the queue management units 600-0 to 600-3 described above progresses independently without synchronization with the other queue management units. Therefore, the memory access control units 700-0 to 700-3
Is busy, so that other queues can wait for processing despite the presence of subsequent queues, eliminating waste in the case of a synchronous method. And the memory throughput is improved. On the other hand, there is a problem of synchronization when the requests divided into the respective queue management units 600-0 to 600-3 are output to the bus. Request management 500 is responsible for this synchronization function. For large machines, the SCU sends the data to the IP without synchronization, and the IP side synchronizes. In the case of processors connected in a bus format to which the present invention is applied (in the case of a small-sized device), the bus interface is more effective in the method of sending synchronization within the SCU than in the method of sending it to the bus with synchronization information. It is simple, the IP is easy to control, and the control in the SCU is relatively simple. Hereinafter, this synchronization method will be described.

The synchronization of the disassembled requests that proceed independently in each of the queue management units 600-0 to 0-3 is such that, when the SCU receives the request, the request management 500 divides the request-specific identifier (token) into each of the disassembled queues. To add,
At the time when the memory access is completed, it is detected whether or not all the tokens of each of the decomposed cues are matched (matching is detected). If the tokens are matched (matching is established), the bus right is determined by the bus arbiter 200. And outputting an end notification to the S bus 300 based on the end system bus procedure. These tokens are request sequence numbers (token numbers) added to the requests received by the SCU 100 in the order of reception, and are, for example, four numbers 0 to 3. This token number moves cyclically as 0,1,2,3,0, .... The processing of each request proceeds in the order of the token number added at the time of reception, and is synchronously output to the bus. The block that manages the token number and synchronization is the request management unit 500 described above.

First, an operation of adding a token to each of the decomposed queues will be described. As mentioned above, the bus interface 400
Receives the request, the request acceptance notification signal TR
Send UP830 to the request management unit 500. In response to this, the request management unit 500 counts up the token number (TR), registers information of the received request (details will be described later) in the last tail of the request queue, and simultaneously registers the information with the queue management units 600-0 to 600-3. Send a new TR at TRNUM874.

Next, matching detection at the end of memory access and bus right request operation will be described. Request Management 500
Sends the token number (MQ) of the queue for which memory access has been completed from the queue management units 600-0 to 3 (MQNUM0 to
3) Received by 872-0 to 3 and compare it with request information and token number in request management section 500.
If the token numbers of all decomposed queues match the token numbers in the request management 500 (when matching is established), MATCH0-3 (870-0-3) is sent to the corresponding queue management units 600-0-0-3. send. Queue management 0-3 (6
00-0 to 3) receive MATCH0 to 3 (870-0 to 3) and count up the pointer indicating the matched queue. When a new matching is established (including a case where the matching has been established but there is a request waiting for bus output), the request management unit 500 sends a BUSREQr signal 12-r to the bus arbiter 200. Bus Arbiter 20
Bus interface when receiving BUSACPr signal 20-r from 0
The BUSOUR signal 828 is sent to 400. As mentioned above,
The bus interface 400 receiving this transfers the memory access result.

As described above, the request-specific token number is added to each queue, and after confirming that all of the queues have been prepared, each is output to the bus.
The memory access can be completed within 100 within synchronization.

Next, a detailed configuration example of each block of the SCU performing the operation described above will be described.

FIG. 6 is a configuration diagram of the bus arbiter 200. Bus arbiter 200 shown in this embodiment, the requester (IP ₀ 10-a shown in FIG. _{3, IP 1 10-b, IOP} 0 10-c , etc.) corresponding admission decision circuit 210-i (i = a~d , As described above), has a reception determination circuit 210-r corresponding to the request management 500. In the reception judgment circuits 210-i and 210-r, a counter latch (STAR) indicating how many cycles the start-system bus procedure, the end-system bus procedure, and the data bus SDB320 have already been used has been accepted.
Tc) 232, (ENDC) 234, and (SDBC) 236 exist, and the values are updated by the subtractors 222, 224, and 226 every cycle until the values become zero. The latches 232 and 234 set the number of use cycles of the SDB when the data bus (SDB) 320 is used, and set "1" when not used. Among these latch values, bus request signals (BUSREQi, BUSREQr, BUSTYPi, BU
Resources (each control signal S) required by STYPr, BUSCNTi, BUSCNTr)
If DB320) indicates 0 (empty), the bus enable signal RESFREEi to r250-i or 250-r is turned on.

The priority determination circuit 260 receives a plurality of bus enable signals (RESFREEi to r) 250 based on a predetermined priority.
Bus use permission signals (BUSACPi to r) 20 out of -ir
-Determine the requester to send i to r, and
Turn on r. In order to shorten the request processing time, priority is given to the end system request (request from the inside of the SCU), and thereafter, the start system request IOP0 (10-c), IOP1 (10-d), IP0 from the external requester
(10-a), IP1 (10-b). Therefore, RESFRE
When the Er signal 250-r is ON, the BUSACPr signal 20
-R turns on. Start bus enable signal (RESF
REEi) If some of the 250-i are on, the one with the highest priority will be denoted as RESFREEip. When the RESFREEr signal 250-r is off, and when the RESFREEr signal 250-r is on and both SDBs 320 are not used (more specifically, the end request is a read request and the start request is a write request). On request; this is BUSTYP
i-r signals 14-i-r are both on), B
The USACPip signal 20-ip turns on. This priority determination circuit 260 enables simultaneous reception of a start request and an end request as long as the request does not collide with the use of the SDB 320, greatly improving the throughput of the bus.

Update the counter latch STARTC232, ENDC234, SDBC236 as follows. The priority determination circuit 260 accepts (B
It is necessary to update the value of the counter latch (STARTC232, etc.) used by the request (with USACPi-r, 20i-r turned on) to the number of accepted cycles. Set counter selection circuit 270
Are the BUSACPi-r signals 20i-r and the BUSTYPi-r signals 14i-
An update instruction signal 274 is sent to the latch to be updated based on r. The selector switching signal 276 outputs the output signal from the counter set value selection circuit 272 when the latch value (the value of the signal 278) is zero, and subtracters 222, 224, and 22 when the latch value is not zero.
Indicates that output 6 is to be selected. The counter set value selection circuit 272 outputs the BUSACPi-r signals 20-i-r and the BUSTYPi
The value indicated by the BUSCNTi-r signal 16-i-r corresponding to the latch to be updated based on the -r signal 14-i-r, or "1"
Send. Sending "1" is a request not using the SDB 320, that is, a case where the BUSTYPi-r signals 14-ir are zero. As a result, the counter latches 232,234,
When a new request is accepted, the value of 236 is updated to the cycle for which use reservation is made, and the non-zero counter latch is decremented by 1 every cycle. As a result, the counter latch holds a value indicating the remaining number of cycles of use reservation.

FIG. 7 is a configuration diagram of the bus interface 400.
In the figure, BSACTB430, BSRDB432, BSTYPB434, BSCNTB43
6, BSUNTB438 is a start signal control signal latch. SABB410 is a latch of SAB310, SDBB420 is SDB320
Latch, BEACTB450, BERDB452, BECNTB454, BEUNTB456
Are the latches of the end signal control signal.

First, the reception of the start system will be described. The start system control signal is held in the latches 430, 432, 434, 436, 438,
The decoder 460 turns on the signal 461 if the BSTYPB434 is a request other than the cancel access. Also, the comparator 464
Turns on signal 465 if the address latched in SABB410 is within the address range to be handled by SCU100.
To Further, if BSACTB430 is ON, TRUP signal 830 is ON
And accept the request.

The control circuit 462 sends an address 840-0 to 3, a data 842-0 to 3, and a control signal to the queue management units 600-0 to 600-3 simultaneously with the queue acceptance notification signal TQ (0 to 3) UP832 to UP83-2. Send 841-0 to 3 This queue acceptance notification signal TQ
(0-3) UP832-0-3 are sent together with the detailed information 831 of the request to the request management section 500 together with the TRUP signal 830, and are latched.

Next, transmission of the end system will be described. Upon receiving BUSOUT828 and detailed information 829 from the request management section 500,
The control circuit 466 sends a BUSO to the queue management units 600-0 to 600-3.
Send UT0-3 (834-0-0-3). When the fetch data 844-0 to 844-3 are sent from the queue management units 600-0 to 3-3 which have received this, the control circuit 466 starts the end system bus procedure,
Switch selector 470, and end system control signal latch 450, 45
2,454,456 are controlled and bus output.

FIG. 8 is a configuration diagram of the request management unit 500. The request management unit 500 shown in the present embodiment includes a control information table 530 in which control information of a request is stored, and latches HR510 and TR512 which hold addresses of the control information table 530 management (using the token numbers). , MR514
And a matching unit 560.
The control information table 530 includes 540, 542, 544 and
It consists of 546 four registers. Adder 51
6,518,520 are used for counting up pointer information.

TR512 and HR510 are latches for holding the token numbers of the last and first requests among the requests in the request management unit 500, respectively. The MR 514 is a latch that holds the token number of the request for establishing the next matching. The control information table 530 is UNT53
0-a, CHK530-b, Way (0-3) 530-c, CNT530-d, RD530
-E five fields. Way (0-3) 5
30-c indicates which way of the queue control the request was divided into, and the queue control number (Way
The number is latched with "0" and the non-existent one is latched with "1" (the reverse of the logical meaning).

The request latch will be described. When the bus interface 400 receives the start request, the request management unit 500 is sent a TR512 count-up signal TRUP83.
Send 0. In response to this, the TR 512 counts up, and the decoder 532 indicates the position of the control information table 530 corresponding to the token number indicated by the TR 512. This decoder
The register in the control information table 530 pointed to by 532 stores control information of a new request, that is, detailed information 831 of the request, Way (0 to 3), and a queue acceptance notification signal TQ.
(0-3) UP832-0-3 are latched.

Next, the matching mechanism will be described with reference to FIG. When the processes in the memory access control units 700-0 to 700-3 are completed, the queue management units 600-0 to 600-3 transmit queue numbers MQNUM0 to MQNUM3 (872
-0 to 3) are sent. This MQNUM0-3 (872-0-0
3) The comparators 550, 552, 554, and 556 compare the value of the token number with the value of the token number of the MR 514, and output "1" if they match. This output and the Wa of the register of the control information table 530 output from the selector 572 with the number indicated by the MR 514.
The y information (530-c) is ORed by the OR circuits 580, 582, 548, 586, and the signal 562 turns ON when the processing of all the corresponding queues is completed. As a result, the Way information (530
−c) For queue management where queues exist, MATCH0 ~
Three signals (870-0 to 3) are sent, and the MR 514 counts up.

Next, a process for ending a request, that is, acquiring a bus right, sending request information to the bus interface 400, and activating an end bus procedure will be described. MR514
HR510 and M
There is a difference in the value of R514, which means that there is a request for which matching has been established but a termination notification to the bus has not been output, and the output signal BUSREQr of the comparator 522.
(12-r) turns ON. Response signal BUSACPr for this
When (20-r) is sent from the bus arbiter 200, HR5
10 is counted up, and among the information of the control information table 530 output from the selector 570 corresponding to the value of the HR 510, UNT 530-a, CHK 530-b, CNT 530-d and RD 530-e
Is synchronized with the BUSOUT signal 828 and the bus interface 400
Sent to The bus interface 400 latches them and starts an end system procedure based on the instruction of the BUSOUT signal 828.

FIG. 9 is a configuration diagram of the queue management units 600-0 to 600-3. The queue management units 600-0 to 600-3 provide information to be passed or received to the memory access control units 700-0 to 700-3 (that is,
Address 630-a, store data 630-b, control information 630-c,
A queue information table 630 holding the fetch data 630-e, a token number 600-d), and a latch HQ616, MQ614, A holding the management address of the queue information table 630.
It is composed of E612 and TQ610. The queue information table 630 has four registers, 640, 642, 644.
And 646.

TQ610 and HQ616 are latches for holding the queue numbers of the last and first queues among the queues in the queue management units 600-0 to 600-3. MR614 is a latch that holds the queue number of the queue to be established next. AR612 indicates the queue number currently being processed by the memory access control units 700-0 to 3 or the memory access control unit.
If 700-0 to 700-3 are not being processed, this is a latch holding the key number to be processed next.

First, Kyu's latch is described. When TQiUP832-i is sent from the bus interface 400, TQ610 is counted up, and the decoder 622 indicates the position of the queue information table 630 corresponding to the queue number indicated by TQ610. New key information, that is, address 840-i, store data 842-i, and control information 841-i are latched in the registers in the key information table 630 indicated by the decoder 622.

TQ610 is counted up, and a difference is generated between AQ612 and AQ612.
When CCENDi838-i is sent, control circuit 670 sends AQ61
Fetch data pointed to by the decoder 624 receiving the signal from 2
Latch data 854-0 to 3 to 630-e, then signal 672
As a result, the AQ 612 counts up and the memory access control units 700-0 to 700-3 synchronize the information 850- of the queue control table 630 selected by the selector 674 with the ACCREQi 836-i.
Send i, 852-i.

Next, the matching mechanism on the key control side will be described. According to the value of MQ614, the token number 630-d of the queue selected by the selector 676 is sent to the request control unit 500 as MQNUMi872-i. When the request control unit 500 receives MATCHi870-i indicating that the matching has been established, the value of the MQ614 is counted up and the token number of the queue to be matched next is set to the MQNUMi872-i.
Send to

Finally, the termination procedure will be described. BUSOUTi834−
Upon receiving i, the value of HQ616 is counted up. With this updated value, the end information (fetch data 630-e) of the queue information table 630 selected by the selector 678 is sent to the bus interface 400 as a data signal 844-i.

As described above, the embodiment of the present invention has been described. However, the following embodiments can be easily realized.

First, when the block target data is transferred to the bus, the transfer is performed in the first cycle, so that the IP
The number of processing wait cycles on the side can be reduced. In the bus interface 400 having received the request, information indicating the way of the generated target data is held in the request control unit as a part of the control information, and is sent to the bus interface 400 when the bus is output. In response, the bus interface 400 can be realized by controlling the target data to be sent in the first cycle.

Second, the bus interface 40 that received the request
At 0, the bus output order information of each queue is sent to the queue control units 600-0 to 600-3 as control information, and the queue control unit 600
-0 to 3 are based on this information, and the key control units 600-0 to 600-3 with the slowest bus output order are used by the MQNUM 872 according to the order.
By sending -i earlier, unnecessary matching waiting cycles can be prevented from occurring, and the average number of access cycles can be reduced.

Further, in the above embodiment, the case where the data bus width is 4 bytes and the number of ways is 4 is described as an example, but the present invention is not limited to this.
It has a memory access control unit and a queue control unit in two ways.
A two-way mode in which the request control unit establishes matching or a similar one-way mode can be easily configured at the time when the fetch of y is completed four times of 4 bytes, and the memory throughput according to the cost is hurt. Is possible.

In the above embodiment, the case where only one SCU is connected to the S bus is shown. However, in addition to the SCU 100, an additional SCU 102 incorporating a requester for requesting an end system bus right without an arbiter is used.
A configuration for connecting to a bus can be easily realized. In this embodiment, the SCU 100 and the additional SCU receive a start request from the S bus, check the address range in the bus interface block, and separate the request. Also, the end bus request from the extension SCU is sent to the SCU.
The 100 bus arbiters 200 accept the end system bus right request from inside the SCU 100 in the same manner. This additional SCU enables more flexible memory expansion.

〔The invention's effect〕

As described above, according to the present invention, in an information processing device in which a memory access request such as an IP or an IOP and an SCU are combined in a bus format and a bus arbiter transfers a bus right between the devices, the SCU Between the memory access circuit and the bus interface circuit, a buffer for waiting for a memory access between the memory access request received by the bus interface circuit and the memory access control, and transfer to the requester processed by the memory access circuit. A bus output waiting buffer is provided between the waiting memory access request and the bus interface, and when a request exists in the bus output waiting buffer, the request from the bus output waiting buffer to the bus arbiter and from the requester to the bus arbiter. It is configured to output a bus right request different from the bus right request to the bus arbiter. , In which a marked effect of realizing a memory access control method which enables to improve the memory throughput bracts of the information processing apparatus described above the SCU and the requester is coupled by a bus format.

[Brief description of the drawings]

FIG. 1 is a block diagram of an SCU of an information processing apparatus showing an embodiment of the present invention, FIG. 2 is a time chart comparing a conventional method with the method of the present invention, and FIG. FIG. 4 is an explanatory diagram of the S bus and the bus grant / receive signal, FIG. 5 is a time chart of the S bus, FIG. 6 is a block diagram of the bus arbiter shown in FIG. 1, and FIG. FIG. 8 is a block diagram of the request management unit, and FIG. 9 is a block diagram of the queue management unit. 10-a, 10-b ... Instruction processing unit (IP), 10-c, 10-d ...
… I / O processing unit (IOP), 20 …… Basic processing unit (BP
U), 30 RAM, 100 Storage controller (SCU), 200
… Bus arbiter, 300… S bus, 400… bus interface, 500… request management unit, 600-0 to 3… queue management unit, 700-0 to 3… memory access control unit

Claims (7)

(57) [Claims] 1. A memory access control method for an information processing device in which a requester device for generating a memory access request and a storage control device for processing the memory access request are connected by a bus, and a bus arbiter transfers a bus right. When the memory access is completed in the control device, the storage control device issues an end bus request signal to the bus arbiter, and the bus arbiter transfers the bus right similarly to the start bus request signal from the requester device. A memory access control method, comprising: 2. A bus output waiting buffer circuit having a bus interface circuit and a memory access circuit in the storage control device, and holding memory access completion information of a memory access request between the bus interface circuit and the memory access circuit. And when the completion information presence signal indicating that the memory access completion information is present in the bus output waiting buffer circuit is on or the access completion signal from the memory access circuit is on, the end bus request 2. The memory access control method according to claim 1, wherein a signal is turned on. 3. A memory access waiting buffer circuit for holding memory access waiting information of a memory access request is provided between the bus interface circuit and the memory access circuit, and a request acceptance signal from the bus interface circuit is turned on, or 3. The memory access request signal for the memory access circuit according to claim 2, wherein the memory access request signal for the memory access circuit is turned on when an access wait request presence signal indicating that a memory access wait request exists in the memory access wait buffer circuit is on. Memory access control method. 4. A signal indicating the number of bus use cycles is added to the start bus request signal and the end bus request signal, and based on this information, the bus arbiter predicts an end cycle of a bus use period. 2. The memory access control method according to claim 1, wherein the grant of the next bus right is controlled in advance. 5. The control system according to claim 1, wherein said bus comprises an address bus, a data bus, and a control bus, said control bus being a start system control bus used for transferring request information from said requester device to said storage control device, and said storage control device. An end control bus used to transfer memory access completion information from the requester device to the requester device, and a bus specification type signal indicating which of the bus components is to be used is the start bus request signal, Added to the end bus request signal,
5. The memory according to claim 4, wherein the bus arbiter predicts an end cycle of a bus use period of all bus components requested based on the bus specification type signal, and controls the next bus right assignment in advance. Access control method. 6. When the start system bus request signal and the end system bus request signal do not simultaneously request the use of the bus components, the start system bus request signal and the end system bus request signal are simultaneously output. 6. The memory access control method according to claim 5, wherein the method is accepted. 7. An interleave structure comprising a plurality of banks of said memory access wait buffer circuit, said memory access circuit, and said bus output wait buffer circuit, and further comprising a request specific transfer request transferred to said bus interface circuit by said start control bus. A request buffer for storing information, in the request buffer, interleaving information indicating which bank was interleaved, a request source code, etc. as request-specific information; and the bus interface circuit receives a memory access request. Then, the same token information is given to the request buffer and the memory access waiting buffer circuit in order to distinguish it from other memory access requests in the storage controller, and the token information and other request information As the process proceeds, the token information is transferred to the memory access circuit and the bus output waiting buffer circuit. When the token information arrives in the bus output waiting buffer circuit, the token information is transferred to the request buffer. A match check is performed with reference to the interleave information, and as a result of the match check, when completion synchronization is established for all interleaved bus output waiting buffer circuits, the completion information presence signal is turned on. Item 3. The memory access control method according to Item 3.