JPS6111805A - Sequence control device - Google Patents

Sequence control device

Info

Publication number
JPS6111805A
JPS6111805A JP13100884A JP13100884A JPS6111805A JP S6111805 A JPS6111805 A JP S6111805A JP 13100884 A JP13100884 A JP 13100884A JP 13100884 A JP13100884 A JP 13100884A JP S6111805 A JPS6111805 A JP S6111805A
Authority
JP
Japan
Prior art keywords
flag
data
instruction
control device
sequence control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13100884A
Other languages
Japanese (ja)
Inventor
Toshiro Kasahara
笠原 敏郎
Kosuke Okamura
光祐 岡村
Takayuki Oshiga
押賀 孝幸
Atsushi Ito
厚 伊東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13100884A priority Critical patent/JPS6111805A/en
Publication of JPS6111805A publication Critical patent/JPS6111805A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/07Programme control other than numerical control, i.e. in sequence controllers or logic controllers where the programme is defined in the fixed connection of electrical elements, e.g. potentiometers, counters, transistors

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To synchronize the transmission/reception of data easily by forming a flag storing part to be accessed from respective operation parts and determining the execution of processing of the succeeding instruction or after on the basis of the status whether the flag storing part is set or not. CONSTITUTION:In a sequence control device, operation parts 3, 4 execute the operation of data inputted from an external apparatus 8 through an input part 6 in accordance with a program stored in storage parts 1, 2 and transfers the operated result to the external apparatus 8 through an output part 7. In this case, the flag storing part 9 to be directly accessed from respective operation parts 3, 4 is formed to store an instruction for jumping its operation to a specified address if the flag is set up or executing the succeeding instruction, and if not set up, setting up the flag and executing the succeeding instruction without jump and also storing an instruction for resetting the flag. Consequently, the synchronization of the transmission/reception of data between plural programs can be guaranteed.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、複数の演算部を持ち、複数のプログラムの並
列処理を行なうシーケンス制御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a sequence control device that has a plurality of arithmetic units and processes a plurality of programs in parallel.

〔発明の背景〕[Background of the invention]

第1図に従来め並列処理方式のシーケンス制御装置の一
例を示す。8の外部機器から6の入力部を介して取り込
んだデータを基に、1と2の記憶部に格納されたプログ
ラムに従って、3と4の演算部にて演算を行なう。演算
結果は7の出力部を通じて外部機器に渡される。5は内
部出力記憶部であり一演算の途中経過等、直接外部に出
力する必要のないデータを一時格紬しておくためのもの
である。以上のような従来のシーケンス制御装置の場合
、演算部3と4はそれぞれ非同期で演算を行なうため、
相互間のデータの受は渡しの同期化がとれないという欠
卓があった。たとえば、位置決め装置の2軸制御を行な
うような場合、3の演算部が1の記憶部に格納されたプ
ログラムに従ってX軸位置座標データとY軸位置座標デ
ータを取り込んで、5の内部出力記憶部に格納し、これ
をもとに記憶部1と2の相方のプログラムで次の位・置
座標の指令等の演算を行なう。このような場合、3の演
算部がX軸データを5の内部出力に格納した時点で、4
の演算部が5の内部出力からデータを取り出して演算を
行なう可能性もある。このようなタイミングでは、X軸
のデータだけが最新データでY軸の位置座標データは旧
データ□のままとなh、これらのデータを基にして4の
演算部が演算を行なっても正しい結果は得られない。同
様に、4の演算部が5の内部出力記憶部からX軸座標デ
ータを読み出した直後に、3の演算部がX、  Y軸と
もデータを更新する可能性もある。このように従来のも
のにおいては、5の記憶部に設定されるデータの同時性
が保証できないという欠点があった。
FIG. 1 shows an example of a conventional parallel processing type sequence control device. Based on the data taken in from the external device 8 through the input unit 6, calculation units 3 and 4 perform calculations according to the programs stored in the storage units 1 and 2. The calculation result is passed to an external device through the output section 7. Reference numeral 5 denotes an internal output storage section for temporarily storing data that does not need to be directly output to the outside, such as the progress of one calculation. In the case of the conventional sequence control device as described above, since the calculation units 3 and 4 each perform calculations asynchronously,
There was a drawback in that the transfer of data between them could not be synchronized. For example, when performing two-axis control of a positioning device, the calculation unit 3 takes in X-axis position coordinate data and Y-axis position coordinate data according to the program stored in the storage unit 1, and outputs the data to the internal output storage unit 5. Based on this, the partner programs in storage units 1 and 2 perform calculations such as commands for the next position and position coordinates. In such a case, when the calculation unit 3 stores the X-axis data in the internal output of 5,
There is also a possibility that the arithmetic unit of 5 takes out data from the internal output of 5 and performs arithmetic operations. At a timing like this, only the X-axis data is the latest data, and the Y-axis position coordinate data remains the old data. Even if the calculation unit 4 performs calculations based on these data, the result will not be correct. cannot be obtained. Similarly, immediately after the calculation unit 4 reads out the X-axis coordinate data from the internal output storage unit 5, the calculation unit 3 may update the data for both the X and Y axes. As described above, the conventional device has the drawback that the simultaneity of the data set in the storage section 5 cannot be guaranteed.

また、これを防ぐため、1の記憶部のプログラムが終了
してから、再び先頭より実行するまでのサイクリック処
理の間隙を利用して、データを更新する方法もとられた
が、プログラムの長さが長(なると、デー□り更新の頻
度が少なくなシ、応答が遅くなるという欠点があった。
In order to prevent this, a method was also adopted in which the data was updated by using the gap in the cyclic processing after the program in the first storage section ended until it was executed again from the beginning. The problem was that the data was updated infrequently and the response was slow.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、複数のプログラムを並列処理する場合
、容易にデー夕の受は渡しの同期化な計れるシーケンス
制御装置を提供することKある。
An object of the present invention is to provide a sequence control device that can easily synchronize data reception and transfer when processing a plurality of programs in parallel.

〔発明の概要〕[Summary of the invention]

本発明の特徴は、各演算部よりアクセス可能なフラグ記
憶部を設け、このフラグ記憶部がセットされているかど
うかにより次の命令以下の処理を行なうかどうか決定す
るようにしたことKある。
A feature of the present invention is that a flag storage section that can be accessed by each arithmetic unit is provided, and whether or not to perform processing following the next instruction is determined depending on whether or not this flag storage section is set.

上記フラグ記憶部をチェックすることにより、受は渡し
のエリアをアクセスし°てよいかどうか判断できるため
、データの受は渡しの同期がとれる。
By checking the flag storage unit, the receiver can determine whether or not it is allowed to access the transfer area, so that data reception and transfer can be synchronized.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第2図、第3図により説明す
る。
An embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

第3図は本実施例のシーケンス制御装置の一例のブロッ
ク図である。外部機器8から入力部6を介して取り込ん
だデータを基に、記憶部1.2に格納されたプログラム
に従って、演算部3.4にて演算を行なう。演算結果は
出力部7を通じて外部機器8に渡される。5は内部出力
記憶部であJ、演算の途中経過等、直接外部に出力する
必要のないデータを一時格納しておくためのものである
FIG. 3 is a block diagram of an example of the sequence control device of this embodiment. Based on the data taken in from the external device 8 via the input unit 6, the calculation unit 3.4 performs calculations according to the program stored in the storage unit 1.2. The calculation result is passed to the external device 8 through the output section 7. Reference numeral 5 denotes an internal output storage section J, which is used to temporarily store data that does not need to be directly output to the outside, such as intermediate progress of calculations.

本実施例の特徴は各演算部3.4から直接アクセス可能
なフラグ記憶部9を設け、このフラグがセットされてい
れば指定した場所にジャンプし、リセットされていれば
フラグをセットしてジャンプせず、次の命令から実行し
ていく命令(仮KIRI81!1RVE命令と呼ぶ)を
有し、かつ、このフラグをリセットする命令(以後IF
RIK命令と呼ぶ)を有することKある。
The feature of this embodiment is that it is provided with a flag storage section 9 that can be accessed directly from each calculation section 3.4, and if this flag is set, it jumps to the specified location, and if it is reset, it sets the flag and jumps. First, it has an instruction to be executed from the next instruction (temporary KIRI81!1RVE instruction), and an instruction to reset this flag (hereinafter referred to as IF
(referred to as the RIK instruction).

データの受は渡しの同時性を保つためには、第3図(a
)の如く、データを内部出力記憶部5にセットするプロ
グラム10の前にR’1.BnRVR命令を入れる。こ
の命令を実行する処理手段3.4はまずフラグをチェッ
クし、これがセットされていなければ、セットして他の
演算部忙対してデータを更新中であることを知らしめる
。そして、プログラム10の終了後、’PRF!Fi命
令によシフラグ記憶部9をリセットする。この時のプロ
グラムの実行順序を第3図(b)に示す。実線がプログ
ラムの実行、破線はジャンプを示す。この例は、シルケ
ンスプログラムなので、サイクリック処理が行なわれて
いる。一方、RE8KRVB命令が実行された時−7ラ
グ記憶部9がセットされていると、演算部3.4は、次
の命令に移らずにRBBRRVB以降に示されたジャン
プ先忙ジャンプする。
In order to maintain the simultaneity of receiving and passing data, it is necessary to
), before the program 10 that sets data in the internal output storage section 5, R'1. Insert the BnRVR command. The processing means 3.4 which executes this instruction first checks the flag and, if it is not set, sets it to indicate that other arithmetic units are busy updating data. After Program 10 ends, 'PRF! The shift flag storage unit 9 is reset by the Fi instruction. The execution order of the program at this time is shown in FIG. 3(b). Solid lines indicate program execution, and dashed lines indicate jumps. This example is a Silkens program, so cyclic processing is performed. On the other hand, if the -7 lag storage section 9 is set when the RE8KRVB instruction is executed, the arithmetic section 3.4 jumps to the jump destination indicated after RBBRRVB without proceeding to the next instruction.

この時の実行順序を示したのが、第3図(c)である。FIG. 3(c) shows the execution order at this time.

以上ノI’tlli81RVK、F’R,BB命令によ
り、受は渡しデータの更新中には必ず9のフラグがセッ
トされている状襲となり、他の演算部は、このデータを
アクセスできないから、データがすべて更新されPRE
K命令が実行された後に読み込むことに起り、読み込む
データの同時性が確保できる。
Due to the above I'tlli81RVK, F'R, and BB instructions, the receive will always have the flag 9 set while updating the passing data, and other arithmetic units cannot access this data, so the data are all updated PRE
This occurs because the data is read after the K instruction is executed, and the simultaneity of the data to be read can be ensured.

〔発明の効果〕〔Effect of the invention〕

以上のようK、本発明によれば、応答速度を犠牲にする
ことなしに、複数のプログラム間で、データの受は渡し
の同時性を保証することが可能なシーケンス制御装置を
得ることができる。
As described above, according to the present invention, it is possible to obtain a sequence control device that can guarantee the simultaneity of receiving and passing data between multiple programs without sacrificing response speed. .

【図面の簡単な説明】[Brief explanation of drawings]

第1因は、従来の並列処理型シーケンス制御装置の一例
を示すプルツク図−第、2図は本発明の−実施例を示す
シーケンス制御装置のブロック図、第3図は本実施例に
よるプログラム実行順序を示す図である。 1.2・・・プログラム記憶部、3.4・・・演算部、
5・・・内部出力記憶−,6・・・入力部、7・・・出
力部、8・・・外部機器、9・・・フラグ記憶部、10
・・・データ受は渡しプログラム 代理人  弁理士 高  橋  明  夫$ 1 目
The first cause is a Plutz diagram showing an example of a conventional parallel processing type sequence control device, and FIG. 2 is a block diagram of a sequence control device showing an embodiment of the present invention, and FIG. 3 is a block diagram of a sequence control device showing an embodiment of the present invention. It is a figure which shows an order. 1.2...Program storage unit, 3.4...Arithmetic unit,
5... Internal output memory, 6... Input section, 7... Output section, 8... External device, 9... Flag storage section, 10
...Data is delivered to you Program agent Patent attorney Akio Takahashi $ 1

Claims (1)

【特許請求の範囲】[Claims] 複数のプログラムを格納する記憶部と、外部機器より信
号を取り込む入力部と、入力部より取り込んだデータを
基に前記記憶部から読み出した複数のプログラムに従つ
て演算を行なう複数の演算部を有する制御部と、前記演
算結果を外部機器に伝える出力部とを具備して成るシー
ケンス制御装置において、前記演算部からアクセス可能
なフラグ記憶部を設け、このフラグ記憶部がセツトされ
ているか否かにより、次の命令以下の処理を行なうか否
かを決定する処理手段を有することを特徴とする、シー
ケンス制御装置。
It has a storage part that stores a plurality of programs, an input part that takes in signals from an external device, and a plurality of calculation parts that perform calculations according to the plurality of programs read from the storage part based on the data taken in from the input part. In a sequence control device comprising a control section and an output section for transmitting the calculation result to an external device, a flag storage section accessible from the calculation section is provided, and a flag storage section is set. , a sequence control device comprising processing means for determining whether or not to perform processing subsequent to the next command.
JP13100884A 1984-06-27 1984-06-27 Sequence control device Pending JPS6111805A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13100884A JPS6111805A (en) 1984-06-27 1984-06-27 Sequence control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13100884A JPS6111805A (en) 1984-06-27 1984-06-27 Sequence control device

Publications (1)

Publication Number Publication Date
JPS6111805A true JPS6111805A (en) 1986-01-20

Family

ID=15047808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13100884A Pending JPS6111805A (en) 1984-06-27 1984-06-27 Sequence control device

Country Status (1)

Country Link
JP (1) JPS6111805A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5617401A (en) * 1979-07-23 1981-02-19 Omron Tateisi Electronics Co Sequence controller
JPS5789104A (en) * 1980-11-21 1982-06-03 Toyota Motor Corp Control method of parallel processing type programmable controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5617401A (en) * 1979-07-23 1981-02-19 Omron Tateisi Electronics Co Sequence controller
JPS5789104A (en) * 1980-11-21 1982-06-03 Toyota Motor Corp Control method of parallel processing type programmable controller

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