JPS61117627A - Diagnostic circuit of logic circuit - Google Patents

Abstract

PURPOSE:To improve the diagnosis rate by dividing an FF group in a logic circuit into FFs, which can be entered in a scan loop, and FFs, which cannot be entered there, in accordance with diagnostic environments and making them operable to diagnose a maximum range of the logic circuit. CONSTITUTION:When a logic circuit board is diagnosed as a single substance, a test mode signal 10 is set to '1', and scan out data 14 from the scan loop where both scan loops of logic blocks 1 and 2 are coupled is selected by a multiplexer 3. At this time, a shift pulse 6 is supplied to both of logic blocks 1 and 2 because an AND circuit 19 functions. Consequently, scan in data 7 can be inputted to scan loops of logic blocks 1 and 2 successively, and scan out data 17 is read out from the multiplexer 3. This data 17 is used to diagnose logic blocks 1 and 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a shift type diagnostic circuit that is incorporated in advance into a logic circuit board or an IC in order to test a logic circuit. The present invention relates to a diagnostic circuit that diagnoses a logic circuit in which registers and counters that require input are added to the scan loop.

[Conventional technology]

2. Description of the Related Art In recent years, as information processing devices and various control devices have become larger and have higher performance, a large number of complex and large-scale logic circuits are being used.

On the other hand, due to advances in LSI technology and packaging technology, the circuit packaging density of logic circuit boards has improved significantly, making testing of logic circuit boards extremely difficult and time-consuming.

Generally, when testing or diagnosing a logic circuit board, test data is given and the presence or absence of a fault is determined from the logic output results. The drawback is that it is not possible to know the detailed internal state of the system. One solution to this problem is to use flip-flops inside the circuit to directly set test data and to read out the internal state of the circuit to the outside.A shift register mechanism is built into the logic circuit in advance. A diagnostic method called the "shift shift method" is often used.

This shift method uses flip-flops FF, FF in the logic circuit 21 as shown in FIG.

. . . FF, . . . FF, are connected in series to create a scan loop with a soft register configuration.
During analysis, a shift pulse is applied from the outside to shift the test data string, that is, scan-in data, into the scan loop (called scan-in), and then the data is set in each flip-flop FF, FF, etc. A logical operation is executed based on the test data, and once the results are set in each flip-flop, they are shifted and output to the outside as scan-out data (referred to as scan-out). By the way, each flip-flop in the scan loop is (,
51'l: It includes a circuit and a control circuit for soft register operation, and only the shift pulse is inputted while the shift pulse and the clock for the original Frino Zoflo knob operation are stopped.

[Problem that the invention seeks to solve]

Conventionally, in diagnosing logic circuits using the shift method, there have been cases in which the diagnosis was performed on the board alone and cases in which the diagnosis was performed with the board mounted. In the latter case, if the output of a logic circuit on one board is essential for the operation of a circuit on another board, the clock of that logic circuit will be stopped. In that case, it was necessary to exclude that logic circuit from the scan loop.

For example, if a refresh counter for generating a memory refresh address is placed on one board, and a memory that uses that refresh address is placed on another board, the count to the refresh counter will be cannot stop the clock.

Therefore, even if it is possible to stop the count clock supply to the refresh counter when diagnosing the board alone, as long as there is a possibility of performing the diagnosis while the board is mounted, each flip-flop that makes up the refresh counter can no longer be included in the scan loop,
This was a major reason why it was not possible to increase the proportion of the diagnosable range in the logic circuit, that is, the diagnostic rate.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention has been developed in such a way that the clock supply to the logic circuit may be stopped depending on the conditions in which the diagnosis is performed, that is, the diagnosis environment, such as diagnosis of the board alone and diagnosis of the board mounted on the device. Flip-flow logic circuit that changes whether it is possible or not.

As for the logic circuit, it is possible to select whether to include or exclude it from the scan loop4, and its configuration is to diagnose the logic circuit based on the diagnostics of the logic circuit that performs shift scan-in and scan-out. A first scan loop connects a group of flip-flops whose clock supply cannot sometimes be stopped even during operation, and a second scan loop which connects a group of flip-flops whose clock supply can be stopped during diagnostic operation regardless of the diagnostic environment described above. The first loop and the second loop are provided separately.
The present invention is characterized in that it includes means for switching between one scan loop in which two scan loops are connected and a second independent scan loop using an external control signal.

〔Example〕

The details of the present invention will be explained below based on examples.

FIG. 1 shows the configuration of one embodiment of a logic circuit board equipped with a diagnostic circuit according to the present invention.

In the figure, l is a logic block that can stop the clock regardless of the diagnostic environment, 2 is a logic block that cannot stop the clock depending on the diagnostic environment, 3 is a multiplexer for scan-out data switching, and 4 is the clock of logic block 1, 5 is the manual data of logic block I, 6 is the noft pulse, 7 is the scan-in data,
8 is a count ronc, 9 is a reset signal, 10 is a test mode signal, 11 is a shift pulse of logic block 2, 12.13.18 is scan out data of logic block 1, 14 is logic block l and 8 remainder Scan-out data of frontk 2, 15 is output data of logic block 1, 16 is output data of logic block 2, 17 is scan-out data, 19 is AND circuit, 20.21
is a buffer.

In addition, 1a, ■b, 1c shown in logical block 1,
2a, 2b, and 2c shown in the logic block 2 are all flip-flops that have a predetermined role in each logic block, and in particular, 2a, 2b, and 2c constitute each stage of the refresh counter. . These flip-flops also serve as stages of a shift register that constitutes a scan loop. Terminals Si, So, and Sc in each flip-flop are terminals provided to function as a shift register, where Si is a shift data input terminal, SO is a shift data output terminal,
Sc represents a shift pulse input terminal.

A scan loop consisting of flip-flops la, 1b and IC of logic block 1 is connected to flip-flop 2a of logic block 2 via buffer 2o.

2b and 2c, and is further connected to one input terminal of the multiplexer 3, and the scan loop of the logic block l is connected alone to the other one input terminal of the multiplexer 3 via the buffer 21. .

Therefore, by controlling multiplexer 3,
It is possible to select either one long scan loop in which the scan loops in two blocks, logic block 1 and logic block 2, are connected vertically, or only the scan loop in logic block 1.

Next, a specific diagnosis operation will be explained.

For example, when diagnosing the illustrated logic circuit board alone, the refresh counter function of the logic block 2 may be temporarily stopped, so the test mode signal 10 is set to "1".
'' to cause multiplexer 3 to select scan-out data 14 from a scan loop that combines the scan loops of both logic block 1 and logic block 2.

At this time, since the AND circuit 19 is functionalized, the shift pulse 6 is supplied to both the logic block 1 and the logic block 2. As a result, the scan-in data 7 is transferred to the scan loop of the logic block l and the logic block 2. The scan loop can be manually operated one after another, and the scan-out data 17 can be read out from the multiplexer 3.

Using this scanout data 17, logical block 1 is
Logic block 2 is then diagnosed.

Next, when each logic circuit board is mounted on a device and a device test is performed, logic block 2 must be removed from the target. In this case, set the test mote signal 10 to “0”.
”. This causes the multiplexer 3 to output the skimmed-out data 13 from the scan loop of the logical block l.
9, and the AND circuit 1 is disabled, thereby blocking the supply of the shift pulse to the logic block 2.9 Therefore, the shift pulse 6 is supplied only to the logic block I, and the scan-in Data 7 is manually outputted and scanout data 13 is outputted to multiplexer 3.
The scan-out data 17 is read out from the scan-out data 17. Logic block 1 is tested using this scan-out data 17. During this period, the counting ROFF signal 8 or the reset signal 9 is applied to the logic block 2, which operates as a refresh counter and sends out the refresh address as output data 16.

〔Effect of the invention〕

As described above, according to the present invention, the flip-flops in the logic circuit are divided into those that can be put into the scan loop and those that cannot be put into the scan loop depending on the diagnostic environment, and by enabling the respective operations, the flip-flops are always in the diagnostic environment. Diagnosis can be performed on the maximum range of logic circuits corresponding to the requirements, and the diagnostic rate can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is an explanatory diagram of a diagnostic circuit using a shift method. In the figure, 1 is a logic block that can always stop the clock, 2
3 is a multiplexer, 4 is a clock, 5 is manual data, 6 is a shift pulse, 7 is scan-in data, 8 is a counting clock, and 9 is a logic processor whose clock cannot be stopped depending on the conditions of the diagnostic environment. Reset signal, 10
is the test mode signal, 12.13.14.17.18 is the scan out data, 15.16 is the output data, 19
represents an AND circuit, and 20.21 represents a buffer.

Claims (1)

[Claims] In a logic circuit that performs shift scan-in and scan-out, there is a first scan loop connecting a group of flip-flops in which clock supply may not be stopped even during diagnostic operation depending on the diagnostic environment of the logic circuit; and a second scan loop connected to a group of flip-flops that can stop clock supply during diagnostic operation regardless of the diagnosis operation, and one scan loop connecting the first scan loop and the second scan loop. 1. A diagnostic circuit for a logic circuit, comprising means for switching between the first scan loop and the second independent scan loop using an external control signal.