JPS61115339A - Eprom device - Google Patents
Eprom deviceInfo
- Publication number
- JPS61115339A JPS61115339A JP59236588A JP23658884A JPS61115339A JP S61115339 A JPS61115339 A JP S61115339A JP 59236588 A JP59236588 A JP 59236588A JP 23658884 A JP23658884 A JP 23658884A JP S61115339 A JPS61115339 A JP S61115339A
- Authority
- JP
- Japan
- Prior art keywords
- ultraviolet
- resin
- chip
- eprom
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/18—Circuits for erasing optically
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Read Only Memory (AREA)
- Non-Volatile Memory (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分ＩＦ）
この発明は、紫外線消去形プ胃グラマプル・リード・オ
ンリ・メモリ装置であるＥＰＲＯＭ装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application IF) This invention relates to an EPROM device which is an ultraviolet erasable programmable read only memory device.
（従来の技術）
従来のサーディツプパッケージ構造のＥＰＲＯＭ装置の
外観斜視図を第２図に示し、その図のｌ−ｌｌ１断面図
を第３図に示す。また、第３図の部分拡大図を第４図に
示す。これらの図に示すように、サーディツプパッケー
ジ構造のＥＰＲＯＭ装置は、サーディツプヘッダ（以下
単にヘッダという）１とサーディツプキャップ（以下単
にキャップという）２を有する。ヘッダ１は、アルミナ
（Ａ ｊ 、 ０．）からなる基材３に外部導出端子４
が低融点ガラス５で接着されている。また、ヘッダ１は
、ガラスに金粉を多量に混入した所謂金ペーストを焼結
した素子搭載部６が前記基材３の中央部上に設けられて
いる。そして、この素子搭載部６にＥＰＲＯＭチップ７
が紫外線照射面を上にしてダイボンディングされ、この
チップ７の電極パッドと前記外部導出端子４とが金属細
線（アルミニウム）８によって接続されている。また、
第４図に示すように、素子搭載部６上には、頭部にアル
ミニウム９を蒸着したシリコン小片からなるグランドダ
イス１０がグイポンディングされ、このグランドダイス
１Ｇには前記頭部のアルミニウム９に、ＥＰＲＯＭチッ
プ７の電極パッドのうち接地電極パッド１１が金属線Ｍ
（アルミニウム）８ａにより接続される。(Prior Art) FIG. 2 shows an external perspective view of an EPROM device with a conventional cerdip package structure, and FIG. 3 shows a sectional view taken along line 1-11 of that figure. Further, a partially enlarged view of FIG. 3 is shown in FIG. 4. As shown in these figures, the EPROM device having a surdip package structure has a surdip header (hereinafter simply referred to as a header) 1 and a surdip cap (hereinafter simply referred to as a cap) 2. The header 1 has an external lead terminal 4 on a base material 3 made of alumina (A j , 0.).
are bonded with low melting point glass 5. Further, the header 1 is provided with an element mounting portion 6 on the center portion of the base material 3, which is made of sintered so-called gold paste, which is glass mixed with a large amount of gold powder. Then, an EPROM chip 7 is mounted on this element mounting portion 6.
is die-bonded with the ultraviolet irradiation surface facing upward, and the electrode pads of this chip 7 and the external lead-out terminals 4 are connected by thin metal wires (aluminum) 8. Also,
As shown in FIG. 4, a ground die 10 made of a small piece of silicon with aluminum 9 deposited on its head is mounted on the element mounting portion 6, and this ground die 1G is bonded to the aluminum 9 on the head. , the ground electrode pad 11 of the electrode pads of the EPROM chip 7 is connected to the metal wire M
(Aluminum) Connected by 8a.
一方、キャップ２は蓋部材であって、前記ＥＰＲＯＭチ
ップ７の紫外線照射面と対向するように窓１２を設けた
アルミナからなる基材１３を有し、この基材１３の下面
周辺部に低融点ガラス１４が塗られている。そして、こ
のキャップ２は、前記ヘッダ１上に被せられた後、４８
０’ｅ程度に加熱されることによって低融点ガラス１４
がヘッダ１の低融点ガラス５と溶融一体となることによ
り、ＥＦＲＯＭチップ？上を気密封止している。On the other hand, the cap 2 is a lid member, and has a base material 13 made of alumina and provided with a window 12 so as to face the ultraviolet irradiation surface of the EPROM chip 7. Glass 14 is painted. After this cap 2 is placed on the header 1, the cap 2 is
The low melting point glass 14 is heated to about 0'e.
By melting and integrating with the low melting point glass 5 of the header 1, the EFROM chip? The top is hermetically sealed.
（発明が解決しようとする問題点）
しかるに、このようなサーディツプパッケージ構造のＥ
ＦＲＯＭＩ置では、次のような欠点があった。(Problem to be solved by the invention) However, the E
The FROMI system had the following drawbacks.
（１１Ｅ Ｐ ＲＯＭチップ７の接地電極パッド１１を
素子搭載部６に配線することにより、接地電極パッド１
１とＥＰＲＯＭチップ７の基板とを電気的に接続するわ
けであるが、そのための金属線４１１８ｍを直接素子搭
載部６に接続することができず、グランドダイス１０を
介在させなければならない。すなわち、上述したサーデ
ィツプパッケージ構造のＥＰＲＯＭ装置では、低融点ガ
ラス５と１４を溶融させて封止を行うため、レール温度
が４８０℃程度と高温である。また、金ペーストと呼ば
れるガラスに金が混入したものを焼結して素子搭載部６
を形成しているため、アルミニウム線または金線からな
る金属細線を直接素子搭載部６に接続すると、前記シー
ル温度（４８０℃程度の高温）で、ガラス中に含まれる
船あるいはその他の物質と前記金とでアロイ化が進み配
線抵抗が高くなるという問題が生しる。したがって、従
来のサーディツプパッケージ構造のＥＰＲＯＭ装置では
、シリコン小片からなるグランドダイス１０を素子搭載
部６に接着し、その頭部の蒸着アルミニウム９に金属
）細１１１８ｍを接続して上記の問題点を回
避しているが、これが極めてわずられしい作業である。(By wiring the ground electrode pad 11 of the 11E P ROM chip 7 to the element mounting section 6, the ground electrode pad 1
1 and the substrate of the EPROM chip 7, the metal wire 4118m for this purpose cannot be directly connected to the element mounting portion 6, and a grounding die 10 must be interposed. That is, in the above-mentioned EPROM device having the cerdip package structure, the low melting point glasses 5 and 14 are melted for sealing, so the rail temperature is as high as about 480°C. In addition, a material called gold paste, in which gold is mixed into glass, is sintered to form the element mounting area 6.
Therefore, if a thin metal wire made of aluminum wire or gold wire is directly connected to the element mounting part 6, the sealing temperature (high temperature of about 480°C) will cause the ship or other substance contained in the glass to separate from the above. The problem arises that alloying with gold progresses and wiring resistance increases. Therefore, in the conventional EPROM device with a cerdip package structure, a ground die 10 made of a small piece of silicon is glued to the element mounting part 6, and a metal is attached to the vapor-deposited aluminum 9 on the head of the ground die 10.
) The above problem is avoided by connecting 1118 m of thin wire, but this is an extremely troublesome work.
（２）上述のようにシール温度が高い結果、金属線＄ｌ
ｉ８，８ａ（現在アルミニウム線）として金線を用いた
場合、ＥＰＲＯＭチップ７表面の電極パッドのアルミニ
ウムと金線との間でやはり二元合金が形成されて配線抵
抗が高くなるので、高速ワイヤボンドが可能な金線を金
属細線８゜８ａとして用いることができず、組立時間が
長くかかる。(2) As a result of the high sealing temperature as mentioned above, the metal wire $l
If a gold wire is used as the i8,8a (currently an aluminum wire), a binary alloy is formed between the aluminum of the electrode pad on the surface of the EPROM chip 7 and the gold wire, increasing the wiring resistance. It is not possible to use a gold wire that can be used as the thin metal wire 8° 8a, and it takes a long time to assemble it.
（３）衝撃に弱く、シばしば基材３，１３などのパッケ
ージが欠けたりする。(3) It is weak against impact, and packages such as the base materials 3 and 13 are often chipped.
（４）装置の重量が重いため、プリント基板への搭載数
が制限される。(4) Since the device is heavy, the number of devices that can be mounted on a printed circuit board is limited.
（問題点を解決するための手段）
そこで、この発明では、リードフレーム上にＥＰＲＯＭ
チップを搭載する乙とｉζ加えて、そのチップ上に紫外
線透過性樹脂を盛ること、およびその樹脂上に平板状の
紫外線透過性窓部材を取着することにより、ｍ脂封止型
のＥＰＲＯＭ装置を実現可能とする。(Means for solving the problem) Therefore, in this invention, an EPROM is mounted on a lead frame.
In addition to mounting the chip, by placing an ultraviolet-transparent resin on the chip and attaching a flat ultraviolet-transparent window member to the resin, a resin-sealed EPROM device can be created. is made possible.
（作 用）
樹脂封止型のＥＰＲＯＭ装置によれば、樹脂による封止
であるから、シール温度は低くなる。さらに、軽量とな
り、衝撃に対しても強い。(Function) According to the resin-sealed EPROM device, the sealing temperature is low because the resin is used for sealing. Furthermore, it is lightweight and strong against impact.
（実施例）
以下この発明の一実施例を図面を参照して説明する。第
１図はこの発明の一実施例の装置の断面図である。この
図において、２１は金属板をエツチングあるいは打ｖｉ
、き加工して形成されたリードフレームで、前記加工後
金メッキあるいは銀メッキが施された素子搭載部２２、
およびこの素子搭載部２２側の端であるポスト部に同じ
（加工後金メッキあるいは銀メッキが施された複数の外
部導出端子２３を有する。このリードフレーム２１の素
子搭載部２２上には、ＡｇペーストなどによってＥＰＲ
ＯＭチップ２４がダイボンディングされる。(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an apparatus according to an embodiment of the present invention. In this figure, 21 is a metal plate etched or stamped.
, an element mounting portion 22 which is a lead frame formed by processing and is plated with gold or silver after the processing;
The post part, which is the end on the side of the element mounting part 22, has a plurality of external lead-out terminals 23 which are plated with gold or silver after processing. EPR by etc.
The OM chip 24 is die-bonded.
そして、そのＥＰＲＯＭチップ２４は、表面の電極パッ
ドが前記外部導出端子２３のポスト部に金などの金属線
＠２５によって配線される。また、図示しないが、ＥＰ
ＲＯＭチップ２４の電極パツドのうち接地電極パッドは
、同じく金などからなる金属細線によって素子搭載部２
２に配線される。The electrode pads on the surface of the EPROM chip 24 are wired to the post portions of the external lead terminals 23 using metal wires such as gold wire @25. Also, although not shown, EP
Among the electrode pads of the ROM chip 24, the ground electrode pad is connected to the element mounting portion 2 by a thin metal wire made of gold or the like.
Wired to 2.
その場合、金属細線は、金メッキあるいは銀メッキが施
された素子搭載部２２に直接接続される。In that case, the thin metal wire is directly connected to the element mounting portion 22 which is plated with gold or silver.
このようにして配線が行われたＥＰＲＯＭチップ２４上
には紫外線透過性樹脂２６が盛られろ。この紫外線透過
性樹脂２６は、後述する紫外線透過性窓部材が有害な外
部雰囲気（機械的応力なども含む）からＥＰＲＯＭチッ
プ２４を保護するから、最低の条件として紫外線透過性
を有するものであればよく、例えばシリコン樹脂（東し
ＪＣＲ−６１２７など）でよい。このような紫外＊ａ過
性樹脂２６上には、前記ＥＰＲＯＭチップ２４の表面（
紫外線照射面）と平行に平板状の紫外線透過性窓部材２
７が取着される。この紫外線透過性窓部材２７は、いう
までもなく紫外線透過性の材料で形成されるものであり
、具体的にはアルミナ。An ultraviolet-transparent resin 26 is placed on the EPROM chip 24 wired in this way. This ultraviolet-transparent resin 26 should be ultraviolet-transparent as a minimum condition, since the ultraviolet-transparent window member described later protects the EPROM chip 24 from a harmful external atmosphere (including mechanical stress, etc.). For example, silicone resin (Toshi JCR-6127, etc.) may be used. The surface of the EPROM chip 24 (
A flat ultraviolet-transparent window member 2 parallel to the ultraviolet irradiation surface)
7 is attached. Needless to say, the ultraviolet-transparent window member 27 is made of an ultraviolet-transparent material, specifically alumina.
石英、アクリル系樹脂などにより作られる。そして、こ
の紫外線透過性窓部材２７および前記リードフレーム２
１などからなる以上の構造体は、リードフレーム２１の
外部導出端子２３の外部導出部（ボスト部側の一部範囲
を除く部分）を除いて、かつ紫外線透過性窓部材２７の
表面を上面に露出させて絶縁性樹脂２８で包囲される。Made from quartz, acrylic resin, etc. This ultraviolet-transparent window member 27 and the lead frame 2
1, etc., except for the external lead-out portion of the external lead-out terminal 23 of the lead frame 21 (excluding a part of the area on the boss side), and with the surface of the ultraviolet-transparent window member 27 facing upward. It is exposed and surrounded by an insulating resin 28.
この絶縁性＠［１２８としては熱硬化性のエポキシ系樹
脂、特にフイラを含有した半導体成形用樹脂がアルミナ
あるいは石英またはガラスと強い密着性を呈するので好
ましい。As the insulating property @[128, a thermosetting epoxy resin, particularly a filler-containing resin for semiconductor molding, is preferable because it exhibits strong adhesion to alumina, quartz, or glass.
以上のようなＥＦＲＯＭｌ＋置は次のようにして製造さ
れる。まず、リードフレーム２１に対するＥＰＲＯＭチ
ップ２４の搭載および配線を行っておく。一方、第５図
に示すように上向きコ字形の治具２９を用意し、その底
部に平板状の紫外線透過性窓部材２７をセットし、その
窓部材２７上にボッティングによって紫外線透過性４Ｉ
ＩＩＩＩ２６を滴下する。そして、その紫外線通過性物
１１２６が硬化しないうちに、前記ＥＰＲＯＭチップ２
４が搭載されたリードフレーム２１を上下反転させて前
記第５図に示すようにＥＰＲＯＭチップ２４を前記紫外
線透過性樹＠２Ｇに押し当てるようにしてリードフレー
ム２１を治具２９上に保持する。しかる後、その状態で
ｉｓｏ℃で１時間程度加熱し、前記紫外線透過性樹Ｗａ
２Ｂを硬化させる。これにより、リードフレーム２１．
ＥＰＲＯＭチップ２４、紫外線透過性樹脂２６および紫
外線透過性窓部材２７からなる一体構造が完成する。こ
の時、ＥＰＲＯＭチップ２４の表面と紫外線透過性窓部
材２７とが平行になっていなければならない。もし、平
行になっていないと、上記一体構造体をモールディング
金型にセットした時に、モールディング金型と前記窓部
材２７との間に間隙ができて、封止樹脂（絶縁性樹脂）
を加圧注入した時に、封止樹脂の薄い膜（モールディン
グフラッシュ）が窓部材２７の表面上にできてしまい、
前記窓部材２７の紫外線透過性が低下し、また外観上も
よくなくなる。しかし、上記製造方法によれば、前記治
具２９を用いろことにより、平行具合を高精度に保つこ
とができる。しかる後、上記一体構造体を治具２９から
外す一方、トランスファーモールディング金型にセット
し、その金型内に絶縁性樹ｍ＜封止側１を加圧注入・射
出成形することにより絶縁性樹脂からなる包囲体（第１
図の絶縁性樹脂２８）を形成する。The EFROM1+ device as described above is manufactured as follows. First, the EPROM chip 24 is mounted on the lead frame 21 and wired. On the other hand, as shown in FIG. 5, an upward U-shaped jig 29 is prepared, a flat ultraviolet-transparent window member 27 is set at the bottom of the jig 29, and an ultraviolet-transparent 4I
Drop III26. Then, before the ultraviolet-transmissive material 1126 is cured, the EPROM chip 2
The lead frame 21 on which the lead frame 4 is mounted is turned upside down and the lead frame 21 is held on the jig 29 so that the EPROM chip 24 is pressed against the ultraviolet transparent tree @2G as shown in FIG. Thereafter, the ultraviolet-transparent tree Wa is heated in that state for about 1 hour at iso°C.
2B is cured. As a result, the lead frame 21.
An integrated structure consisting of the EPROM chip 24, the ultraviolet-transparent resin 26, and the ultraviolet-transparent window member 27 is completed. At this time, the surface of the EPROM chip 24 and the ultraviolet transparent window member 27 must be parallel to each other. If they are not parallel, when the integral structure is set in a molding die, a gap will be created between the molding die and the window member 27, and the sealing resin (insulating resin)
When injected under pressure, a thin film of sealing resin (molding flash) was formed on the surface of the window member 27,
The ultraviolet transmittance of the window member 27 decreases, and the appearance also deteriorates. However, according to the above manufacturing method, by using the jig 29, the parallelism can be maintained with high precision. Thereafter, the integrated structure is removed from the jig 29, and set in a transfer molding mold, and the insulating resin m<sealing side 1 is injected and injection molded into the mold under pressure. An enclosing body (first
Insulating resin 28) shown in the figure is formed.
（発明の効果）
以上説明したように、この発明によれば、リードフレー
ム上にＦ、ＦＲＯＭチップを搭載することに加えて、そ
のチップ上に紫外線透過性樹脂を盛ること、およびその
樹脂上に平板状の紫外線透過性窓部材を取着することに
より、４！ｌｌｌ１封止型のＥＰＲＯＭ装置を実現でき
る。そして、樹脂封止型のＥＰＲＯＭ装置によれば、樹
脂（絶縁性側１による封止（包囲）であるためシール温
度は低くなり、その結果ア田イ化を防止できるので、金
属細線を直接素子搭載部に接続して作業および構造の簡
素化を図ることができるとともに、金属細線として金線
を使用して高速ワイヤボンドを実現でき作業時間を短か
くできる。さらに、シール温度が低（なれば、ＥＰＲＯ
Ｍチップに与える熱ストレスも軽減できる。また、樹脂
封止のＥＰＲＯＭ装置によれば、サーディツプ型あるい
はセラミツり型のパッケージで構成された従来のＥＰＲ
ＯＭ装置に比べて圧倒的に軽量であるためプリント基板
への実装数の制限を緩和でき、さらに熱硬化性の硬い樹
脂で構成されているためサーディツプ型のパフケージの
ように欠けたしすることがなく、しかも安価となる。ま
た、この発明のＥＰＲＯＭ装置においては紫外線透過性
樹脂を用いているが、とのｍ脂は製造時、平板状の紫外
線通過性窓部材上にボッティングによって滴下するだけ
でよく、中空有底キャップ内に狭い充填孔より充填する
などの作業が不要で樹脂の注入が容易であるから、＊＊
内に気泡混入などのｌ［［を生じない。すなわち、高性
能なＥＰＲＯＭ装置を歩留りよく得られる。□(Effects of the Invention) As explained above, according to the present invention, in addition to mounting an F and FROM chip on a lead frame, an ultraviolet-transparent resin is placed on the chip, and an ultraviolet-transparent resin is placed on the resin. By attaching a flat UV-transparent window member, 4! It is possible to realize a 111 sealed EPROM device. According to the resin-sealed EPROM device, the sealing temperature is low because the resin (insulating side 1) is used to seal (enclose) the device, and as a result, it is possible to prevent the metal from forming into a metal. It can be connected to the mounting part to simplify the work and structure, and high-speed wire bonding can be achieved by using gold wire as the thin metal wire, reducing work time.Furthermore, the sealing temperature is low (if possible). , EPRO
Thermal stress given to the M chip can also be reduced. Furthermore, according to the resin-sealed EPROM device, conventional EPR devices configured with a cerdip type or ceramic type package
It is overwhelmingly lighter than OM devices, which eases the restrictions on the number of devices that can be mounted on a printed circuit board, and since it is made of hard thermosetting resin, it does not chip or chip like a cerdip-type puff cage. Not only that, but it is also inexpensive. In addition, although the EPROM device of the present invention uses an ultraviolet-transparent resin, the resin only needs to be dropped by botting onto a flat ultraviolet-transparent window member during manufacturing, and the resin can be dropped onto a hollow bottomed cap. Because it is easy to inject resin without having to fill it through a narrow filling hole, etc.
It does not cause problems such as air bubbles in the inside. That is, a high-performance EPROM device can be obtained with a high yield. □
第１図はこの発明のＥＰＲＯＭ装置の一実施例を示す断
面図、第２図は従来のサーディツプパッケージ構造のＥ
ＰＲＯＭ装置の外観斜視図、第３図は第２図のＩ−１線
断面図、第４図は第３図の部分拡大図、第５図はこの発
明の一実施例の装置の製造途中における断面図である。
２１・・・リードフレーム、２２・・・素子搭載部、２
３・・・外部導出端子、２４・・・ＥＰＲＯＭチップ、
２５・・・金属細線、２６・・・紫外線透過性ｔｉｉｍ
、２７・・・紫外線透過性窓部材、２８・・・絶縁性樹
脂。
２１：＋Ｊ−ｒ７し嶋
２４：ＥＰＲＯＭ斗−Ｉプ
２５；金属！ｍｌｌ
第２図
第３図
第５図
り１FIG. 1 is a sectional view showing an embodiment of the EPROM device of the present invention, and FIG.
FIG. 3 is a cross-sectional view taken along line I-1 in FIG. 2, FIG. 4 is a partially enlarged view of FIG. 3, and FIG. FIG. 21... Lead frame, 22... Element mounting part, 2
3...External lead-out terminal, 24...EPROM chip,
25...Thin metal wire, 26...UV-transparent tiim
, 27... UV-transparent window member, 28... Insulating resin. 21: +J-r7 Shijima 24: EPROM To-Ipu 25; Metal! mll Figure 2 Figure 3 Figure 5 Diagram 1
Claims (1)
と、このリードフレームの素子搭載部上に搭載され、表
面の電極パッドが少なくともリードフレームの外部導出
端子のポスト部に金属細線によつて配線されたＥＰＲＯ
Ｍチップと、このＥＰＲＯＭチップ上に盛られた紫外線
透過性樹脂と、この紫外線通過性樹脂の上部に取着され
た平板状の紫外線透過性窓部材と、以上の構造体を、リ
ードフレームの外部導出端子の外部導出部を除いて、か
つ、平板状の紫外線通過性窓部材の表面を上面に露出さ
せて包囲する絶縁性樹脂とを具備してなるＥＰＲＯＭ装
置。A lead frame having an element mounting part and an external lead-out terminal, and an EPRO mounted on the element mounting part of this lead frame, and having an electrode pad on the surface wired with a thin metal wire to at least a post part of an external lead-out terminal of the lead frame.
The M chip, the ultraviolet-transparent resin mounted on the EPROM chip, the flat ultraviolet-transparent window member attached to the top of the ultraviolet-transparent resin, and the above structure are attached to the outside of the lead frame. 1. An EPROM device comprising an insulating resin that exposes and surrounds the surface of a flat ultraviolet-transmissive window member, excluding the external lead-out portion of the lead-out terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59236588A JPS61115339A (en) | 1984-11-12 | 1984-11-12 | Eprom device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59236588A JPS61115339A (en) | 1984-11-12 | 1984-11-12 | Eprom device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61115339A true JPS61115339A (en) | 1986-06-02 |
Family
ID=17002860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59236588A Pending JPS61115339A (en) | 1984-11-12 | 1984-11-12 | Eprom device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61115339A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0499758A1 (en) * | 1990-10-15 | 1992-08-26 | STMicroelectronics S.A. | Moulded integrated circuit box with window and moulding processing |
-
1984
- 1984-11-12 JP JP59236588A patent/JPS61115339A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0499758A1 (en) * | 1990-10-15 | 1992-08-26 | STMicroelectronics S.A. | Moulded integrated circuit box with window and moulding processing |
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