JPS61115170A - Moving average calculating device - Google Patents

Abstract

PURPOSE:To make it possible to calculate a moving average value at high speed by giving the oldest data taken out from the register for being processed to the subtracting device, by subtracting the taken-out oldest data from the cumulatively added value, and by dividing the cumulatively added value by averaged number to obtain the moving average. CONSTITUTION:Data taken out from register 5 for being processed and the cumulatively add data ratched in register 6B are added together by digital adder 6A, the result of the addition is rewritten on register 6B by clock CLK2 and the new data ratched in register 5 is added to the cumulatively added data ratched in register 6B. Repeating this operation enables past data to be accumulated for addition. On the other hand, from circuit 8, for example, the data item counted 10th back from the present one is taken out and supplied to subtractor 7, and as a result when the 11th data from the initial state is inputted to accumulation adder 6 for being processed, the cumulatively added data can be updated by subtracting the data item counted 10th back from the cumulatively added data using subtractor 7. This updated add data is divided by averaged number M using divider 15, thereby obtaining the moving average number.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention can be used to remove noise mixed into analog signals when eAD converting various analog signals and importing them into a digital processing device. The present invention relates to a moving average calculation device.

"Prior Art" For example, a moving average method is often used as a method for removing noise components mixed into measurement signals when AD converting various measurement signals and importing them into a data processing device. The moving average method is to add the past N data and find the average value, and when the next data is imported, remove the oldest data before that N data, find the average value each time, and calculate the average value. This is done by using the converted value as data.

According to this moving average method, there is a large difference between the preceding and succeeding data values due to noise (even if a direct input is made, the data is averaged, so the noise component is not directly taken in as data, so effects can be removed.

Conventionally, the digital signal converted from AD using an AD converter is input to two microcomputers, and the microcomputer calculates the moving average using software. This method was common. When the moving average is determined by software in this way, it takes time to calculate the moving average, which causes the disadvantage that analog signals cannot be captured at high speed.

For this purpose, for example, as shown in FIG. 2, a buffer memory 4 is provided between the AD converter 2 and the microcomputer 3, data is written from the AD converter 2 into this buffer memory 4 at high speed, and the microcomputer 3 4
One possible method is to calculate a moving average by sequentially importing the data stored in .

"Problem to be solved by the invention" By providing the buffer memory 4 in this way, A.
The D converter 2 can AD convert an analog signal at high speed and write it into the memory 4. However, since the moving average (goods) is still calculated by a microcomputer, it takes time to calculate the moving average value. As a result, there is a speed difference between the AD conversion operation and the moving average calculation operation, so that unless the storage capacity of the buffer memory 4 is selected to be a considerably large value, it will not be possible to withstand long-term use. In addition, since the data retention time in the buffer memory 4 becomes long, the analog signal given to the AD converter 2 and the microcomputer 3
There is a time lag between the moving average value outputted from the moving average value, and there is a drawback that the input and the moving average cannot be synchronized.

"Means for solving the problem" What is the input processed data in this invention? An accumulative adder that performs cumulative addition, a cascade-connected register that stores N pieces of past processed data, and a cascade-connected register that stores N pieces of past processed data; A gate that takes out the processed data, a subtractor that subtracts the cumulative sum calculated by the total cumulative adder for the processed data taken out by this gate, and a subtracter that divides the cumulative sum subtracted by this subtracter by the averaging number. A moving average calculation device is constructed by the divider.

"Operation" According to the moving average calculation device according to the present invention, each time data to be processed is input, the accumulator adds the data to be processed, and at the same time, the oldest processed data from the cascaded registers is added. Take out the data, give the oldest data to be processed to the subtracter, and add the past cumulative data in the subtracter. The moving average is calculated by dividing by the number.

Accordingly, according to the moving average calculation device according to the invention, the moving average amount can be obtained at the same time each time the data to be processed is input. Therefore, since the moving -V average can be obtained at a high speed, an analog signal that changes at a relatively high speed can be taken in as a moving average value, and as a result, noise components can be removed.

"Embodiment of the Invention" FIG. 1 shows an embodiment of a moving average calculation device according to the present invention. In Figure 1, 1 is an analog signal input terminal, 2 is an A
A D converter is shown. The digital i-processed data that has been AD converted by the AD converter 2 is temporarily stored in the register 5.

It is assumed that this register 5 has a capacity of all parallel antinode number bits in order to take in the AD conversion output of the AD converter 2. The data to be processed temporarily stored in the register 5 is provided to the cumulative adder 6.

The accumulative adder 6 includes a digital adder 6A, and the output of the digital adder 6A is taken in and added to the digital adder 6.
It can be constituted by registers 6B and 6K for giving the cumulative addition value up to the previous time to the input terminal B of the capacity of A.

In this example, the output of the register 6B is shown through the subtracter 7 to one input terminal B of the adder 156A for the past cumulative 170 calculations (direct).
By giving Ikekata's input terminal B the oldest cumulatively added data to be processed! ll Cumulative addition [The oldest data can be subtracted from the current.

8 shows a circuit for extracting the oldest past data to be processed. This circuit 8 consists of N cascaded registers 9A.
, 9B...9N and these N registers 9A~
Gate 10A, which retrieves data from the desired address of 9N;
1. OB... ION and an OR gate 11. The data taken out to the output side of OR gate 11 is applied to gate 12.

This gate 12 is controlled to be open by receiving a gate signal 5UBE from a controller 13, and provides the oldest processed data in the past to the subtracter 7 at an appropriate timing.

Reference numeral 14 denotes a gate that subtracts the oldest past data from the cumulative adder 6 and takes out the updated cumulative added value at the timing when the updated cumulative added value is output. The cumulative addition value updated by this gate 14 is taken out and the divider 1
5 to input terminal A. The averaging number M is given from the controller 13 to the input terminal B of the divider 150 Ikegata, the cumulative addition value is divided by this averaging number M, and the moving average [N] is output to the output terminal 16. do.

Reference numeral 17 denotes a decoder for taking in the averaging number M and giving an open signal to one of the gates 108 to 1ON. In other words, register 9A corresponding to the averaging number M
Outputs a gate selection signal for extracting the output signal of the 9N stage.

“Operation of the Embodiment” In the above-described implementation structure, the controller 13 can be configured by, for example, a microcomputer, and the input device 1A
By inputting the averaging number M from 13A, the decoder 1
7 and the divider 15 are given an averaging number M. By setting this averaging number M, one of the gates 10A to IOH is selected and controlled to be open. For example, when M=10 is set, the gate that takes out the output of the 10th register of registers 9A to 9N is controlled to be open, and the data to be processed that was AD converted 10 times ago is taken out, and the data is transferred to the subtracter 7.
give to

On the other hand, in the cumulative adder 6, each time new data to be processed is given to the register 5 from the AD converter 2, the data to be processed is directly added to the past cumulative addition in the digital adder 6A. That is, the past cumulative addition [direct] is latched in the register 6B, and its latch output is applied to the input terminal B of the digital adder 6A via the subtracter 7. Therefore, the data to be processed given from register 5 □ and the cumulative addition data latched in register 6B are added by digital adder 6A, and the addition result is rewritten to register 6B by CLK2, and the written cumulative data is New data latched in register 5 is added to the added data. By repeating this operation, past data can be cumulatively added.

On the other hand, from the circuit 8, for example, the previous 10 data is taken out and given to the subtracter 7, so that the cumulative adder 6 is supplied with 11 data from the initial state.
When the 10th data to be processed is input, the 10th previous data is subtracted from the cumulative value by the subtracter 7, thereby updating the cumulative data. Therefore, the operation of adding new data from the register 5 to the cumulative adder 6 and the operation of subtracting the oldest data from the cumulatively added data can be performed at the same time. Therefore, the cumulative addition data can be updated at the speed at which new data is loaded into the register 5, and the moving average value can be obtained by dividing this updated cumulative addition data by the averaging number M in the divider 15. Can be done.

"Effects of the Invention" As described above, according to the present invention, a moving average value can be obtained at high speed, and even an analog signal that changes relatively quickly can be taken in as a signal from which noise has been removed.

"Modified Embodiment of the Invention" In the above, a structure in which N stages of registers are cascaded is used as a means to obtain past data, but as a method for that purpose, FiFo
(First-in-first-act) memory can also be used. When all the FiFo memories are used, the circuit scale can be reduced even if the number of stages is increased.

Further, in the above description, a case has been described in which the register 6B is connected between the output to the adder 6 and the input terminal A of the subtracter 7, but it may be connected between the outputs of the six adders and the gate 14. With this configuration, division processing and addition/subtraction processing can be performed at the same time.

Furthermore, although the above description has been given of an example in which the register 5 is specially provided, the register 9A having N stages connected in cascade can be used in place of the register 5. In this case, it is necessary to shift the connection stage of the gates 10A to 1ON from which past data is extracted one stage at a time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the invention in detail,
FIG. 2 is a block diagram for explaining a conventional moving average calculation device. 1: Analog input terminal, 2: AD converter, 5°6B, 9
A~9N: Register, 6: Accumulator, 6A: Digital adder, 7: Subtracter, 8: Circuit for retrieving the oldest past data, 10A~ION: Gate, 11 Nior gate, 12: Gate, 13: Controller, 13A: manual means,
14: Gate, 15: Divider, 16: Output terminal. Patent applicant: Takeda Riken Kogyo Aji Shiki Co., Ltd. Nippon Kameshin Telephone Corporation

Claims (1)

[Claims] (1) A, a cumulative adder that cumulatively adds processed data, and B
, a cascade-connected register that stores N pieces of past processed data, and C, a gate that retrieves past processed data from a stage corresponding to the averaged number of this register by a number corresponding to the number of averages. , D. A subtracter that subtracts the processed data taken out by this gate from the cumulative value added by the adder, and E. Averaging the cumulative value obtained by adding the data subtracted by this subtracter and new data. A moving average calculation device consisting of a divider that divides by a number and a divider that divides by a number.