JPH0319726B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field to which the invention pertains] This invention provides a digital differential signal with a good signal-to-noise ratio of the AD-converted signal when AD-converting various analog signals and inputting them into a digital arithmetic processing device. The present invention relates to a differential filter circuit that can be obtained.

[Prior art]

For example, when AD converting various measurement signals and importing them into a data processing device, a differential filter is often used as a method of obtaining a digital differential signal of the measurement signals.

The differential filter is expressed by the following formula (1) (for example, described in "Digital Filter" by RW, HAMMING, published by Science and Technology Publishing Co., Ltd., July 25, 1980, page 111)
As shown in , Y _o,N = 3/N (N+1) ( _2N +1) _N 〓 ^k=-N _kXo+k = 1/K= (N+1)(2N+
1)/3 Weighted cumulative addition value X _o,N = _N 〓 ^k=-N _kXo+k Past M (=2N+1) processed data X _o+k including captured processed data N≦
k≦N), a constant k is added to the processed data X _o+k.
The value Y o,N obtained by dividing the weighted cumulative addition value = X _{o,N by} the normalization constant K by cumulatively adding these multiplied values is used as differential data.

According to this differential filter, even if differentiation results in a differential signal with significant noise, a relatively smooth differential signal can be obtained, and a decrease in the signal-to-noise ratio due to differentiation can be reduced.

[Problem that the invention seeks to solve]

Conventionally, the common method was to input a digital signal AD-converted by an AD converter to a microcomputer, and then use software to determine the differential value in the microcomputer according to equation (1).

However, when the differential value is calculated by software according to equation (1) in this way, it takes time to calculate the differential value, and there is a problem that analog signals cannot be captured at high speed.

For this reason, for example, as shown in Figure 2, AD
A buffer memory 54 is provided between the converter 52 and the microcopy user 53, and this buffer memory 54
writes data at high speed from the AD converter 52 to
The microcomputer 53 has a buffer memory 54
One possible method is to calculate the differential value by sequentially importing the data stored in the . Note that 51 is an analog signal input terminal.

By providing the buffer memory 54 in this way, the AD converter 52 can convert analog signals at high speed.
The data can be AD converted and written to the buffer memory 54. However, since the calculation of the differential value is still performed by a microcomputer, it takes time to calculate the differential value.

As a result, there is a speed difference between the AD conversion operation and the differential value calculation operation, so there is an inconvenience that the buffer memory 54 cannot withstand long-term use unless the storage capacity of the buffer memory 54 is selected to be a considerably large value. In addition, since the data retention time in the buffer memory 54 becomes longer, a time lag occurs between the analog signal applied to the AD converter 52 and the differential signal output from the microcomputer 53, resulting in a difference between the input and the differential output. The drawback is that simultaneity cannot be achieved.

[Purpose of the invention]

In order to solve the above-mentioned drawbacks of the prior art, the present invention reduces the amount of calculation by using a recurrence formula to update the differential value, and performs the differential value calculation operation using parallel processing using a logic circuit configuration. The object of the present invention is to provide a differential filter method and its circuit that speeds up the processing.

[Means to solve the problem]

"Method" First, the method of the present invention will be explained.

The method of this invention is as follows, which is obtained by modifying equation (1).
By using the relationship between the weighted cumulative addition value = X _{o +1,N} and = X _o,N shown in equation (2), the amount of calculation required for calculating the differential value is significantly reduced.

= X _o+1,N == X _o,N − _o,N +N (X _oN +X _o+1+N ) ...(2) However, cumulative addition value _o,N = _N 〓 ^k=-N+1 = X _o+K First, divide X _o,N by the normalization constant K to get the differential value Y _o,N
Calculate.

When the next data X _o+1+N is imported, (2)
As shown in the formula, the value obtained by multiplying the sum of the imported data X _o+1+N and the oldest data X _oN M times before it by a constant N is added to the weighted cumulative sum value = X _o,N. Then, the cumulative addition value _{o, of the processed data from the 1st to the 2Nth past imported processed data.}
By removing _N , update = X _o,N to = X _o+1,N ,
Differential data is obtained by dividing by the standard rating constant K each time.
Find Y _o+1,N .

"Configuration" Next, a circuit configuration for realizing the above method will be described.

In order to realize the above-described method, the present invention includes an accumulative adder that sequentially adds up input data to be processed, a cascade-connected register that stores up to 2N+1 past data to be processed, and this register. A gate that extracts past processed data that goes back a number of times corresponding to the number of samples from a stage corresponding to the number of samples, and a subtraction that subtracts the processed data extracted by this gate from the cumulative value added by the cumulative adder. an adder that adds the captured data to be processed and the data to be processed taken out by the gate, a multiplier that multiplies the added value added by this adder by a constant N, and a multiplier that is multiplied by this multiplier. A cumulative adder that cumulatively adds values, a subtracter that subtracts the output data of the subtracter from the data cumulatively added by the cumulative adder, and a subtracter that adds the data subtracted by this subtracter and the output data of the multiplier. A differential filter circuit is constructed by a divider that divides the added value by a constant.

"Operation" According to the differential filter circuit of the present invention, the adder operates every time the data to be processed X _o+1+N is input.
Add X _o+1+N and the oldest past processed data X _oN taken out from the cascaded registers, multiply the added value by a constant N, and then
The cumulative adder A1 cumulatively adds (X _o+1+N +X _oN ) and sends the result to the subtracter B1.

In parallel with this, the cumulative adder A2 adds data to be processed.
At the same time as cumulatively adding X _o+N ,
Take out X _oN and give it to subtractor B2, subtracter B
2, subtract X _oN from _o-1,N + _o+N , obtain the subtracted cumulative addition value _{o,N ,} and send it to subtractor B1. The differential value _{Y o+1, N is obtained by subtracting X o,N} from o+1+N +X _oN ) and dividing this subtracted value _{o +1,N} by the normalization constant K.

Therefore, according to the differential filter circuit according to the present invention, a differential value can be simultaneously obtained each time data to be processed is input. Therefore, since the differential can be determined at high speed, a desired differential signal can be obtained in real time from a signal that changes at a relatively high speed.

[Embodiments of the invention]

FIG. 1 shows an embodiment of a differential filter circuit according to the present invention.

In Fig. 1, 1 is an analog signal input terminal;
2 indicates an AD converter.

The digital data to be processed X _o+1+N that has been AD converted by the AD converter 2 is temporarily stored in the register 5 .

X _o+1+N temporarily stored in register 5 is added to adder 6
is applied to input terminal A of .

Give X _oN to the other input terminal B of the adder 6,
Adder 6 outputs the added value X _o+1+N +X _oN .

A portion 13 surrounded by a chain line shows a circuit for extracting X _oN .

This circuit 13 consists of M cascaded registers 1
4A, 14B, . . . 14M, gates 15A, 15B, .

The data taken out to the output side of the OR gate 16 is applied to the gate 17. This gate 17 is controlled to open when the gate signal SUBE is applied from the controller 24, and X _oN is added to the adder 6 at an appropriate timing.
give to

Next, the output data of the adder 6 is applied to the input terminal A of the multiplier 7, and the controller 24 is applied to the other input terminal B.
A constant N is given from , and the result of multiplying both is given to the input terminal A of the digital adder 8A.

The cumulative adder 8 (the part surrounded by the broken line) takes in the output of the digital adder 8A and the output of this digital adder 8A, and sends the weighted cumulative addition value up to the previous time to the other input terminal B of this digital adder 8A. It can be configured by a register 8B for giving.

This example shows a case where the past weighted cumulative value is applied to one input terminal B of the digital adder 8A from the output of the register 8B via the subtracter 9. Therefore, the other input terminal B of the subtracter 9
By giving _{o and N} , the weighted cumulative addition value can be updated.

A portion 10 surrounded by a dashed line shows a circuit for extracting the cumulative addition values _{o and N.} This circuit can be constructed by an accumulative adder 11 and a subtracter 12.

The cumulative adder 11 (the part surrounded by the broken line) includes a digital adder 11A and this digital adder 11.
This digital adder 11A takes in the output of
A register 11B for giving the cumulative addition value up to the previous time to the other input terminal B of the register 11B.

In this circuit 10, a case is shown in which the output of the register 11B is applied to one input terminal B of the adder 11A via a subtracter 12 to give a past cumulative addition value.

By applying the output of the circuit 13 to the other input terminal B of the subtracter 12, the desired cumulative addition values _o,N can be obtained from the output terminal of the subtracter 12.

Next, 20 is the weighted cumulative value updated from the cumulative adder 8 = X _{o+1, at the timing when N} is output = X _o+
A gate is shown that takes out _{1 and N} and supplies them to the input terminal A of the divider 21.

A normalization constant K is given from the control 24 to the other input terminal B of the divider 21, the output value is divided by this normalization constant K, and the calculation result, that is, the differential filter output Y _o+1,N is output. Output to terminal 22.

Note that 23 takes in the number of sample points M and calls gate 1.
A decoder for providing an open signal to any one of gates 5A to 15M is shown. In other words, the decoder 23 has registers 14A to 14A corresponding to the number of sample points M.
Outputs a gate selection signal for taking out the output signal of the 14M stage.

"Operation of the Embodiment" In the embodiment described above, the controller 24 can be configured by, for example, a microcomputer, and by inputting the number of sample points M from the input means 24A, the constant N is input to the multiplier 17 and the decoder 23
The number of sample points M is given to , and the normalization constant K is given to the divider 21 .

Gates 15A to 15M depending on the setting of the number of sample points M
One of them is selected and controlled to be open.

For example, if M=7, register 14
The gates for taking out the outputs of the seventh-stage registers A to 14M are controlled to be open, and the seven previous AD-converted to-be-processed data X _o-3 are taken out and the data is given to the adder 6.

On the other hand, in adder 6, AD converter 2 is stored in register 5.
Every time new processed data X _o+4 is given from
X _o+4 and output data X _o-3 of the circuit 13 are added.

The multiplier 7 inputs the output data (X _o+4 +X _o-3 ) of the adder 6 into the input terminal A, multiplies it by a constant N=3 set at the other input terminal B, and obtains the multiplied value 3.
(X _o+4 +X _o-3 ) is sent to the cumulative adder 8.

In the cumulative adder 8, every time new data to be processed is given to the register 5 from the AD converter 2, the output of the multiplier 7 is added to the past weighted cumulative addition value in the adder 8A.

That is, = X _o,3 is latched in register 8B, and the latch output is sent to adder 8 via subtracter
A is applied to input terminal B of A.

Therefore, the data given from multiplier 7 and =X _o,3 latched in register 8B are added by adder 8A, and the addition result is written again to register 8B by clock CLK2, and the written weight New data output from the multiplier 7 can be added to the cumulative addition value.

On the other hand, since _o,3 is taken out from the circuit 10 and given to the subtracter 9, for example, if M=7, when the eighth data to be processed is input, _o,3
By subtracting from _o,3 +N (X _o+4 +X _o-3 ) with the subtractor 9, the weighted cumulative addition value = X _o,3 can be updated.

Therefore, the operation of adding 3·(=X _o+4 +X _o-3 ) to _{X o} ,3 and the operation of subtracting _o,3 can be performed at the same time.

Therefore, the weighted cumulative addition value can be updated at the speed at which new data is taken into the register 5.
By dividing this updated weighted cumulative addition value X _o+1,3 by the normalization constant K=28 using the divider 21, the differential value can be updated to Y _o+1,N. can.

The flow of the above calculation will be explained below.

The A terminal of the subtracter 9 is given the previous (first past) output data from the register 8B, that is, the weighted cumulative addition value = X _o,N , and the B terminal is given the circuit 10.
_{o and N} are given from the gate 18 through the gate 18. Therefore, the output of the subtracter 9 is the value obtained by subtracting o _{,N from =X o ,N} , and that value is applied to the B terminal of the adder 8A. In addition, the A terminal of the adder 8A is connected to the multiplier 7.
The output of , that is, N(X _oN +X _o+1+N ) is given. Then, the added value of both, that is, _the value obtained by subtracting _{o,N from} the previous output data
The value obtained by adding X _o+1+N ) is the current output data X _o+1,N
The signal is sent to the divider 21 via the gate 20 as a signal. Then, it is divided by the normalization constant K by the divider 21 to obtain the current differential value, which is output from the output terminal 22.

Further, the output of the adder 8A, that is, the current output data, is stored in the register 8B and used as the first past output data in the next calculation, and thereafter, the cumulative addition value is sequentially updated.

By the way, in the circuit 10, when the cumulative adder 11 receives X _o+4 from the AD converter 2 to the register 5, the adder 11A adds X _o+3 to _o-1,3 .

That is, _o-1,3 is latched in the register 11B, and the latch output is applied to the input terminal B of the adder 11A via the subtracter 12.

Therefore, X _o+3 given from register 14A and _o-1,3 latched to register 11B are added to adder 11.
A is added, and the addition result is sent to clock CLK2.
The new data taken in from the register 14A is added to the written cumulative addition value.

By repeating this operation, past data can be cumulatively added.

On the other hand, from the circuit 13, for example, X _o-3 is taken out and given to the subtracter 12, so when X _o+3 is input to the cumulative adder 11, X _o-3 is extracted from the subtracter 12.
2, the cumulative addition value _o-1,3 can be updated by subtracting it from _o-1,3 +X _o+3 .

Therefore, from register 14A to cumulative adder 11
The operation of adding X _o+3 and the operation of subtracting X _o-3 from the cumulative addition value can be performed at the same time.

Therefore, the cumulative addition value _o-1,3 can be updated at the speed at which new data is taken into the register 5, and this updated cumulative addition value _o,3 can be output to the subtracter 9.

"Modified Embodiment of the Invention" In the above description, a structure in which M stages of registers are cascaded is used as a means for obtaining past data, but other methods include first-in, first-out, etc.
Memory (FiFo memory) can be used.
When using FiFo memory, the circuit scale can be reduced even if the number of stages is increased.

Note that the FiFo memory has a cascade structure in which input signals are sent sequentially and output from the final stage in the order in which they were input.

Further, although the case where the register 8B is connected between the output of the adder 8A and the input terminal A of the subtracter 9 has been described above, it may be connected between the output of the adder 8A and the gate 20. With this configuration, division processing and addition/subtraction processing can be performed at the same time.

Furthermore, although the above description has been given of an example in which the register 5 is specially provided, the register 14A having M stages cascaded can be used instead of the register 5.

In this case, gate 1 to retrieve past data
It is necessary to shift the connection stages of 0A to 10M one stage at a time.

If you add one divider, input the output of the adder 11A to one input terminal, input the constant 2N+1 set by the controller 24 to the other input terminal, and perform division, this divider The output of is AD converter 2
This is the moving average of the AD converted signal.

Thereby, it is possible to simultaneously obtain an input signal whose signal-to-noise ratio has been improved by the moving average and a differential signal whose signal-to-noise ratio has been improved by the differential filter.

〔Effect of the invention〕

As described above, according to the present invention, differential values can be obtained at high speed, and differential signals with a good signal-to-noise ratio can be obtained in real time even for input signals that change relatively quickly. Excellent effects can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional differential filter. "Explanation of symbols", 1...Analog input terminal, 2
... AD converter, 5 ... Register, 6 ... Adder, 7 ... Multiplier, 8, 11 ... Accumulation adder, 8
A, 11A...Adder, 8B, 11B...Register, 9, 12...Subtractor, 10...Circuit for extracting the cumulative addition value of the M-1th data after the captured data, 13... ...Circuit for extracting M-th data from captured data, 14A~
14M...Register, 15A-15M...Gate, 16...Or gate, 17, 18, 19, 2
0...Gate, 21...Divider, 22...Output terminal, 23...Decoder, 24...Controller, 24A
...Input means.

Claims (1)

[Claims] 1 Add the captured data to be processed and the past 2N+1st processed data from the captured data to be processed, multiply this added value by a constant N, and calculate the past 1 data. Subtract the cumulative sum of the past 2N processed data from the past 1st output data, add the above multiplication result to the subtraction result to make the current output data, and set this output data as a constant. A differential filter method that is characterized by calculating differential values by dividing. 2. An accumulative adder that cumulatively adds the captured data to be processed, a storage device that stores up to 2N+1 past data to be processed, and a storage device that stores up to 2N+1 pieces of past data to be processed, and a storage device that stores data from a stage corresponding to the number of sample points in the memory device by a number corresponding to the number of sample points. A gate for extracting past processed data,
a subtracter that subtracts the processed data taken out by the gate from the cumulative addition value cumulatively added by the cumulative adder; an adder that adds the taken processed data and the processed data taken out by the gate;
A multiplier that multiplies the added value added by this adder by a constant N, an accumulative adder that cumulatively adds the multiplied value multiplied by this multiplier, and an output of the above subtracter from the data cumulatively added by this accumulative adder. A differential filter circuit comprising a subtracter that subtracts data, and a divider that divides a cumulative value obtained by adding the data subtracted by the subtracter and the output data of the multiplier by a constant. 3. The differential filter circuit according to claim 2, wherein a FiFo memory is used as the storage means.