JPS61114596A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board

Info

Publication number
JPS61114596A
JPS61114596A JP23640084A JP23640084A JPS61114596A JP S61114596 A JPS61114596 A JP S61114596A JP 23640084 A JP23640084 A JP 23640084A JP 23640084 A JP23640084 A JP 23640084A JP S61114596 A JPS61114596 A JP S61114596A
Authority
JP
Japan
Prior art keywords
layer
printed wiring
wiring board
multilayer printed
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23640084A
Other languages
Japanese (ja)
Inventor
茂夫 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23640084A priority Critical patent/JPS61114596A/en
Publication of JPS61114596A publication Critical patent/JPS61114596A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分計〕 本発明は、多層プリント配線板に関するものである。[Detailed description of the invention] [Industrial usage total] The present invention relates to a multilayer printed wiring board.

〔従来の技術〕[Conventional technology]

従来の多層プリント配線板構成を4層プリント板に例を
とって説明する。従来の4層プリント板は1層、4層が
信号層の個別層、2層がグランド層、3層がTri源層
の共通層でイ?り成され、共31層への接Fff、は、
各プリント板で、接続位置の一般部品ビンまた1iV1
aホールにて固定されたスルーホール位置でなされてい
た。第3図は従来の内層構成を示すもので、図中10が
接続ホール、12がクリアランスホールである。
A conventional multilayer printed wiring board structure will be explained using a four-layer printed wiring board as an example. Conventional 4-layer printed circuit board has 1 layer, 4th layer is individual layer for signal layer, 2nd layer is ground layer, and 3rd layer is common layer for Tri source layer. The connection Fff to the 31st layer is
On each printed board, the general parts bin or 1iV1 at the connection location
This was done with a through-hole position fixed at the a-hole. FIG. 3 shows a conventional inner layer structure, in which 10 is a connection hole and 12 is a clearance hole.

〔解決すべき問題点〕[Problems to be solved]

従来の多層プリント配線板にあっては、多品種のチップ
形状を搭載する事を考えた場合共通パターン層(グラン
ド、gLmm>への接続位置の固定化が出来ず共通層の
意味が薄れ始めた。また共通層が個別扱いとなると原画
作成最が多くなりプリント板の価格に影響し安価なプリ
ント板が供給出来なくなる欠点があった。父、たとえ内
層接続位置を固定化して、内層の電源、ブランド層の共
通化を図ったとしても、搭載部品の電源、グランド供給
が直接内層接続が小米ないものに対しては、信号配線層
で、幅広パターンにて配線する必要があり、配線収容性
面でも阻害°平置となる欠点もあった。
In conventional multilayer printed wiring boards, when considering mounting a wide variety of chip shapes, it is not possible to fix the connection position to the common pattern layer (ground, gLmm>), and the meaning of the common layer begins to diminish. .Also, if the common layer were to be treated individually, the original drawings would have to be created, which would affect the price of the printed board, making it impossible to supply cheap printed boards.My father, even if the inner layer connection position was fixed, the power supply of the inner layer, Even if we try to standardize the brand layer, if the power supply and ground supply of mounted components does not have a direct inner layer connection, it will be necessary to wire in a wide pattern on the signal wiring layer, which will reduce the wiring capacity. However, it also had the drawback of being inhibited and placed flat.

〔問題点の解決手段〕[Means for solving problems]

本発明は、上記従来の問題点を解決し、共通層のグラン
ド層、電源層各1種類であらゆる位置で共通層に接続出
来得るようにするものであって、その解決手段として、
信号層及び市源、グランド層からなる多層プリント配線
板において、上記電源、グランド層の接続位置を、交互
にかつ、繰返し配線格子外に共通的に配置したことを特
徴とする多層プリント配線板を提供せんとするものであ
るO 〔実施列〕 次に本発明を4層プリント板に実施した例を図面を参照
して説明する。
The present invention solves the above-mentioned conventional problems and enables connection to the common layer at any position using one type of common layer, one type of ground layer and one type of power layer.
A multilayer printed wiring board consisting of a signal layer, a power source, and a ground layer, characterized in that the connection positions of the power source and ground layers are alternately and repeatedly commonly arranged outside the wiring grid. [Embodiment] Next, an example in which the present invention is implemented in a four-layer printed board will be described with reference to the drawings.

従来多くの場合41i’lプリント板は第1層、第4層
を信号層の個別層、第2R4,第3PIをグランド層 
4源層の共通層で構成されていた。
Conventionally, in many cases, 41i'l printed boards used the 1st and 4th layers as individual signal layers, and the 2nd R4 and 3rd PI as ground layers.
It was composed of a common layer of four source layers.

第1図は本発明を実施した共通グランド層(または71
1 fi、N5 )の銅箔パターン8成を示したもので
ある。一般部品穴又は、’Viaホールに対しての内層
のクリアランス部2の間隙に接続ランド1を設は例えば
クリアランス部2に形成されるスルーホール3をグラン
ド(または電源)に接続したい場合Fi第2図で示す様
に前記接続ランド部lにスルーホール4を形成し信号層
で配線する事により接続が完了する。この様に、電源、
グランド接続位置を交互に共通的に配置する事により所
望の位置で電源、グランドの接続が可能となり、且つ内
層パターンの共通化も可能となる。又、内層接続位置を
配線格子外に設定する事により、信号層での配線収容面
への影響も軽減出来るものである。
FIG. 1 shows a common ground layer (or 71
This figure shows eight copper foil patterns of 1 fi, N5). For example, if you want to connect the through hole 3 formed in the clearance part 2 to the ground (or power supply), the connection land 1 is installed in the gap between the clearance part 2 of the inner layer with respect to the general component hole or the 'Via hole. As shown in the figure, the connection is completed by forming a through hole 4 in the connection land l and wiring in the signal layer. In this way, the power supply,
By alternately and commonly arranging the ground connection positions, it is possible to connect the power supply and the ground at desired positions, and it is also possible to share the inner layer pattern. Furthermore, by setting the inner layer connection position outside the wiring grid, the influence on the wiring accommodation surface of the signal layer can be reduced.

〔発明の効果〕〔Effect of the invention〕

本発明は以上説明した様に共通層のグランド層電II層
を各1種類起すだけで容易に安定したグランド、電源供
給を最短接続でき且つ安価な多層プリント配線板を提供
出来るという効果がある。
As explained above, the present invention has the advantage that it is possible to provide an inexpensive multilayer printed wiring board in which stable grounding and power supply can be easily connected in the shortest possible time by simply forming one type of common ground layer and power supply II layer.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の一実施例を部分的に表わす多層プリ
ント配線板の内層構成を示す部分説明図、@2図は、本
発明の信号層パターン例を示す説明図、 そして、第3図は、従来の多層プリント配線板の内層構
成を示す説明図である。
FIG. 1 is a partial explanatory diagram showing the inner layer structure of a multilayer printed wiring board partially representing an embodiment of the present invention, @2 is an explanatory diagram showing an example of a signal layer pattern of the present invention, and The figure is an explanatory diagram showing the inner layer structure of a conventional multilayer printed wiring board.

Claims (1)

【特許請求の範囲】[Claims] 信号層及び電源、グランド層からなる多層プリント配線
板において、上記電源、グランド層の接続位置を、交互
にかつ繰返し配線格子外に共通的に配置したことを特徴
とする多層プリント配線板。
A multilayer printed wiring board comprising a signal layer, a power supply layer, and a ground layer, wherein the connection positions of the power supply layer and the ground layer are alternately and repeatedly commonly arranged outside the wiring grid.
JP23640084A 1984-11-09 1984-11-09 Multilayer printed wiring board Pending JPS61114596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23640084A JPS61114596A (en) 1984-11-09 1984-11-09 Multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23640084A JPS61114596A (en) 1984-11-09 1984-11-09 Multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPS61114596A true JPS61114596A (en) 1986-06-02

Family

ID=17000196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23640084A Pending JPS61114596A (en) 1984-11-09 1984-11-09 Multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPS61114596A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006114741A (en) * 2004-10-15 2006-04-27 Ibiden Co Ltd Multilayer core substrate and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006114741A (en) * 2004-10-15 2006-04-27 Ibiden Co Ltd Multilayer core substrate and manufacturing method thereof
JP4551730B2 (en) * 2004-10-15 2010-09-29 イビデン株式会社 Multilayer core substrate and manufacturing method thereof
US7905014B2 (en) 2004-10-15 2011-03-15 Ibiden Co., Ltd. Manufacturing method of multilayer core board

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