JPS61114571A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61114571A JPS61114571A JP23605184A JP23605184A JPS61114571A JP S61114571 A JPS61114571 A JP S61114571A JP 23605184 A JP23605184 A JP 23605184A JP 23605184 A JP23605184 A JP 23605184A JP S61114571 A JPS61114571 A JP S61114571A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- buried
- arsenic
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000470 constituent Substances 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052785 arsenic Inorganic materials 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 238000000926 separation method Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 3
- 238000002513 implantation Methods 0.000 abstract 2
- 230000003213 activating effect Effects 0.000 abstract 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 abstract 1
- 238000010276 construction Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005260 alpha ray Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical group [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体基板内(埋込み導を層を設けるバイポー
ラ集積回路の製造方法に関し、詳しくは、酸素イオンを
深く注入することにより基鈑内部に酸化膜な形成する技
術をバイポーラICの製造工に
程に適用して埋没層下の基板鴨埋込み絶縁層を形成し、
バイボー2素子のS OI (5illeon 0nI
ns++Iator ) !’II造を簡便にかつ安定
した結晶性で得ろ方法を提供するものであるう
〔従来の技術〕
半導体集積回路において基板−素子間あるいは配線−基
板間容量の低減及び耐α線ソフトエラー強度増大をはか
るためにSt基板と直接接触する部分をもたないSOI
や同様の目的を達成するための8OS (Sllico
n On 5apphire)の構造が −注目されて
いる。SOI構造を実現する手段として醸化膜上の多結
晶シリコンt!!−単結晶化するレーザアニール技術や
基板中にNl素原子をイオン注入して熱処理を行5こと
で絶縁層を形成するSIMOX (Separatio
n by Implanted Ox)’gen)技術
があり、盛んに検討されている。このSIMOX技術(
おいてはレーザーアニールで形成したSOI撰造よりも
良好な特性を示すバイポーラ素子の試作例が報告されて
いる。アイイーイーイーエレクトロンデバイスレターズ
頁9L〜93、第5巻、七3.3月、1984年「パー
ティカル稍−p−nバイポーラトランジスタ・7アプリ
ケイテイド・オン・ベリット・オキサイドS OI J
(IEEEELECTRON DEVrCE LETT
ER8%p、91−93、VOL、EDL−5,NO,
3,MARCH1984:VertlcmI n −p
−n Blpolar Transistors F
abricated on Buried 0xi
de 5ol)〔発明が解決しようとする問題点〕
SO8は27フイア基板とシリコンエピタキシャル層間
の格子不適合(よる電流漏れ増大及び電荷移動度の低下
、サファイア基板のコスト高という欠点がある。一方し
−ザアニール技術ニよルsO■の場合では安定した単結
晶SOIを得ることができず、バイポーラ素子ではまだ
良好な特性を示す実施例に報告されていない。またSI
MOX技術(おける上記試作例では埋没層がないため、
コレクタの直列抵抗を低くできないという欠点が存在す
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing bipolar integrated circuits in which a layer of buried conductors is provided in a semiconductor substrate. Applying oxide film formation technology to the manufacturing process of bipolar ICs, a buried insulating layer is formed under the buried layer,
Bibo 2-element S OI (5illeon 0nI
ns++Iator)! [Prior art] To provide a method for easily obtaining an II structure with stable crystallinity. [Prior art] Reducing the capacitance between a substrate and an element or between a wiring and a substrate and increasing the resistance to α-ray soft errors in a semiconductor integrated circuit. SOI that does not have a part that comes into direct contact with the St substrate to measure
8OS (Sllico
The structure of n On 5apphire is attracting attention. As a means to realize the SOI structure, polycrystalline silicon t! ! - SIMOX (Separation), which forms an insulating layer by laser annealing technology for single crystallization, ion implantation of Nl atoms into the substrate, and heat treatment5.
n by Implanted Ox)'gen) technology, which is being actively studied. This SIMOX technology (
In recent years, prototype bipolar devices have been reported that exhibit better characteristics than SOI devices formed by laser annealing. IE Electron Device Letters, pp. 9L-93, Volume 5, March 7, 1984 "Particle-pn Bipolar Transistor 7 Applications on Verit Oxide S OI J
(IEEEELECTRON DEVrCE LETT
ER8%p, 91-93, VOL, EDL-5, NO,
3, MARCH1984: VertlcmI n-p
-n Blpolar Transistors F
ascribed on Buried 0xi
[Problems to be Solved by the Invention] SO8 has drawbacks such as increased current leakage and decreased charge mobility due to lattice mismatch between the 27F substrate and the silicon epitaxial layer, and high cost of the sapphire substrate. In the case of the annealing technology, it is not possible to obtain a stable single-crystal SOI, and no examples have been reported showing good characteristics in bipolar devices.
MOX technology (in the above prototype example, there is no buried layer, so
The drawback is that the series resistance of the collector cannot be lowered.
本発明ではSIMOX技術によるsor!li造を利用
することでsorm造でありながらも容易く安定した結
晶状態を得、しかもコレクタの直列抵抗を低くできるバ
イポーラ素子を実現することを目的とする。In the present invention, the sor! The object of the present invention is to realize a bipolar element that can easily obtain a stable crystalline state even though it is a sorm structure by utilizing the lithium structure, and can also reduce the series resistance of the collector.
本発明では半導体基板中へ導電型を与える不純物原子及
び基板構成原子と結合して絶縁物を形成できる原子をイ
オン注入し、熱処理を施することにより低抵抗導電層を
形成すると同時に埋込み絶縁層を形成することによって
なされる。In the present invention, impurity atoms that provide a conductivity type and atoms that can combine with substrate constituent atoms to form an insulator are ion-implanted into a semiconductor substrate, and heat treatment is performed to form a low-resistance conductive layer and at the same time to form a buried insulating layer. It is done by forming.
以下第1図〜第4図の基板断面図を参照して実施例を説
明する。Embodiments will be described below with reference to substrate sectional views shown in FIGS. 1 to 4.
第1図ではP型のSi基板11へ酸素(0)を400
K e V、 lxl 0 ”cx−”以上でイオン注
入し、次いで砒素(As)を60〜70Ke¥、IX
10”cm−”にイオン注入する。In FIG. 1, 400% of oxygen (0) is applied to a P-type Si substrate 11.
Ion implantation is performed at K e V, lxl 0 "cx-" or higher, and then arsenic (As) is implanted at 60 to 70 Ke\, IX
Ion implantation is performed at a depth of 10"cm-".
このとき散票原子は0.5〜1.0μm砒素原子は表面
から0.5μm程度の深さに分布する。注入イオンは砒
素のかわりにN型の不純物、たとえばリン(P)やアン
チモン(Sb)等でもよい。注入の順序は任意でよく、
物質ごとに加速電圧とイオン注入量を制御する。At this time, the scattered atoms are distributed at a depth of 0.5 to 1.0 μm, and the arsenic atoms are distributed at a depth of about 0.5 μm from the surface. Instead of arsenic, the implanted ions may be N-type impurities such as phosphorus (P) or antimony (Sb). The order of injection can be arbitrary;
The acceleration voltage and ion implantation amount are controlled for each substance.
vKz図ではイオン注入を行った基板に1150℃で2
時間の熱処理を施して前工程で注入した酸素イオンによ
り該酸素注入領域に絶縁層となる二酸化シリ=r y
(S 101)層(あるいは5iOxN)12を形成し
埋込み絶縁層とすると同時に砒素注入領域では砒素原子
を活性化して、イオン注入で発生した結晶欠陥密度を少
くとも1lla!/−以下に回復し、埋込層となる層1
3を形成する。In the vKz diagram, 2
Silicon dioxide = r y which becomes an insulating layer in the oxygen implanted region by the oxygen ions implanted in the previous process after being subjected to heat treatment for several hours.
(S 101) layer (or 5iOxN) 12 is formed as a buried insulating layer, and at the same time, arsenic atoms are activated in the arsenic implanted region to reduce the crystal defect density generated by ion implantation to at least 1lla! Layer 1 recovers to below /- and becomes a buried layer
form 3.
第3図では該基板上にn のエピタキシャル層14を成
長する。In FIG. 3, an n 2 epitaxial layer 14 is grown on the substrate.
第4図では該エピタキシャル層14の素子分離となる領
域に埋込み酸化膜層に到達するU字状の溝を異方性ドラ
イエツチングで形成した後、診溝を酸化膜及びポリシリ
コンで充填し素子分離領域を完成する。In FIG. 4, a U-shaped trench reaching the buried oxide film layer is formed in the region of the epitaxial layer 14 for device isolation by anisotropic dry etching, and then the diagnostic trench is filled with an oxide film and polysilicon to form the device. Complete the isolation area.
以降、通常のバイポーラ素子形成工程に従ってコレクタ
リーチスルー領域、ペース、エミッタ領埒
域等や形成する。Thereafter, a collector reach-through region, a paste, an emitter region, etc. are formed according to a normal bipolar element forming process.
以上説明したように本発明によれば、結晶性の優れたS
OI構造をコレクタ埋没層が存在するバイポーラ素子に
適用できるので、コレクタ抵抗値を低く保ちながら、基
板−配線間あるいは基W−素子間の宥生容量を少なくで
き、しかも耐α線ソフトエラー強度の大きなバイポーラ
集積回路を製造することが可能となる。As explained above, according to the present invention, S with excellent crystallinity
Since the OI structure can be applied to bipolar devices with a buried collector layer, it is possible to reduce the capacitance between the substrate and wiring or between the base W and the device while keeping the collector resistance low, and to improve the resistance to α-ray soft errors. It becomes possible to manufacture large bipolar integrated circuits.
第1図〜第4図は本発明の実施例における各工程の基板
断面図を表す。
11・・・・・・P型シリコン基板、12・・・・・埋
込み絶縁層、13・・・・・・埋込み層、14・・・・
・エピタキシャル層、15・・・・・・二酸化シリコン
膜。
第1図
番 ÷ ◆ φ ↓ (
↓ ↓ ↓ ↓
築2図
第3図
第4 図
手続補正書(方式)
%式%
昭和5r年特許願第λ3Gらs(号
3、 Ti1l正をすると
’IG)’l−との関(I 持詐出願人住所
神奈用県11陣?市中1t;flx: Iニー1−11
1中10151fr地(522)名称富士通株式会社1 to 4 represent cross-sectional views of the substrate at each step in the embodiment of the present invention. 11...P-type silicon substrate, 12...buried insulating layer, 13...buried layer, 14...
-Epitaxial layer, 15...Silicon dioxide film. Figure 1 number ÷ ◆ φ ↓ ( ↓ ↓ ↓ ↓ Building 2 Figure 3 Figure 4 Figure procedure amendment (method) % formula % 1932 patent application No. λ3G et al. )'l- Relationship with (I Fraudulent applicant's address
Kanayo Prefecture 11 teams? City 1t; flx: I knee 1-11
10151fr land (522) Name Fujitsu Limited
Claims (1)
構成原子と結合して絶縁物を形成できる原子をイオン注
入し、熱処理を施すことにより低抵抗導電層を形成する
と同時に埋込み絶縁層を形成することを特徴とする半導
体装置の製造方法。Forming a low-resistance conductive layer and a buried insulating layer at the same time by ion-implanting impurity atoms that give a conductivity type and atoms that can combine with substrate constituent atoms to form an insulator into a semiconductor substrate and performing heat treatment. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23605184A JPS61114571A (en) | 1984-11-09 | 1984-11-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23605184A JPS61114571A (en) | 1984-11-09 | 1984-11-09 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61114571A true JPS61114571A (en) | 1986-06-02 |
Family
ID=16995017
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23605184A Pending JPS61114571A (en) | 1984-11-09 | 1984-11-09 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61114571A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6336566A (en) * | 1986-07-31 | 1988-02-17 | Hitachi Ltd | Semiconductor device |
JPS649657A (en) * | 1987-07-01 | 1989-01-12 | Nec Corp | Junction transistor |
JPS6480075A (en) * | 1987-09-21 | 1989-03-24 | Nec Corp | Bipolar type integrated circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54109761A (en) * | 1978-02-17 | 1979-08-28 | Toshiba Corp | Manufacture of semiconductor device |
-
1984
- 1984-11-09 JP JP23605184A patent/JPS61114571A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54109761A (en) * | 1978-02-17 | 1979-08-28 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6336566A (en) * | 1986-07-31 | 1988-02-17 | Hitachi Ltd | Semiconductor device |
JPS649657A (en) * | 1987-07-01 | 1989-01-12 | Nec Corp | Junction transistor |
JPS6480075A (en) * | 1987-09-21 | 1989-03-24 | Nec Corp | Bipolar type integrated circuit |
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