JPS61114325A - Timing signal controller - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and also to make fine adjustment of timing easy by producing different timing signals through a charging/ discharging circuit, switching circuit and a HALT state detecting circuit. CONSTITUTION:When a CPU10 is started, a control signal is delivered through an input terminal and a short circuit is secured at a switching circuit between terminals 120 and 130 of resistances 12 and 13 and the VDD respectively. Thus the potential of a terminal 110 rises up, and an originating control signal 101 and a reset signal 102 are supplied to an oscillation control circuit 3 and a reset circuit 4 of the CPU10 with the timing as shown in the figure. Thus the CPU10 is always started. When the working of the CPU10 is stopped, a short circuit is secured by the circuit 15 between terminals 120 and 130 of resistances R1 and R2 and the VSS respectively. However, the signal is switched only when the CPU10 is set under a HALT state since an AND gate 2 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a timing signal control device for controlling a CPU.

[Prior art]

Conventionally, in a CPU that controls the oscillation circuit, the internal clock control circuit, and the on/off state of the oscillation circuit using an external signal asynchronously with the internal clock, these external signals are controlled at the timing described below. There is a need.

That is, as shown in FIG. 2, first, the oscillation control signal 101 is activated ( ) 1 IREPEL) IC to start oscillation.

The oscillation signal 105 takes Ict seconds to stabilize.

After that, the reset signal is sensed at the n3rd gate of the internal clock. Also, after the IJ set signal is sensed as active (low), all internal circuits and control outputs of CplL are initialized. Furthermore,
When the reset means becomes inactive ( ), level), the instruction fetch cycle starts from the n2th internal edge.

Therefore, let us consider the control of 6'pu, as shown in Figure 5)K
The output signal 4 from the 1-oscillation suppression control angle control circuit 32 causes a delay time of 1lIIIl1 times #+35, and a delay of t1 seconds within the delay time O# y town start delay, n! The delay time of the start is counted, and a control signal is outputted to 34 reset signal control circuits 34 at each timing h, and a reset signal is generated at these delay timings and inputted to the reset circuit M4 of cpwlo.

On the other hand, when stopping 6pu, the method is (1) c
Stop the power supply to PLL.

(2) Stop the CPU program λ.

(3) Suspend the supply of black yak.

There are 03 methods.

(1) When things are busy, one option is to use a switching circuit that turns on and off the power to the CPU, as shown in Figure 4.

(2) With Ic, instead of continuing to supply power, CT%
There is a method to HALT the inside. Specific 1c
By executing a 1 (ALT instruction) inside H1cp1L, the program is stopped and the NOP instruction and refresh operation are repeated.

Regarding (3), there is a method of continuing to supply power, but not only stopping the program, but also stopping the internal clock, and stopping the oscillation itself using an external control signal. However, in this case, since the internal clock and the oscillation control circuit are asynchronous, be sure to execute the HALT command inside the cplL to ensure that all the clocks are in the HALT state), and then stop the internal clock. , it is necessary to stop the oscillation circuit. Also, at this time, the reset signal always maintains the non-agutiz state and is not reset again before one oscillation stops.

Specifically) C is VcHAL as shown in FIG. A delay time control circuit 54 counts the delay time from the fall of the state detection circuit 51 signal, the oscillation control signal, and the oscillation control signal. Further, after the oscillation is completely stopped by the output signal from the delay time control circuit, the reset signal control circuit makes the reset signal ( ) 1 active again.

[Problems that the invention aims to solve]

However, among the conventional techniques mentioned above, five methods for stopping cplL were listed.

(1) Regarding K, if the CPU has internal RAM, its contents will be completely erased. Furthermore, when a transistor is used for switching the power supply, when operating at 69%, there is an open end point when the supply voltage decreases.

(2) As for the IC, as for the CPU control circuit, all (although no load is applied, it always supplies cpuVc voltage, and current continues to flow even though the CPU operation has stopped). There is a problem.

Regarding (5), both the internal clock and the oscillation circuit are stopped, the current value can be reduced to almost zero, and the control outputs of each data bus etc. continue to maintain their last state because they are equipped with a hold circuit. However, there is a problem that the circuit configuration is complicated as shown in Figure @5, and the control itself is also complicated.

This method has the problem that the control of the timing signal at the start of the CPU operation is complicated, and both the circuit configuration and control become complicated.

Furthermore, if the frequency of the cplL is changed and the oscillation variation of the vibrator itself is taken into consideration, there is a problem in that it becomes difficult to finely adjust the delay time of the timing signal.

[Means for solving problems]

The timing signal control device of the present invention includes at least an oscillation means, an internal clock control means, an on/off control means capable of controlling the oscillation means asynchronously with an internal clock, and an internal clock and an external clock. Controls the CPU, which has a reset means that initializes internal circuits and control outputs, etc. in synchronization with signals from the oscillation control signal and the reset signal. Discharging means, switching means for turning it on and off according to one control signal, and cpuL:
1') Features [Function] characterized by having means for detecting a HALT state Since the present invention has the above configuration, as shown in FIG.
When C'n1L is in operation, the timing of the oscillation control signal and the reset signal is created by the CR time constant determined by the capacitor 11 and the resistor 12 by the operation of the # button of the switching circuit. (j7) When stopping u, change the switching means, check the car in which the CPU is in the HALT state by the signal from the HALT state detection means, and then connect the capacitor 11 and the resistor 12.1! An oscillation control signal and a reset signal are output to the CPU according to a fixed number of ORs determined by SK.

〔Example〕

The present invention will be described in detail below based on examples.

FIG. 1 is a block diagram of a system using the timing signal control device of the present invention.

When starting cplLlo, a control signal is output from the input terminal 90, and the switching circuit 15 connects the resistor 1.
2.13 terminal 120. 130 with yon.

- make it hit. First of all, activate the auxiliary circuit by 7ri. On the other hand, the potential of the terminal 110 is determined by the capacitance of the capacitor 11 being CI, the resistor 12. Let the resistance value of i3 be R, ,
R, then the signal will rise with a time delay of Δt = -R, cl tog (1-v*7p-) ((2) potential of terminal 110, E is potential difference of 711-VDD). Therefore, R in advance
Let the value of ,,0, be Vtrue! V? h L , Δ1>1.・・・・・・・・・
...(1st formula) vs xV? h I, he<!
1+? J XT..."...C2nd formula) (However, V
? 11 L, V? h M is the logic qfV level of Cps, and the potential or T for determining the input signal low, ) and a, respectively.
is the period of the internal clock) Set to a value that satisfies the condition of formula 02.

As a result, the oscillation control circuit 3 and reset circuit 4 of the CPU receive the oscillation control signal 10 at the timing shown in FIG.
1 and the quirk signal 102 are supplied and the normal VCc g
You can start w.

On the other hand, when cput is stopped, the switching circuit 15VC connects the terminals 120130 of the resistors R, , R,
can be abbreviated as yss. However, switching circuit 1
Since the output of 5 and the output of +HALT state detection circuit 51 are ANDed, the large signal when cpulo is in the H4LT state changes.

Terminal 120. When 130 is set to 7am, terminal 1
The potential (vs) of 20 drops to the 1st position determined by R1 and R1. That is, vs 2 Ry'R1+ R1K.

On the other hand, the potential (VR) of the terminal 110 is
The electric charge q0 stored in the capacitance q0 is changed by a discharge curve determined by the capacitance C1 and the resistance value R1R2.

Therefore, R, gold vs = R, /(R, +R,)XI<vτhL −・
・・・−(3rd formula) Δtx=−(R1+R,)c l
l-1a (1-v v-ti/w)>φ・−・−(
4th formula) If we define the 02 formula as 2L72 and 51C, then c
After pu enters the HALT state, the oscillation circuit is reliably stopped, and the reset signal remains inactive during that time.

FIG. 6 is a system diagram of an embodiment based on the present invention. The control c1w17 receives and receives data via the 6pu10 and the data bus 61.

Control cpw17, constant transistor 161
A C high level signal 160 is output. CpvAO
When operating the transistor 16, the output 160 is set to low level to turn on the transistor 16.

At this time, terminal 120. As shown in FIG.
.

XT) reaches a high level with a delay of seconds. At this time, the cpU starts oscillation, initializes the internal circuit and control output, and
Start the 7th etch of the program written in CROM18K.

On the other hand, the CPU stops the program and the HALT state IMV
c, data from cpulo indicating that it is in the HALT state (for example, a 4-bit code signal)
cpwTic for control via data bus 61
Output. Control C7) The received code is detected by the HALT state detection circuit 51, and the output signal to the transistor 16 is set to high level again. At this time, the transistor 16 is cut off, and the capacitor 11 is connected to the resistor R+12. By the discharge circuit consisting of Rt13, the terminals 120 and 110 first go to low level and stop the first oscillation at the timing shown in FIG. 7, and then Δt! =-(R4+R2) JtO(J (I E
-Vi/R) delay y! At PIVl, the potential of the terminal 110 goes to low level KfK.

It should be noted that the nine embodiments listed here are just one embodiment.

〔Effect of the invention〕

As described above, according to the present invention, the start of the operation of the CPU,
Since the different timing signals for stopping are configured by one charging/discharging circuit, a switching circuit, and an H-in LT type tII detection circuit, the circuit configuration is simplified.

Moreover, the control signals for these component circuits are extremely simple, as they only require turning on and off the charging and discharging circuits.

Furthermore, even if the oscillation frequency bζ of VC, c't'ru changes or the vibrator varies, fine adjustment can be effected by simply changing the capacitance of the resistor and capacitor.

[Brief explanation of drawings]

Il! Fig. 1 is a diagram clearly showing the configuration of the present invention, Fig. 2 is a timing diagram related to the VC of the present invention, Figs. 3 to 5 are diagrams showing the prior art, and Fig. 6 is a diagram of an embodiment of the present invention. , FIG. 7 is a timing signal diagram in the embodiment. 1°... Input terminal 2... Gate circuit 3... Oscillation control circuit 4... Reset circuit 5... Oscillation circuit 6... ... Gate circuit 7 ... Oscillation resistor 8 ... Vibrator 9 ... Oscillation capacitor 10 ... River CPU 11 ... Capacitor 12.13 ... ... Resistor 51, music, HALT state detection circuit and above Izuhara Suwa Seikosha Co., Ltd. Figure 1 1121! 1 1J3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] An oscillation control signal (cp
The capacitor is charged in a signal control device that generates a reset signal (controls the CPU's oscillation means) and a reset signal (controls the CPU's reset means), and enables the CPU to asynchronously control the oscillation of its internal clock. The discharging means, the switching means that turns it on and off using a single control signal, and the CPU are in a stopped state (a state in which the internal logic continues to maintain a certain state by stopping the supply of internal clocks. Hereinafter referred to as "HALT") 1. A timing signal control device characterized by having means for detecting that a state is in a state (referred to as a "state").