JPH0553693A - Reset circuit for information terminal equipment or the like - Google Patents

Abstract

PURPOSE:To provide the similar operation function to the hardware structure as the conventional one in the reset circuit for information terminal equipment or the like. CONSTITUTION:A capacitor 11 of a charge/discharge circuit inputting a CONT signal from a power supply ON/OFF control circuit 3 is charged and discharged. The charged and discharged voltage is applied to a Schmitt input inverter 12 as a first RESET signal 13, resetting and setting a CPU circuit 5. The rise and fall of the applied voltage Vcc to the CPU circuit is controlled to keep the contents of the RAM and a clock chip or the like of the CPU circuit at that time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit (hereinafter,
The present invention relates to a reset circuit for an information terminal device using a CPU.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional reset circuit for an information terminal of this type. In FIG. 1, 1 is a power supply for outputting a power supply voltage V _DD (5 V as an example), and 2 is a power supply 1. Power switch to turn ON / OFF, 3 is HIGH / LOW
Power ON / OFF to output the count signal (CONT)
A control circuit, 4 is a power supply switching circuit whose operation is controlled by the CONT signal, 5 is a CPU circuit incorporated in an information terminal device, V _CC is a voltage applied to the CPU circuit, 6 is a capacitor, and 7 is a reference. A power source 8 is a reference voltage V _DD from the reference power source and a voltage V _CC applied to the CPU circuit 5.
An operational amplifier for comparing and detecting the input signal 9 is input to the detection output of the operational amplifier, and is reset to the CPU circuit 5 (RESE).
T) A falling delay circuit which receives the signal 10 and resets it.

The operation of the hardware reset circuit configured as described above will be described below.

First, the power switch 2 is turned off as shown in the figure.
When the power source 1 is turned off, the CONT signal of the power source ON / OFF control circuit 3 is LOW, no power is supplied to the CPU circuit 5 by the power source switching circuit 4, and the applied voltage V _CC is zero V. ..

Therefore, as the detection output of the operational amplifier 8, the reference voltage V _DD of the reference power source 7 is input to the falling delay circuit 9, so that the RESET signal 10 is momentarily HIGH.
Then, the CPU circuit 5 is reset.

Next, the power switch O is turned on by turning on the power switch 2.
In the N state, C of the power ON / OFF control circuit 3
The ONT signal is HIGH, and the power source switching circuit 4 causes C
Power is supplied to the PU circuit 5 and a predetermined applied voltage V _CC is applied. At this time, the operational amplifier 8 performs comparison detection between the applied voltage V _CC and the reference voltage V _DD, and after the applied voltage V _CC , that is, the voltage of the power supply 1 reaches the reference voltage V _DD , the voltage stabilizes after a while. Then, the RESET signal 10 from the falling delay circuit 9 becomes LOW, and the reset of the CPU circuit 5 is released.

As described above, when the power supply 1 is turned off, the RESET signal instantly becomes HIGH and the CPU circuit is reset. That is, by resetting the CPU circuit within a time period in which a voltage is required for the CPU circuit to operate normally, the contents of the RAM, clock chip, etc. in the circuit can be retained.

[0008]

However, the above-mentioned conventional configuration has a problem that the price becomes high because the operational amplifier 8 and the delay circuit 9 are used.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a hardware reset circuit that can obtain the same effect at a lower cost.

[0010]

SUMMARY OF THE INVENTION The present invention is to turn on / off a power supply.
When the count signal is set to HIGH / LOW depending on the OFF state, the power supply ON / OFF control circuit, the power supply switching circuit for controlling the power supply to the CPU circuit by the count signal HIGH / LOW, and the count signal HIGH / LOW A charging / discharging circuit for charging / discharging; and a Schmitt input type inverter for inputting an output of the charging / discharging circuit as a first reset signal and outputting a second reset signal for the CPU circuit. To do.

[0011]

According to the structure of the present invention, the same operation as the conventional one can be performed by the inexpensive charging element, the resistors for controlling the charging start of the charging element, the diode elements, and the Schmitt input type inverter.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a circuit configuration of an embodiment of the present invention. In FIG. 1, 11 is a charge / discharge capacitor for generating a first reset (RESET) signal 13, and 12 is a first RE.
Schmitt input type inverters D1 and D that receive the SET signal and generate the second reset (RESET) signal 14.
2 is a diode and R1 to R3 are resistors, where R
1 is for D1 protection, R2 is a CR constant with the capacitor 11, and creates a time for delaying the rising of the first RESET signal 13. In addition, the same reference numerals as those in FIG. 3 indicate the same elements, and the description thereof will be omitted.

Here, the capacitor (1 μF) of the charging / discharging circuit
One end of 11 has a series circuit of a diode D1 and a resistor R1 (1 kΩ), a diode D2 to which an applied voltage V _CC is applied, and a resistor R1.
It is connected to a connection point P with a parallel circuit of 2 (100 kΩ), and the other end of the capacitor 11 is grounded.

Further, one end of the Schmitt input type inverter protection resistor R3 (100 kΩ) is connected to the connection point P, and the other end of the resistor R3 is connected to the input end of the Schmitt input type inverter 12. This R3 may be deleted if necessary.

Further, the state of the second RESET signal 14 is controlled by the first RESET signal 13 obtained by the charge / discharge circuit using the CONT signal as an input.

The operation of the reset circuit of the information terminal equipment configured as described above will be described with reference to the signal switching timing chart shown in FIG.

When the power supply 1 with the power switch 2 in FIG. 1 opened is OFF ((1) in FIG. 2), the CONT signal from the power ON / OFF control circuit 3 is LOW, and the power supply switching circuit 4 causes the CPU to operate. The circuit 5 is not supplied with power and the applied voltage V _CC is zero V ((2) in FIG. 2). And
The charging circuit of the capacitor 11 is not formed by the LOW of the CONT signal, the charge of the capacitor 11 is discharged, and the first RESET signal 13 remains LOW ((3) in FIG. 3). 2nd RES from 12
The ET signal 14 becomes HIGH ((4) in FIG. 2), and the CPU circuit 5 is reset.

Next, when the power switch 2 is closed, the power source 1
Is turned on and the CONT signal becomes HIGH by the power ON / OFF control circuit 3, whereby the applied voltage V _CC is applied to the CPU circuit 5 by the power switching circuit 4.

The applied voltage V _CC gradually rises as shown in (2) of FIG. 2, and at the same time, since the CONT signal is HIGH, the capacitor 11 is charged through the diode D1 and the resistor R1. Also applied voltage V _CC of this charge to the diode D1 and resistor R2 began rising in the relaxed or as shown in (2) in FIG. 2, approximately from applied voltage V _CC reaches the specified voltage 5V 80 ms (D1, R1 Time constant) after V _CC
When the charging voltage of the capacitor 11 reaches the midpoint 2.5V, the first
RESET signal 13 becomes HIGH, and the Schmitt input type inverter 12 causes the second RESET signal 14 to go LOW.
(4) in FIG. 2, the CPU circuit 5 is reset, and power (applied voltage V _CC ... (2) in FIG. 2) is supplied to the CPU circuit.

In this way, the voltage V applied to the CPU circuit 5 is
800 ms after _CC reaches the specified voltage of 5 V, V _CC is already
Is stable, the operation of the CPU circuit 5 is guaranteed, and CP
The contents of the RAM and clock chip in the U circuit are retained.

Next, when the power switch 2 is turned off, the power source O
The CONT signal from the N / OFF control circuit 3 is L
It becomes OW, the capacitor 11 has a resistor R1, a diode D1
The first RESET in an instant by discharging through
The signal 13 falls as shown in (3) of FIG. 2 and 1.5 ms after the power switch 2 is turned off ((1) of FIG. 2), the applied voltage V _CC to the CPU circuit 5 drops to 2.5V. And the second RESET signal 14 is set to H by the Schmitt input type inverter 12.
It is set to IGH ((4) in FIG. 2) and the CPU circuit 5 is reset.

As described above, the CPU circuit falls while the applied voltage V _CC is a voltage that can guarantee the operation of the CPU circuit 5, whereby the contents of the RAM, the clock chip and the like in the CPU circuit are held. Then, after a while after the CPU circuit is reset, V _CC safely falls to zero V as shown in (2) of FIG.

[0023]

As described above, the reset circuit of the information terminal device or the like of the present invention is a capacitor of a charge / discharge circuit which is composed of an inexpensive element by the HIGH / LOW of the CONT signal from the power ON / OFF control circuit. By charging / discharging 11, the CPU circuit can be set / reset by the similarly inexpensive Schmidt input type inverter.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention.

FIG. 2 is a signal switching timing chart for explaining the operation of FIG.

FIG. 3 is a diagram showing an example of a reset circuit of a conventional information terminal device.

[Explanation of symbols]

1 ... Power supply, 2 ... Power switch, 3 ... Power ON / OF
F control circuit, 4 ... power supply switching circuit, 5 ... CPU
Circuit, 6, 11 ... Capacitor, 12 ... Schmidt input type inverter, 13 ... First RESET signal, 14 ... Second
RESET signal, D1, D2 ... Diode, R
1, R2, R3 ... Resistance.

Claims (1)

[Claims] 1. A power ON / OFF control circuit and a HIGH / LOW count signal when the count signal is set to HIGH / LOW depending on the ON / OFF state of the power supply.
A power supply switching circuit for switching control of power supply to the CPU circuit, a charging / discharging circuit for charging / discharging according to HIGH / LOW of the count signal, and an output of the charging / discharging circuit as a first reset signal, A reset circuit for an information terminal device or the like, comprising: a Schmitt input type inverter that outputs a second reset signal to the CPU circuit.