JPH05136672A - Power-on reset circuit - Google Patents

Abstract

PURPOSE:To attain sure power-on reset by not implementing charging till a power supply voltage reaches a prescribed value. CONSTITUTION:A voltage divided voltage of a voltage division circuit 10 is suppressed to a level not turning on a switching element 11 even when a current is supplied from a circuit of other system. At application of power supply voltage Vcc of its own system, a voltage division voltage of the circuit 10 turns on the element 11, a charge/discharge circuit 12 is charged and when the charging potential reaches a prescribed level, a waveform shaping circuit 13 outputs a reset pulse. Thus, the disable state of power-on reset by a bypassed current from another system circuit is avoided and sure power-on reset is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit for initializing the circuit when the power supply voltage is turned on.

[0002]

2. Description of the Related Art In various digital circuits, resetting for circuit initialization is performed by a power-on reset signal created when the power is turned on. FIG. 7 is a diagram showing an example of a conventional power-on reset circuit, and shows two types, (a) and (b).

In FIG. 1A, a series circuit of a resistor R1 and a capacitor C1 is connected between a power source V _CC and ground to form a charge / discharge circuit. This resistor R1 and capacitor C
The potential at the connection point 1 is connected to the waveform shaping circuit U1. Then, the power-on reset signal _VRST is output from the waveform shaping circuit U1.

On the other hand, in the circuit shown in (b), a charging / discharging circuit is constituted by a series circuit of resistors R2 and R3 and a capacitor C2 connected between the connection point of these resistors R2 and R3 and the ground. There is. The other circuits are the same as in (a).

The operation of the circuit (a) thus constructed will be described with reference to the operation waveforms of FIG. Now, it is assumed that the power supply voltage V _CC has risen as shown in (a). As a result, the charge / discharge circuit of the resistor R1 and the capacitor C1 is gradually charged by the power supply voltage V _CC . As a result, the potential V _{CR at} the connection point between the resistor R1 and the capacitor C1 was gradually changed to the time constant R1 · C1 (the identification symbol was used as the value of the resistor R1 and the capacitor C1 as it is as shown in (b)).
The same applies hereinafter).

Here, the value of the potential V _CR is the waveform shaping circuit U.
When the trigger level of 1 is reached, the waveform shaping circuit U1 outputs a reset pulse _VRST as shown in (c). The time Δt from the rise of the power supply voltage V _CC to the rise of the reset pulse V _RST is the reset time. By setting this Δt to an appropriate value, the circuit can be reset (initialized).

The operation of the circuit shown in FIG. 6B is the same as that of FIG. The difference from the circuit shown in (a) is that the potential when the capacitor C2 is completely charged becomes the divided potential of the resistors R2 and R3.

[0008]

Now, let us consider a system as shown in FIG. The same parts as those in FIG. 7 are designated by the same reference numerals. The circuit 1 and the circuit 2 are connected by the signal line 1. That is, the signal output from the ICU 2 in the circuit 1 is transmitted to the circuit 2 side via the signal line 1. On the circuit 2 side, the signal from the ICU 2 is received by the ICU 3 and buffered, and then notified to the microprocessor (μP) 2.

The reset input R of the microprocessor 2 receives a reset signal from the power-on reset circuit 3. That is, the microprocessor 2 is initialized by the reset signal from the power-on reset circuit 3. Circuit 1 is power supply voltage V
It operates on _CC1 , and the circuit 2 operates on the power supply voltage V _CC2 .

In the circuit thus constructed, the power supplies of both circuits are turned on at the same time, and the power supply V of the circuit 2 is increased.
It is assumed that _CC2 starts up slightly later. As a result, a current flows from the ICU 2 of the circuit 1 in the direction indicated by the thick solid line in the figure. That is, ICU2 → resistor R4 → power supply V
_A current flows through the route of _CC2 → resistor R1 → capacitor C1 and the capacitor C1 is charged.

Therefore, if the _{divided potential} V _CR has already reached the "1" level of the waveform shaping circuit U1 at the time when the power source V _CC2 on the circuit 2 side rises normally, the power-on reset signal is generated. Occurs, the microprocessor 2 is not initialized, and normal operation of the microprocessor 2 cannot be expected.

Such a problem also occurs when the printed circuit board is inserted while the power supply of the entire system is on even when the power supply is common.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a power-on reset circuit capable of surely performing a power-on reset.

[0014]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 10 is a voltage dividing circuit for dividing the power supply voltage V _CC , 11 is a switching element that receives the output of the voltage dividing circuit 10 and performs a switching operation, 12 is a charging / discharging circuit connected to the switching element 11, A waveform shaping circuit 13 receives the output of the charge / discharge circuit 12, shapes the waveform, and outputs a reset pulse.

[0015]

The divided voltage of the voltage dividing circuit 10 can be suppressed to a level at which the switching element 11 cannot be turned on even when a current flows from a circuit of another system. Next, when the power supply voltage V _CC of the own system is turned on, the divided voltage of the voltage dividing circuit 10 turns on the switching element 11. When the switching element 11 is turned on, the charge / discharge circuit 12 is charged, and when the charge potential reaches a predetermined level, the waveform shaping circuit 13 outputs a reset pulse. With such a configuration, it is possible to eliminate the inconvenience that the power-on reset cannot be performed due to the current sneak from the circuit of the other system, and the power-on reset can be surely performed.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. The voltage dividing circuit 10 is composed of a series circuit of resistors R6 and R7. The potential V _{TR at} the connection point between the resistors R6 and R7 is connected to the base of the transistor 11 as a switching element. Here, the divided voltage by the resistors R6 and R7 is selected as a value that does not turn on the transistor 11 due to the power supply sneak current from another system, and the resistance values of R6 and R7 also satisfy this condition. Is set.

The charge / discharge circuit 12 is composed of a series circuit of a resistor R8 and a capacitor C4. Then, the potential V _{CR at} the connection point of the resistor R8 and the capacitor C4 becomes the waveform shaping circuit 1
It is supposed to enter 3. The waveform shaping circuit 13 operates at the level, and for example, a Schmitt trigger circuit is used.
In general, such a Schmitt trigger circuit can be used as a commercially available IC. The operation of the circuit thus configured will be described below with reference to the operation waveform diagram of FIG.

First, as shown in (a), the power supply voltage V _CC
Is turned on at time, the divided potential V _TR of the voltage dividing circuit of the resistors R6 and R7 rises as shown in (b). When the _{V TR} rises to a level that turns on the transistor 11 (e.g. 0.7 V), the transistor 11 as shown in at that time (c) is turned on.

On the other hand, the divided potential V of the charge / discharge circuit 12
_CR is the power supply voltage V _CC rises gradually as shown in the turned on (d). In response to this, the output V _RST of the waveform shaping circuit 13 also rises.

However, at the time, the transistor 11
When is turned on, the potential V _CR is discharged at once and becomes a value close to 0 as shown in the figure. As a result, the output of the waveform shaping circuit 13 which receives this potential is turned off and becomes "0" as shown in (e).

After that, the capacitor C4 is charged with a charge with a time constant determined by R8 × C4. At this time, the divided potential V _CR of the charge / discharge circuit 12 also rises as shown in (d). Then, when the level of this potential V _CR reaches a certain value, the waveform shaping circuit 13 is turned on at that time as shown in (e). Output V of this waveform shaping circuit 13
The period during (and between) the _RST being “0” is the reset period. According to the present invention, after the power supply V _CC is turned on,
Since the "0" period from to occurs without fail, the circuit can be surely reset.

FIG. 4 is a circuit diagram showing another embodiment of the present invention. The same parts as those in FIG. 2 are designated by the same reference numerals.
The embodiment shown in the figure uses a series circuit of a resistor R5 and a Zener diode D1 as the voltage dividing circuit 10. The Zener voltage of the Zener diode D1 may be selected so that the transistor 11 is not turned on by the sneak current from the circuit of the other system when the power supply voltage V _CC is not applied. Then, when the power supply voltage V _CC is applied, the Zener diode D1 is turned on and the transistor 11 is turned on. Other operations are the same as those in FIG.

FIG. 5 is a circuit diagram showing a specific embodiment of the present invention. Option B is an option of system A, and clocks (CLK) and data (Data) sent from ICU7 and ICU8 of system A are received by ICU9 and ICU10 of option B and latched by an internal flip-flop 21. The notification is sent to the microprocessor 20.

The power and ground of option B is system A
It is assumed that the cable is supplied from the cable and is housed in the same cable (connector) 30 as the clock and the data. Options B, and includes a power-on reset circuit 40 according to the present invention, is adapted to reset the microprocessor 20 at its output V _{R ST.} The operation of the circuit thus configured will be described below with reference to the operation waveforms of FIG.

Now, the case where the option B is connected while the power of the system A is still on will be described. It is assumed that the cable 30 is connected at the time shown in FIG. In this case, the signal lines or the power lines are not always connected at the same time, and the four lines of V _CC , E, CLK and Data lines are not
Consider a case in which the lines are connected in the order of E → Data → CLK → _VCC .

When the E line → Data line is connected, I
Power supply V1 of system A via output of CU8 and resistor R10 to power supply V of option B via resistor R13
Current flows into 2. The potential of V2 is ICU7, ICU
Since it goes through 8, the resistor R9, the resistor R10, etc., it becomes lower than V1 as shown in (a). At this time, the voltage V2 prevents the transistor 11 from turning on.
Set the value of 7. As a result, the divided potential V _TR does not reach the level for turning on the transistor 11 as shown in (b). Therefore, the transistor 11 is off as shown in (c).

Next, at time, it is assumed that the line of the power supply voltage V _CC is connected and the power supply V2 has risen to the normal potential as shown in (a). As a result, the divided potential V _TR
Reaches a level at which the transistor 11 is turned on, and the transistor 11 is turned on at time as shown in (c).

As a result of turning on the transistor 11, the divided potential V of the charging / discharging circuit 12 which has been at a certain level up to that point.
_CR is discharged to almost 0V, and then charging of the capacitor C4 is started. Then, the potential V of the capacitor C4
_CR gradually increases as shown in (d).

At the time when this potential exceeds a certain level, the waveform shaping circuit 13 is turned on as shown in (e). As a result, the reset is released, and the power-on reset is normally and surely performed. Here, the time Δt from the time when the transistor 11 is turned on to the time when the waveform shaping circuit 13 is turned on is the reset time.

In the above description, the case where the Schmitt trigger circuit is used as the waveform shaping circuit 13 is taken as an example, but the present invention is not limited to this. Any circuit may be used as long as it is a level trigger type waveform shaping circuit.
Also, the switching element is not limited to the transistor, and may be another element such as an FET.

In the above embodiment, the case where the option B is hot-plugged into the system A has been described, but the present invention can be applied to the case where the system A and the option B are operated by different power sources. Therefore, a reliable power-on reset can be performed.

Further, in the embodiment of FIG. 5, the resistor R13
Alternatively, the case where a current flows into V2 due to R11 has been described, but when ICU9 and ICU10 are MOS elements, a current occurs due to a parasitic diode generated inside the IC even without resistors R11 and R13, which causes a problem. There is no difference. Therefore, the present invention is applicable even in this case.

[0034]

As described above in detail, according to the present invention, the charging of the charging / discharging circuit is prevented from being started to a certain level by the power supply voltage V _CC .
It is possible to provide a power-on reset circuit that can surely perform power-on reset without being aware of the power-on sequence, and the practical effect is extremely large.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing operation waveforms of the circuit shown in FIG.

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

FIG. 5 is a circuit diagram showing a specific embodiment of the present invention.

6 is a diagram showing an example of operation waveforms of respective parts of the circuit shown in FIG.

FIG. 7 is a diagram showing an example of a conventional power-on reset circuit.

FIG. 8 is a diagram showing operation waveforms of each unit.

FIG. 9 is an explanatory diagram of a problem of the conventional circuit.

[Explanation of symbols]

 10 voltage dividing circuit 11 switching element 12 charging / discharging circuit 13 waveform shaping circuit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Haruo Suzuki Haruo Suzuki 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu ACE Co., Ltd. Nagoya Communication System Co., Ltd.

Claims (5)

[Claims] 1. A voltage dividing circuit (10) for dividing a power supply voltage.
A switching element (11) for performing a switching operation by receiving the output of the voltage dividing circuit (10); a charging / discharging circuit (12) connected to the switching element (11); and a charging / discharging circuit (12). A power-on reset circuit including a waveform shaping circuit (13) that receives the output of the above, shapes the waveform, and outputs a reset pulse. 2. The power-on reset circuit according to claim 1, wherein a circuit including a resistor is used as the voltage dividing circuit (10). 3. The power-on reset circuit according to claim 1, wherein a circuit composed of a resistor and a Zener diode is used as the voltage dividing circuit (10). 4. The circuit comprising resistors and capacitors is used as the charging / discharging circuit (12).
The power-on reset circuit described. 5. The waveform shaping circuit according to claim 1, wherein a Schmitt trigger circuit is used as the waveform shaping circuit (13).