JPS61112269A - Answer reception control system - Google Patents

Abstract

PURPOSE:To attain a quick processing with an answer reception control system without monitoring the no-answer time despite the presence of an unpackaged processor, etc., by providing individually the signal lines displaying under- operation modes to each processor. CONSTITUTION:The signal lines 12-15 display the under-operation modes of processors 2-5 respectively and deliver an ON signal when the electric power supply is applied to each processor. Then the processor 2, for example, receives an answer through a register 30 from a bus 1. Thus the originator processor address is decoded by a decoder 31, and one of latches 33-35 corresponding to those processors is set. The OR is secured between the outputs of latches 33-35 and the signals given from the signal lines 23-25 displaying the under- operation modes of processors 3-5. Then the AND of the outputs of those latches is equal to a signal 36. Thus the signal 36 is turned on when the answer is already received or the signal line showing the under-operation mode is cut off with all processors 3-5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for receiving responses from each of a plurality of processing devices connected to a lotus.

In an information processing system that has multiple processing units such as a central processing unit, commands are transferred from one processing unit to another processing unit all at once, and the processing unit that receives the command transmits information such as the execution status of the command. The need to transfer the response to the command issuing processor means that, for example, the address translation buffer (
This is well known for example in the case of invalidation processing of TLB).

In such processing, if there is no response, it would be desirable to be able to accurately identify the cause, in order to speed up the processing.

[Prior art and problems to be solved by the invention] FIG. 2 is a block diagram showing an example of a configuration in which a plurality of processing devices 2 to 5, etc. are connected to one lotus 1 in an information processing system. .

In such a configuration, for example, when the processing device 2 executes a TLB invalidation instruction, as a result, the processing device 2
A TLB invalidation command is sent to all other processing devices 3 to 5.
receives the commands from Lotus 1 all at once.

When the processing devices 3 to 5 successfully process the received command, they each transfer a response via the bus 1.

In this case, if the transfer requests of each processing device 3 to 5 conflict,
Priority control is performed using a conventional, well-known method, and responses from each of the processing devices 3 to 5 are sequentially transferred in time series and received by the processing device 2.

For example, if the processing device 3 has some kind of failure and does not send a response, the processing device 2 waits for a response for a predetermined length of time after the command is advanced, and then determines that there is no response by not receiving a response. .

This time should be long enough to allow successful reception of a normal response even if it has the longest delay.

If this non-response is due to the occurrence of some kind of abnormal condition, it is necessary to start the required fault handling, but the same non-response result will occur if, for example, the processing device 3 is not installed. For example, it is confirmed based on previously stored system configuration information that the processing device 3 is installed.

As mentioned above, if there is a processing device in the system that is not installed or whose power has been turned off for maintenance, the waiting time described above always elapses before the processing waiting for a response is completed. Therefore, there was a problem that processing time was wasted.

[Means for solving problems]

The above problem is that in an information processing system having a plurality of processing devices connected by a 1Mi bus, one processing device transfers commands to the other processing devices all at once via the path,
When receiving a response to the command transferred from the other processing device, there is a signal line that individually indicates whether each of the processing devices is in operation, and depending on the status displayed by the signal line, the response to the command is received. This problem is solved by the response reception control method of the present invention, which identifies the validity of the reception state.

[Effect]

That is, a signal line for indicating that each processing device is in operation is individually provided so as to turn on, for example, when the processing device is in operation.
Each processing device is configured to receive cough signals from other processing devices in parallel.

When each processing device receives the response, it
゛1 For processing devices whose display signal line is off,
For example, the response is treated as already received, the response is actually received only from the processing device in the ON state, or the non-response is determined by the above-mentioned time monitoring or the like.

Therefore, even if there is a processing device that is not installed, processing can normally be completed quickly without requiring time monitoring, and if time monitoring determines that there is no response, it is immediately determined that there is an abnormality with the processing device. You can perform the necessary processing using

〔Example〕

FIG. 1 (al is a block diagram showing the system configuration of an embodiment of the present invention.

In the figure, signal lines 12, 13, 14, and 15 are in-operation display signal lines that display the operating status of each processing device 2.3.4.5, for example, when each processing device is powered on. It outputs an on signal, and becomes an off signal when the power is cut off or not mounted.

Each signal line 12 to 15 is 23.24
．． 25, each of which is configured to input to all other processing devices in a similar manner.

For example, in the processing device 2, with the configuration shown in FIG. 1(b),
When a response from the lotus 1 is received in the register 30, a part of the source processing device address is decoded by the decoder 31, and one of the lunches 33 to 35 corresponding to each processing device is set.

The outputs of the latches 33-35 are connected to the gates 43-45, and the signal lines 23-25 are connected to the operation display signal lines 23-25 of the other processing devices 3-5.
The logical sum of the signal and the negative signal is taken, and the logical sum gate 4
The AND of the outputs 3 to 45 is output to the signal line 36.

Therefore, for all other processing devices 3 to 5, the signal line 36 is turned on when a response has been received or the in-operation display signal line is off.

The signal on signal line 36 is used in the processing unit to identify completion of response reception, and also to stop the separately activated time monitoring as described above.

With the above configuration, even if there is a processing device that is not installed, each processing device can proceed to the next processing immediately after receiving a response from an operating processing device, and there is no need to rely on time monitoring. It disappears.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, when a plurality of processing devices receive a response to a command received at the same time, a non-response determination is made at high speed, thereby improving the processing efficiency of an information processing system. This has a significant industrial effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional configuration. In the figure, 1 is a lotus, 2 to 5 are processing devices, and 12 to 1
5 is an operating display signal line, 30 is a register, 31 is a decoder, 33 to 35
is a lunch, and 43 to 45 are OR gates. Sheep 1 Threshold (a-) (b)

Claims (1)

[Claims] In an information processing system having a plurality of processing devices connected by a set of buses, one of the processing devices transfers commands to the other processing devices all at once via the bus, and the commands transferred from the other processing devices are When receiving a response to a command, it has a signal line that individually indicates whether each of the processing devices is in operation, and the validity of the state in which the response has not been received is determined based on the status displayed by the signal line. A response reception control method characterized by comprising: