JPH0321938B2 - - Google Patents
Info
- Publication number
- JPH0321938B2 JPH0321938B2 JP59216589A JP21658984A JPH0321938B2 JP H0321938 B2 JPH0321938 B2 JP H0321938B2 JP 59216589 A JP59216589 A JP 59216589A JP 21658984 A JP21658984 A JP 21658984A JP H0321938 B2 JPH0321938 B2 JP H0321938B2
- Authority
- JP
- Japan
- Prior art keywords
- processing device
- response
- processing
- signal line
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012545 processing Methods 0.000 claims description 69
- 238000000034 method Methods 0.000 claims description 7
- 230000010365 information processing Effects 0.000 claims description 5
- 238000012546 transfer Methods 0.000 claims description 5
- 238000012544 monitoring process Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はバスに接続された複数の処理装置の、
各々からの応答を受信するための制御方式に関す
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for processing a plurality of processing devices connected to a bus.
This invention relates to a control method for receiving responses from each.
複数の中央処理装置等の処理装置を有する情報
処理システムにおいて、１の処理装置から他の処
理装置へ一斉に指令を転送し、該指令を受信した
処理装置からは、該指令の実行状態等の応答を指
令発行処理装置へ転送することが必要になること
は、例えばアドレス変換バツフア（TLB）の無
効化処理の場合等の例でよく知られている。 In an information processing system that has multiple processing units such as a central processing unit, commands are transferred from one processing unit to another processing unit all at once, and the processing unit that receives the command transmits information such as the execution status of the command. It is well known that it is necessary to transfer a response to a command issuing processing device, for example in the case of invalidation processing of an address translation buffer (TLB).
このような処理において、応答のない場合に、
その要因を的確に識別できるならば、処理の迅速
化等の上で望ましい。 In such processing, if there is no response,
It is desirable to be able to accurately identify the cause of the problem in order to speed up the processing.
第２図は情報処理システムにおける、１組のバ
ス１に複数の処理装置２〜５等が接続された構成
の一例を示すブロツク図である。
FIG. 2 is a block diagram showing an example of a configuration in which a plurality of processing devices 2 to 5 are connected to one bus 1 in an information processing system.
このような構成において、例えば処理装置２が
TLB無効化命令を実行すると、その結果処理装
置２からバス１へTLB無効化指令が送出され、
他の全処理装置３〜５はバス１から該指令を一斉
に受信する。 In such a configuration, for example, the processing device 2
When the TLB invalidation command is executed, as a result, the TLB invalidation command is sent from the processing device 2 to the bus 1,
All other processing devices 3 to 5 receive the command from bus 1 all at once.
処理装置３〜５が受信した指令を正常に処理す
ると、それぞれ応答をバス１によつて転送する。
この場合、各処理装置３〜５の転送要求が競合す
れば、通常の公知の１方法で優先制御が行われ
て、各処理装置３〜５からの応答は、時間的に直
列に順次転送され、処理装置２で受信される。 When the processing devices 3 to 5 successfully process the received command, they each transfer a response via the bus 1.
In this case, if the transfer requests of the processing devices 3 to 5 conflict, priority control is performed using one of the usual known methods, and the responses from the processing devices 3 to 5 are sequentially transferred serially in time. , is received by the processing device 2.
例えば処理装置３に何等かの障害があつて、応
答を送出しない場合には、処理装置２は指令送出
後所定長の時間、応答の受信を待つた後に応答を
受信しないことにより無応答と判定する。 For example, if the processing device 3 has some kind of failure and does not send a response, the processing device 2 waits for a response for a predetermined length of time after sending the command, and then determines that there is no response by not receiving a response. do.
この時間は、正常な応答に最も長い遅延がある
場合にも、その応答を正常に受信できるように、
十分長くする必要がある。 This time is set to ensure that a successful response is received even if the response has the longest delay.
It needs to be long enough.
この無応答が何等かの異常状態の発生によるも
のであれば、所要の障害処理を開始する必要があ
るが、例えば処理装置３が未実装の場合等も同様
の無応答の結果になるので、例えば予め記憶され
ているシステム構成情報により、処理装置３が実
装されていることを確認する。 If this non-response is due to the occurrence of some kind of abnormal condition, it is necessary to start the required fault handling, but the same non-response result will occur if, for example, the processing device 3 is not installed. For example, it is confirmed based on previously stored system configuration information that the processing device 3 is installed.
以上のように、システムに未実装処理装置ある
いは保守のために電源断にされている等の処理装
置がある場合には、応答待ちの処理を完了するま
でに常に前記のような待ち時間を経過することに
なるので、処理時間を浪費するという問題があつ
た。 As mentioned above, if there is a processing device in the system that is not installed or whose power has been turned off for maintenance, the waiting time described above always elapses before the processing waiting for a response is completed. Therefore, there was a problem that processing time was wasted.
前記の問題点は、１組のバスによつて接続され
た複数の処理装置を有する情報処理システムの１
の該処理装置が他の該処理装置へ該バスにより一
斉に指令を転送し、該他の処理装置から転送され
る該指令に対する応答を受信するに際し、各該処
理装置の動作中を所定の信号状態によつて表示す
る信号線を個別に有し、該信号線が該所定の信号
状態でない当該処理装置については、該応答を受
信済みとして制御し、該所定の信号状態の当該処
理装置についてのみ、該処理装置から転送される
該応答の受信を待機するようにした本発明の応答
受信制御方式によつて解決される。
The above problem arises when one of the information processing systems has a plurality of processing devices connected by a set of buses.
When this processing device transfers commands to other processing devices all at once via the bus and receives a response to the commands transferred from the other processing devices, a predetermined signal indicates that each processing device is in operation. For the processing device that has an individual signal line that is displayed depending on the state, and the signal line is not in the predetermined signal state, the response is controlled as having been received, and only for the processing device in the predetermined signal state. This problem is solved by the response reception control method of the present invention, which waits for reception of the response transferred from the processing device.
即ち、各処理装置の動作中状態において例えば
オン状態になるようにした、動作中表示の信号線
を個別に設け、各処理装置は他の処理装置の該信
号線の信号を並列に受信するように構成する。
That is, each processing device is provided with a signal line indicating that the processing device is in operation and is turned on, for example, when the processing device is in operation, and each processing device receives signals on the signal line of other processing devices in parallel. Configure.
各処理装置が前記応答を受信する場合には、動
作中表示信号線がオフ状態の処理装置について
は、例えば応答を受信済として処理し、オン状態
の処理装置についてのみ実際に応答を受信し、又
は前記の時間監視等による無応答判定をする。 When each processing device receives the response, for example, the processing device whose operating display signal line is in the OFF state processes the response as having been received, and only the processing device whose operating display signal line is in the ON state actually receives the response; Alternatively, non-response is determined by the above-mentioned time monitoring.
従つて未実装等の処理装置があつても、通常は
時間監視にかかることなく迅速に処理を終了する
ことができ、時間監視によつて無応答と判定した
場合は直ちに該当処理装置に関して異常があると
決定して所要の処理を行うことができる。 Therefore, even if there is a processing device that is not installed, processing can normally be completed quickly without requiring time monitoring, and if time monitoring determines that there is no response, an abnormality can be detected immediately with respect to the processing device. It is possible to determine that there is such a thing and perform the necessary processing.
第１図ａは本発明の一実施例システム構成を示
すブロツク図である。
FIG. 1a is a block diagram showing the system configuration of an embodiment of the present invention.
図において信号線１２，１３，１４，１５は、
それぞれ各処理装置２，３，４，５の動作中状態
を表示する動作中表示信号線で、例えば各処理装
置に電源が投入されているときオン信号を出力
し、電源断又は未実装状態ではオフ信号になつて
いる。 In the figure, the signal lines 12, 13, 14, 15 are
These are operating display signal lines that display the operating status of each processing device 2, 3, 4, and 5. For example, when each processing device is powered on, an on signal is output, and when the power is turned off or it is not installed, it outputs an on signal. The signal is off.
各信号線１２〜１５は、処理装置２について２
３，２４，２５で示すと同様の態様で、それぞれ
他の全処理装置に入力するように構成される。 Each signal line 12 to 15 has two
3, 24, and 25 are configured in a similar manner to input to all other processing devices, respectively.
例えば処理装置２では第１図ｂに示す構成によ
り、バス１から応答をレジスタ３０に受信する
と、その一部の発信元処理装置アドレスを、デコ
ーダ３１でデコードして、各処理装置に対応する
ラツチ３３〜３５の１つをセツトする。 For example, in the processing device 2, when a response is received from the bus 1 in the register 30 using the configuration shown in FIG. Set one of 33 to 35.
ラツチ３３〜３５の出力はゲート４３〜４５に
接続されて、他の処理装置３〜５の動作中表示信
号線２３〜２５の信号の否定信号との論理和がと
られ、論理和ゲート４３〜４５の出力の論理積を
信号線３６に出力する。 The outputs of the latches 33-35 are connected to gates 43-45, and are ORed with the negation signals of the signals on the operating display signal lines 23-25 of the other processing devices 3-5. The AND of the outputs of 45 is output to the signal line 36.
従つて、すべての他の処理装置３〜５につい
て、応答受信済か又は動作中表示信号線オフの状
態において、信号線３６はオンになる。 Therefore, for all other processing devices 3 to 5, the signal line 36 is turned on when a response has been received or the in-operation display signal line is off.
信号線３６の信号は、処理装置において応答受
信完了を識別するように使用され、又前記のよう
に別途起動されている時間監視を停止させる。 The signal on signal line 36 is used in the processing unit to identify completion of response reception, and also to stop the separately activated time monitoring as described above.
以上の構成により、未実装等の処理装置がある
場合にも、各処理装置は動作中の処理装置からの
応答を受信すれば直ちに次の処理へ進むことが可
能となり、時間監視に頼る必要が無くなる。 With the above configuration, even if there is a processing device that is not installed, each processing device can proceed to the next processing immediately after receiving a response from an operating processing device, and there is no need to rely on time monitoring. It disappears.
以上の説明から明らかなように本発明によれ
ば、複数の処理装置が一斉に受信する指令に対す
る応答を受信する場合に無応答の判定が高速に行
われるので、情報処理システムの処理効率を改善
するという著しい工業的効果がある。
As is clear from the above description, according to the present invention, when a plurality of processing devices receive a response to a command received at the same time, a non-response determination is made at high speed, thereby improving the processing efficiency of an information processing system. This has a significant industrial effect.
第１図は本発明の一実施例構成のブロツク図、
第２図は従来の一構成例を示すブロツク図であ
る。
図において、１はバス、２〜５は処理装置、１
２〜１５は動作中表示信号線、３０はレジスタ、
３１はデコーダ、３３〜３５はラツチ、４３〜４
５は論理和ゲートを示す。
FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of a conventional configuration. In the figure, 1 is a bus, 2 to 5 are processing units, 1
2 to 15 are operating display signal lines, 30 is a register,
31 is a decoder, 33-35 are latches, 43-4
5 indicates an OR gate.
Claims (1)
置を有する情報処理システムの１の該処理装置が
他の該処理装置へ該バスにより一斉に指令を転送
し、該他の処理装置から転送される該指令に対す
る応答を受信するに際し、 各該処理装置の動作中を所定の信号状態によつ
て表示する信号線を個別に有し、 該信号線が該所定の信号状態でない当該処理装
置については、該応答を受信済みとして制御し、 該所定の信号状態の当該処理装置についての
み、該処理装置から転送される該応答の受信を待
機するように構成されていることを特徴とする応
答受信制御方式。[Claims] 1. In an information processing system having a plurality of processing devices connected by a set of buses, one processing device transfers commands to the other processing devices all at once via the bus, and When receiving a response to the command transferred from another processing device, each processing device has an individual signal line that indicates the operation of the processing device by a predetermined signal state, and the signal line corresponds to the predetermined signal. The processing device that is not in this state is controlled as having received the response, and only the processing device that is in the predetermined signal state is configured to wait for reception of the response transferred from the processing device. A response reception control method characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59216589A JPS61112269A (en) | 1984-10-16 | 1984-10-16 | Answer reception control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59216589A JPS61112269A (en) | 1984-10-16 | 1984-10-16 | Answer reception control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61112269A JPS61112269A (en) | 1986-05-30 |
| JPH0321938B2 true JPH0321938B2 (en) | 1991-03-25 |
Family
ID=16690785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59216589A Granted JPS61112269A (en) | 1984-10-16 | 1984-10-16 | Answer reception control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61112269A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5361943A (en) * | 1976-11-16 | 1978-06-02 | Nippon Telegr & Teleph Corp <Ntt> | Data transfer system |
| JPS56149627A (en) * | 1980-04-23 | 1981-11-19 | Hitachi Ltd | Fault informing system among plural devices |
-
1984
- 1984-10-16 JP JP59216589A patent/JPS61112269A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5361943A (en) * | 1976-11-16 | 1978-06-02 | Nippon Telegr & Teleph Corp <Ntt> | Data transfer system |
| JPS56149627A (en) * | 1980-04-23 | 1981-11-19 | Hitachi Ltd | Fault informing system among plural devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61112269A (en) | 1986-05-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |