JPS61110426A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To form a contact hole without over etching and unetched region to an insulating film having difference in thickness by previously removing an insulating film of thick region, thereafter forming a thin insulation film and simultaneously etching the region of reduced thickness and the thin insulating film. CONSTITUTION:An N<-> epitaxial layer 11 is formed on a P<+>Si substrate land SiO24 is formed while N<+> layer is formed within a diffusion window of SiO23. The SiO24 on the N<+> layer is totally removed and photo processing is carried out, and etching is then carried out using the SiO2 etchant for SiO23 to form the holes 21, 22. This etching removes SiO2 at the area where etching may easily be left due to thick SiO2 at the area where becomes a contact hole later and thereby the holes 21, 22 are formed. Next, the SiO212 which will become a capacitor is accurately controlled for thickness by the Si oxidation technique. The photo processing is carried out again, etching is carried out for SiO212 and thereby the contact holes 5-9 can be completed.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method C for manufacturing a semiconductor integrated circuit device.
Nipai Polar Process (CJ Contact) - relates to a method for forming holes.

[Conventional technology]

Conventionally, in the biboke process, SiO with a film thickness difference of more than 10 times was used to adjust the capacitance of the capacitor.
, and technical problems arise in forming these SiO,t-contact holes.

FIG. 4 shows a conventional bipolar process, which will be explained below.

■ Figure v4Jt; In P8 substrate 1 (2N-Evita Kinyal 1i11 is formed), P isolation layer 2 (element region is separated from the two), TR is a bipolar transistor region, and C is a capacitor formation region. Yes, 3 is Si for protection.
In the diffusion window C of the SL0.5, Sin and 4 are formed when the N layer is formed.

■ Figure (B) c s and remove all Si0.4 on the N layer.

■ Figure (in Q, S of the desired thickness on the N layer)
! form 12. The Si Otj'l is formed to a desired thickness to adjust the capacitance of the condenser.

■ In Figure 0, from contact etch C:.

Contact holes 5-9 are formed.

[Problem that the invention seeks to solve]

However, in the bipolar process mentioned above,! !
Contact etch C in direction 1: Actually, SL
O, lateral over-etching occurs in thinner portions of the film, and etch residue occurs in thicker portions.

As a result, it did not look like the ideal diagram shown in Figure 1 (8).
), etching remains (hatched areas) occur in contact holes 5' and 6', resulting in 7' + 8' + 9
7. 2. Over-etching occurs. This is because
Sto, 3 (Thick and thin parts Sc Ot i 2
Then, this is because the thickness is more than 10 times different, and the thicker part becomes insufficiently etched, resulting in StO! is not removed and remains partially;
The thin portion (deliberately made thinner for volumetric tm adjustment) becomes over-etched in the lateral direction, exposing the pn junction.

[Means to solve problems]

In order to solve the above problems, the present invention C2 (;
, contact error y-Y- [without grinning, as in the past,
In the first etching C2, a thick part C2 of the insulating film (Sin2) is opened by 6t in advance, and then a desired thin insulating film is etched on the N layer (Sin on the N layer is completely removed as before). A film (Sin film) is formed and a second contact error is performed to complete the contact hole.

In the first etching, after removing all of the N layer, the second contact etching process is carried out using a photo mask using a known photographic technique (2). , is the part that becomes the contact hole after the thick part Bo SLO!5), :SiO! Since C2 is thick, a portion of Sin, which tends to leave etching residue, is removed. Next, using known Si oxidation technology, the thickness of the portion that will become the capacitor is determined. Control and shape. At this time, photo processing and S&O etching are performed again using the contact mask used earlier.

〔Example〕

FIG. 1 shows the steps of an embodiment of the present invention, which will be explained below.

■ Figure (8) is the same as the conventional one, with a P Si substrate 1 (two N-epitaxial layers 11 are formed, a P isolation layer 2 (the element region is separated from the two, and TE is a bipolar transistor region). , C is the capacitance forming region. 3 is the SiO protective film, the film (1O used as a diffusion mask)
, ooof or more SiO,), and within the diffusion window of the Si0,5 (2 is sto, 4 is formed when forming the N layer).

@ Figure (b) In C2, S c Q t on the N+ layer
4 Remove all Y.

■ Figure (C) l = #, using a photomask (not shown) used for the contact 9f-, a known photographic technique (two photo processes) was performed, and an etching mask was formed using a photoresist. , Holes 21 and 22 are formed by etching all of the holes 21 and 22 using a known SLO etching solution.

sio! 2, the Si on the N region that is removed will be partially exposed where a contact hole will be formed later.
Etching solution of z Oz (= contact, but the etching speed of Si is much higher than that of Sin?
There is no problem with Sct2 due to the influence of the etching solution.

This etching (Fig. (c)) is completed, and in the part that will later become the C2 contact hole, the thick sin!; , 22 are formed.

Also, at this time, even if Sin is not completely removed and there is some etching remaining, there will be no problem as the same part will be etched once again, so it can be removed at that time. do not have.

(2) As shown in Figure pcH, the thickness of S'0x12 in the portion that will become the capacitor is controlled accurately using the well-known Si oxidation technique. For example, 1ooo! +2 form.

■ In the figure, the contact error f (
2. Photo processing using a photo mask, 5
Etching of io212 is performed to complete contact holes 5-9. At this time, the contact etch is
Since this is done on S'to, 12, which has the same film thickness, there is no over-
No etch or etch residue occurs.

The details of how an ideal contact hole is formed in the present invention as shown in Fig. 1 are explained below.
This will be explained using figures.

Figure 2 shows the conventional method, in which Si on a 5i50 substrate is
O! Figure 13 of 5+Niphoto resist (A)
L: The hole 14 is formed by one etching. In contrast, in the example of FIG. 5 of the present invention.

As shown in Figure (A), a hole 15 is previously formed in the oxide film, S'&0,3 (corresponding to 21.22 in the first diagram).

In Figure (73), the hole 16)i formed by the first-order etching, and the lateral etching of the perforated portion 1'5, give the hole 16 an inclination. the result.

The contact hole in the thick part of S&□t becomes smoother, reducing the risk of A11IrR.C2.

〔effect〕

As described above, according to the present invention, when there is a large difference in the thickness f of the insulating film to be etched, the thick part of the insulating film is removed in advance or the thin film is removed before forming the thin insulating film. After that, a thin insulating film is formed, and the previously thinned part of the thick insulating film and the thin insulating film are simultaneously (
Insulating film C:, over-etching, over-etching, with a thickness difference of more than 10 times due to layering
A contact hole can be formed during fx, and the yield is significantly improved compared to the conventional method.

In particular, an etching mask using a photoresist film to remove or thin the first thick part of the film, etc., and an etching mask for the second etching.
When forming each mask, the same etching mask can be used, and there is an advantage that a new photo mask is not required.

[Brief explanation of the drawing]

1(4) to 1) are manufacturing process diagrams of a semiconductor integrated circuit device according to the present invention. Figure 2 (a), (BI is a diagram of the contact hole formation process of a conventional semiconductor device. '@Figure 5 (4, (a) is a diagram of the contact hole formation process of the embodiment of the present invention. '@Figure 4 (4) ~(3) is a manufacturing process diagram of a conventional semiconductor integrated circuit. 1...PS board 2...P Separation layer 5...Sin. 4--4SiO, (at the time of N layer formation) 5- 9... Contact hole 11... N-epitaxial layer 12... S pin O! 21, 22... Hole

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor integrated circuit device including a step of forming desired contact holes in both a thick insulating film and a thin insulating film formed on a semiconductor, in which a thick insulating film with a predetermined opening is formed on the semiconductor. A film is formed, a portion of the thick insulating film where a contact hole is to be formed is removed or thinned by photolithography, a desired thin insulating film is formed, and then the thick insulating film is removed by photolithography again. 1. A method of manufacturing a semiconductor integrated circuit device, comprising the step of simultaneously forming a contact hole in a portion of an insulating film where a contact hole is to be formed and the thin insulating film. (2) The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the photolithography is performed using the same mask.