JPS61109320A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To suppress a charge/discharge peak current of a load capacitor to a small value by allowing plural transistors (TRs) of the final stage to charge/discharge an electric charge stored in the load capacitor when the level of an input signal is changed. CONSTITUTION:An output of gates 11, 12 is inverted immediately and goes to 'L', 'H' respectively when the input signal IN changes from 'L' to 'H'. Since a TR13 is turned on and a TR15 is turned off at the same time, the level of a signal line L11 changes to 'H' to turn off a TRTr12. Further, a TR16 is turned on and a TR18 is turned off and the level of signal line L12 is dependent on an output signal OUT. The output level of the gate 12 goes to 'H', then the TRTr11 is turned off and the TRTr12 is turned on and the electric charge stored in the load capacitor is discharged through the TRTr12. Since the TRTr12 has a large on-resistance, the peak current is small. Similarly, when the signal IN changes from 'H' to 'L', the peak value of the charge current is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit of a complementary integrated circuit (hereinafter referred to as 0MO8LSI).

[Conventional technology]

Conventionally, the output buffer circuit of 0MO8LSI is shown in Fig. 6.
As shown in Figure 4, the load container is #JAvJ1m
The output transistor Trsl H'rrsg (Tr4
1 + Tr4m) and these output transistors Trs
+, 'rrlj (Tr4x *Tr4g) control gate 61.32 (41.

42.43, 44.45). .

In the circuit of FIG. 6, the output signal OUT is the human input signal I
determined by N, and the circuit of FIG. 4;
When the control signal C is inactive (low level), the output signal OUT is in a zero impedance state, and when the control signal C is active (high level), the output signal OUT is determined by the input signal IN.

[The problem that the invention attempts to solve]

By the way, as the speed of integrated circuits increases, output buffer circuits are also required to operate at extremely high speeds.
If you try to achieve the same speed by simply increasing the size of the output transistor using the conventional method, when the output signal changes, the time variation of the load capacitance charging/discharging current of the output transistor (current) The curve becomes sharp as shown by curve 54 in the figure, and this instantaneous large current generates noise on the collector circuit and the GND line C, causing malfunction.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an output buffer circuit that is capable of reducing the peak current of the charging and discharging current of a load capacitor at a cylinder speed.

[Means for solving problems]

The present invention is applied to at least one set of a plurality of sets of output final stage transistors that drive one load capacitance and the output final stage transistor control gate.

That is, in the present invention, the peak current of the charging current of the load capacitor is suppressed to a small level by changing the level of the input signal.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of an output buffer circuit according to the present invention, and corresponds to the conventional example shown in FIG.

In this embodiment, two sets of output final stage transistors Tr11+Ttts and TrIs+ drive one load capacitance.
Tr+4, control gate 11.12, control gate 11
output and a pair of final stage transistors Tr1t, Tr
+2 output signal QUTl2 controls another set of final stage transistors Trs**TrIs, respectively.
Set of transistors 13, 14.15 and 16.17.18
Consisting of

Next (2) The operation of this embodiment will be explained.

Now, a case will be described in which the input signal IN changes from a low level (hereinafter referred to as "L") to a high level (hereinafter referred to as 'H').

When the input signal IN is “L”, the 1j force of the gate 111 is H.
'', the output of the gate 12 is L'', so the output transistor Trr1 is turned on and the output transistor Trlg is turned off. At this time, since the transistor 16 is off and the transistor 18 is on, the signal line L1. is "L'" and the output register 7/register 'rrt4 is in an off state. Therefore, the output signal OUT is "H" (2). Also, since the tra/raster 16 is off and the transistor 14.15 is on, the signal line Lll becomes "L++", and the output transistor T
rn is on (= turned on).

Here, when the input signal IN changes from "L" to °HH,
The outputs of gates 11 and 12 are immediately inverted and become "L" and "H", respectively. At the same time, transistor 13 is turned on and transistor 15 is turned off, so that signal line Li
t changes to H'', and the transistor Tru turns off.

At the same time, the transistor 16 is turned on and the transistor 18 is turned off, so that the signal line Ll11 becomes dependent on the output signal OUT.

The change in the output signal OUT at this time will be explained.

First, as the output of the gate 112 becomes "H", the transistor Trlt is turned off, and the transistor TrI! turns on, and the charge stored in the load capacitance (2) begins to be discharged through the transistor 'rrst. Since the on-resistance is larger than Trn ), the peak magnetic current is smaller than that of the conventional example.

The discharge current caused by this transistor Tr1m is shown by a curve 55 in FIG. This discharge causes the output signal OUT
The voltage begins to drop along curve 51 in FIG.

Since the on-resistance of the transistor Trs2 is large, the slope is naturally gentler than that of the conventional example (curve 52 in FIG. 5). However, the voltage of the output signal OUT is
When near the threshold vL (time tr), the signal line LH gradually changes to "H" (=2), and accordingly the transistor Tr14 turns on. From then on, the discharge continues through both the transistors Trxa and Trtn. The discharge current due to the transistor 'rr141- is shown by the curve 56 in FIG. 6. Therefore, the discharge current of the entire output transistor of this embodiment is shown by the curve 5 in FIG.
5 and 56 phases, ie curve 56 (denoted by 2).

The curve 56 has a lower peak than the discharge current curve 54 of the conventional example, indicating that the current is flowing on average.

The same is true when the input signal IN changes from "H'" to "L"(-); charging is initially performed through the first transistor Tr1t, and when the output signal OUT rises to a certain level, the transistor Trys is also turned on. ShiF transistor T
Charging is performed on both rs1 and Trta.

FIG. 2 is a circuit diagram of another embodiment of the output buffer circuit of the present invention corresponding to the conventional example of FIG. 4.

In this embodiment, two sets of final stage transistors Traz + Trn and Try@l'r drive one load container.
ra4, control gates 21, 22, 25, 24.25, and transistors 26, 27 that control the transistor Tra as from the output of the control gate 22 and the output signal OUTζ2.
28, the output of the control gate 124 and the output signal 0UT (transistor 2 which controls the transistor Tr t4)
9. Consists of 2A and 2B.

The operation is similar to the embodiment of FIG.

In this embodiment, when the control signal C is "L", the gate 22 is "L", and the gate 26 is "H".

Since the gate 24 is "H", the gate 25 is "L", the signal line Lzt is "H", and the signal line L!2 is "L", the output transistors Trx+ *Tru, Trn*
All Trs4 are turned off, the output signal OUT is in a high impedance state 42, and the control signal C is “H”
At the time of "H", similar to the circuit of the embodiment shown in FIG.
At the time of output, transistors Tr 21 and ``rr 211''
When outputting “Yes”, transistor Tr2g and 'rr 114
works.

Note that there may be three or more sets of output final stage transistors. In addition, transistors 16 to 18, transistor 26
~2B may be replaced with a gate circuit.

〔Effect of the invention〕

As explained above, in the present invention, one load capacitor is driven by a plurality of sets of output transistors, and at least one of the control gates for controlling each of the output transistors is provided.
2. Since the output of the output transistor is manually controlled, it is possible to realize an output buffer circuit that is high-speed and has a low peak of charging and discharging current.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the output buffer circuit according to the present invention, Figure 2 is a circuit diagram showing another embodiment of the output buffer circuit according to the present invention, and Figures 6 and 4 are A circuit diagram showing a conventional example of an output buffer circuit, FIG. 5 is a diagram showing changes in output voltage over time, and FIG. 6 is a diagram showing changes in charging/discharging current over time. IN...Human input signal, C ...Control signal, OUT...Output signal, 11~18.21~2912A, 2B...Control 11 gate, Ltill Lit + Lll IL! 3"°゛Signal line, Trst ~Trs* 1Trst~ Tri<
``'Output transistor, 51...present invention (: time-output voltage curve, 56...present invention (-time-release')
fM, current curve, 55...output transistor 'rrl
l Discharge current due to H, 56...output transistor 'I
Released by 'rt4'#! L current.

Claims (1)

[Claims] A CMOS integrated circuit includes a plurality of sets of output final stage transistors that drive one load capacitance and a plurality of sets of control gates that control each of the output final stage transistors, and the output of the output final stage transistor is connected to the control gate. An output buffer circuit characterized in that the output buffer circuit is input to at least one set of.