JPS61109139A - 演算装置 - Google Patents
演算装置Info
- Publication number
- JPS61109139A JPS61109139A JP59230768A JP23076884A JPS61109139A JP S61109139 A JPS61109139 A JP S61109139A JP 59230768 A JP59230768 A JP 59230768A JP 23076884 A JP23076884 A JP 23076884A JP S61109139 A JPS61109139 A JP S61109139A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- bits
- output
- point number
- absolute value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 20
- 238000013500 data storage Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59230768A JPS61109139A (ja) | 1984-11-01 | 1984-11-01 | 演算装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59230768A JPS61109139A (ja) | 1984-11-01 | 1984-11-01 | 演算装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61109139A true JPS61109139A (ja) | 1986-05-27 |
JPH0381175B2 JPH0381175B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1991-12-27 |
Family
ID=16912956
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59230768A Granted JPS61109139A (ja) | 1984-11-01 | 1984-11-01 | 演算装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61109139A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1988008606A1 (en) * | 1987-04-28 | 1988-11-03 | Fujitsu Ten Limited | Method and apparatus for data transfer |
JPS6431225A (en) * | 1987-07-28 | 1989-02-01 | Fujitsu Ten Ltd | Processor |
US5148161A (en) * | 1988-04-18 | 1992-09-15 | Fujitsu Ten Limited | Digital signal processor for fixed and floating point data |
-
1984
- 1984-11-01 JP JP59230768A patent/JPS61109139A/ja active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1988008606A1 (en) * | 1987-04-28 | 1988-11-03 | Fujitsu Ten Limited | Method and apparatus for data transfer |
JPS6431225A (en) * | 1987-07-28 | 1989-02-01 | Fujitsu Ten Ltd | Processor |
US5148161A (en) * | 1988-04-18 | 1992-09-15 | Fujitsu Ten Limited | Digital signal processor for fixed and floating point data |
Also Published As
Publication number | Publication date |
---|---|
JPH0381175B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1991-12-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4298949A (en) | Electronic calculator system having high order math capability | |
US3993891A (en) | High speed parallel digital adder employing conditional and look-ahead approaches | |
US4168530A (en) | Multiplication circuit using column compression | |
US3328763A (en) | Electronic desk-type computer | |
GB1108800A (en) | Improvements in or relating to electronic data processing machines | |
JPS6375932A (ja) | ディジタル乗算器 | |
US3822378A (en) | Addition-subtraction device and memory means utilizing stop codes to designate form of stored data | |
US3432811A (en) | Data compression/expansion and compressed data processing | |
US4302816A (en) | Key input control apparatus | |
US3402285A (en) | Calculating apparatus | |
GB1199022A (en) | Improvements in or relating to Calculators | |
JPS61109139A (ja) | 演算装置 | |
RU2099776C1 (ru) | Цифровой сумматор | |
US3987290A (en) | Calculator apparatus for displaying data in engineering notation | |
US3890496A (en) | Variable 8421 BCD multiplier | |
US4331951A (en) | BCD-to-Binary converter | |
GB2094525A (en) | Programmable read-only memory adder | |
US3622768A (en) | Dual key depression for decimal position selection | |
GB1132181A (en) | Time divisional display system for computers | |
JPS6229832B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | ||
US3582944A (en) | Indicating system of 4-bit coded signal | |
JP3055558B2 (ja) | nビット演算装置 | |
US3787672A (en) | Electronic calculating device having arithmetic and error-checking operational modes | |
US3627998A (en) | Arrangement for converting a binary number into a decimal number in a computer | |
SU830371A1 (ru) | Преобразователь двоичного кодаВ дЕС ТичНый |