JPS61107773A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61107773A JPS61107773A JP23062384A JP23062384A JPS61107773A JP S61107773 A JPS61107773 A JP S61107773A JP 23062384 A JP23062384 A JP 23062384A JP 23062384 A JP23062384 A JP 23062384A JP S61107773 A JPS61107773 A JP S61107773A
- Authority
- JP
- Japan
- Prior art keywords
- region
- transistor
- base
- diode
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 36
- 239000000758 substrate Substances 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 21
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 8
- 230000003321 amplification Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 238000013329 compounding Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 10
- 239000002131 composite material Substances 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 101150029237 Il11 gene Proteins 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/7302—Bipolar junction transistors structurally associated with other devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は半導体装置、特に、ダイオードとトランジス
タが複合化された半導体装置の構造の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in the structure of a semiconductor device, particularly a semiconductor device in which a diode and a transistor are combined.
［従来の技術］
第３図は、従来のフライホイールダイオード複合のパワ
ートランジスタの断面構造を示す図である。第３図にお
いて、トランジスタは、Ｎ＋＋域１およびＮ＋＋域１上
に形成されるＮ−型領域２よりなるコレクタと、Ｎ−型
頭Ｔ４２上に形成されるＰ型領域３からなるベースと、
ＰＰ！：！ｆＪ域３内に形成されるＮ＋＋域４かうなる
エミッタとから構成される。ダイオードは、Ｎ＋型領領
域１よびＮ−型領域２からなるカソード領域と、Ｎ−型
領域２上にＰ型領域３から分離して形成されるＰ型領域
５からなるアノード領域とで構成される。Ｐ型領域３お
よびＰ型領域５からなる領域の周縁外部には高耐圧化を
図るために、Ｐ型領域６からなるガードリングが設けら
れる。Ｎ＋型領領域１表面はコレクタ電極８が、Ｎ−型
領域２の表面には電極部を除いて表面保護用の絶縁膜７
が形成され、ベース領域、エミッタおよびアノ−、ド頭
域にはそれぞれベース電極９．エミッタおよび７ノード
電極１０が形成される。[Prior Art] FIG. 3 is a diagram showing a cross-sectional structure of a conventional flywheel diode composite power transistor. In FIG. 3, the transistor has a collector consisting of an N++ region 1 and an N-type region 2 formed on the N++ region 1, a base consisting of a P-type region 3 formed on an N-type head T42,
PP! :! It consists of an N++ region 4 formed within the fJ region 3 and an emitter formed in the N++ region 4. The diode is composed of a cathode region consisting of an N+ type region 1 and an N- type region 2, and an anode region consisting of a P type region 5 formed on the N- type region 2 and separated from a P type region 3. Ru. A guard ring consisting of a P-type region 6 is provided outside the periphery of the region consisting of the P-type region 3 and the P-type region 5 in order to increase the breakdown voltage. A collector electrode 8 is provided on the surface of the N+ type region 1, and an insulating film 7 for surface protection is provided on the surface of the N− type region 2, excluding the electrode portion.
are formed, and base electrodes 9. are formed in the base region, emitter, anode and dome regions, respectively. An emitter and seven node electrode 10 are formed.
従来の複合化技術においては、フライホイールダイオー
ドとトランジスタの分離は第３図に示されるように、Ｎ
−領域を挾んでベース領域３と７ノード領域５とを距離
ＩＩＭして行なわれる。この距離見に対する制約として
は、ガードリング６が不要であるような低耐圧用の複合
トランジスタの場合は、複合トランジスタが形成される
チップのサイズの許容できる範囲で決定される。また、
高耐圧用の複合トランジスタの場合は、トランジスタの
ベース領域とフライホイールダイオードの７ノードとの
間のＮ−領域において高耐圧印加時に形成される空乏層
が到達し得る範囲にする必要がある。従来の複合トラン
ジスタの場合は上述のような構造によりトランジスタと
ダイオードとを分離していた。In conventional composite technology, the separation of the flywheel diode and transistor is as shown in Figure 3.
- This is carried out by setting the distance IIM between the base region 3 and the 7-node region 5 with the region in between. In the case of a low-voltage composite transistor that does not require the guard ring 6, the restriction on this distance is determined by the allowable range of the size of the chip on which the composite transistor is formed. Also,
In the case of a composite transistor for high breakdown voltage, the N- region between the base region of the transistor and the 7th node of the flywheel diode needs to be in a range that can be reached by a depletion layer formed when a high breakdown voltage is applied. In the case of conventional composite transistors, the transistor and diode are separated by the structure described above.
［発明が解決しようとする問題点］
第４図は第３図に示される半導体装置の等価回路図であ
る。第４図に破線で示されるように、ブレナタイプにて
同一チップ内にフライホイールダイオードを複合する従
来の方法においては、トランジスタのベース（第３図の
３）をコレクタとして、ダイオードのアノード（第３図
の５）をエミッタとし、トランジスタのコレクタとダイ
オードのカソードとの共通領域であるＮ−領域（第３図
においで２）をベースとするラテラルＰＮＰ寄生トラ−
ンジスタが形成される。このラテラルＰＮＰ寄生トラン
ジスタによる電流増幅が以下に述べるような問題点を引
き起こす。[Problems to be Solved by the Invention] FIG. 4 is an equivalent circuit diagram of the semiconductor device shown in FIG. 3. As shown by the broken line in Figure 4, in the conventional method of combining flywheel diodes in the same chip using the Brenna type, the base of the transistor (3 in Figure 3) is used as the collector, and the anode (3 in Figure 3) is used as the collector. A lateral PNP parasitic transistor whose emitter is 5) in the figure and whose base is the N- region (2 in Figure 3), which is the common area between the collector of the transistor and the cathode of the diode.
register is formed. Current amplification by this lateral PNP parasitic transistor causes the following problems.
インダクティプ負荷においてスイッチング素子Ｉ□′
として用いる場合、ターンオフ時にエミッタビーベース
８間に逆バイアスを印加することが多い。When used as a switching element I□' in an inductive load, a reverse bias is often applied between the emitter base 8 at turn-off.
ラテラルＰＮＰ寄生トランジスタの電流壜幅率が大きい
場合においては、エミッタビーベース８間を逆バイアス
したとき、エミッタビーベース８間のインピーダンスが
低くなり、エミッタＥ−ペースＢ間に流れる電流■ε８
が非常に大きくなる。When the current width ratio of the lateral PNP parasitic transistor is large, when the emitter bee base 8 is reverse biased, the impedance between the emitter bee base 8 becomes low and the current flowing between the emitter E and the pace B ε8
becomes very large.
具体的な例により少し詳しく説明する。This will be explained in a little more detail using a specific example.
第５図は、３層インバータ回路の１１ｉ！分に対応する
回路の等価回路図である。第５図において、ＮＰＮＩ−
ランジスタＴｒ１のエミッタとＮＰＮトランジスタＴｒ
２のコレクタとが接続される。トランジスタＴｒ １の
ベース−エミッタ間には逆バイアスが印加される。トラ
ンジスタＴｒ２のベース−エミッタ間にこの回路の駆動
用信号が与えられる。トランジスタＴｒ １．Ｔｒ ２
にはそれぞれフライホイールダイオードＤ、、Ｄ、が接
続される。コイルしかこの回路の負荷である。トランジ
スタＴｒ２に第５図に示すような信号が与えられると信
号レベルに応じてトランジスタＴｒ２がオフ状態になる
。このとき負荷電流Ｉｔが図の破線で示すような方向（
トランジスタＴｒ２のコレクタからエミッタへの方向）
へ流れて電流■。となる。次にトランジスタＴｒ２がオ
フ状態になると、負荷電流■Ｌは図に実線で示されるよ
うにフライホイールダイオードＤ、の順方向に流れる。Figure 5 shows 11i! of a three-layer inverter circuit. FIG. In Figure 5, NPNI-
Emitter of transistor Tr1 and NPN transistor Tr
2 collector is connected. A reverse bias is applied between the base and emitter of the transistor Tr1. A driving signal for this circuit is applied between the base and emitter of the transistor Tr2. Transistor Tr 1. Tr 2
A flywheel diode D, , D, is connected to each. The coil is the only load on this circuit. When a signal as shown in FIG. 5 is applied to the transistor Tr2, the transistor Tr2 is turned off in accordance with the signal level. At this time, the load current It is directed in the direction shown by the broken line in the figure (
(direction from collector to emitter of transistor Tr2)
Current flows to■. becomes. Next, when the transistor Tr2 is turned off, the load current ■L flows in the forward direction of the flywheel diode D, as shown by the solid line in the figure.
このことは、ラテラルＰＮＰ寄生トランジスタにおいて
、ダイオードＤ、のアノードがエミッタＥＬになり１ま
たダイオードＤ、のカソードがベースＢＬとなるので、
寄生トランジスタのエミッタＥＬからベースＢ、ヘキャ
リアが注入されたことになる。This means that in the lateral PNP parasitic transistor, the anode of the diode D becomes the emitter EL, and the cathode of the diode D becomes the base BL.
This means that carriers are injected from the emitter EL of the parasitic transistor to the base B.
このとき、トランジスタのベースＢがトランジスタのエ
ミッタＥに対して逆バイアス状態であると、寄生トラン
ジスタのコレクタＣＬとエミッタＥＬが順方向にバイア
スされた状態になり、寄生トランジスタが動作する。こ
の結果、上述のトランジスタのエミッタＥからベースＢ
に流れる電流Ｉ＝Ｓが増加し、トランジスタのベースＢ
−エミッタＥ間に与えられる逆バイアスが十分に印加さ
れないようになる。このことにより、トランジスタにお
いてｄ Ｖ／ｄｔ耐量の低下や、耐圧の低下が生じ、ま
た逆バイアス電源の損失の増加をも当然引き起こす。At this time, if the base B of the transistor is in a reverse bias state with respect to the emitter E of the transistor, the collector CL and emitter EL of the parasitic transistor will be in a forward bias state, and the parasitic transistor will operate. As a result, from the emitter E to the base B of the transistor mentioned above,
The current I=S flowing in increases, and the base of the transistor B
- The reverse bias applied between the emitters E is not sufficiently applied. This causes a decrease in the dV/dt withstand capability and a decrease in the withstand voltage of the transistor, and also naturally causes an increase in the loss of the reverse bias power supply.
それゆえに、この発明の目的は、上述の欠点を除去し、
フライホイールダイオードとトランジスタの複合化によ
って生ずる寄生ラテラルトランジスタの効果を低減した
半導体装置を提供することである。It is therefore an object of this invention to eliminate the above-mentioned drawbacks and
It is an object of the present invention to provide a semiconductor device in which the effect of parasitic lateral transistors caused by combining a flywheel diode and a transistor is reduced.
［問題点を解決するための手段］
奇生トランジスタによる効果を低減させるためには、ラ
テラル寄生トランジスタの電流増幅率を低減させればよ
い。そこで、この発明においては次のような手段を設け
る。すなわち、トランジスタのベース領域とダイオード
の７ノード領域との間に第１伝導型のコレクタ領域に新
たに独立の第２伝導型の＠域を設ける。この独立の第２
伝導型の半導体領域は少なくとも１個でよいが、複数個
設ければ寄生トランジスタのＴＲＦ−増幅率を低減させ
るにはさらに有効な手段となる。[Means for Solving the Problems] In order to reduce the effect of parasitic transistors, the current amplification factor of the lateral parasitic transistors may be reduced. Therefore, in the present invention, the following means are provided. That is, a new independent @ region of the second conductivity type is provided in the collector region of the first conductivity type between the base region of the transistor and the 7-node region of the diode. This second independence
At least one conductive type semiconductor region is sufficient, but providing a plurality of conductive type semiconductor regions becomes a more effective means for reducing the TRF-amplification factor of the parasitic transistor.
この独立の第２伝導型の半導体領域を形成する際の条件
として、トランジスタのエミッターコレクタ間またはダ
イオードの７ノ一ドーカソード間に逆バイアスが印加さ
れたとき各接合より延びる空乏層が到達し得る範囲に独
立の第２伝導型半導体領域を配置することが必要である
。この条件により、高耐圧トランジスタ（コレクターベ
ース間にガードリングを必要とする程度の）において、
高耐圧特性を損なうことなく目的とする効果を得ること
が可能となる。The conditions for forming this independent semiconductor region of the second conductivity type are the range that the depletion layer extending from each junction can reach when a reverse bias is applied between the emitter-collector of a transistor or between the 7-d cathode of a diode. It is necessary to arrange an independent semiconductor region of the second conductivity type. Due to this condition, in high voltage transistors (to the extent that a guard ring is required between the collector and base),
It becomes possible to obtain the desired effect without impairing high voltage resistance characteristics.
さらに、この独立の第２伝導型の半導体領域を形成する
ことは、従来の技術で十分可能であり、特に、ガードリ
ング形成時に必要部分に同時に形成すれば工程を追加す
る必要もない。Further, it is possible to form this independent semiconductor region of the second conductivity type using conventional techniques, and there is no need to add any additional steps, especially if it is formed in a necessary portion at the same time as forming the guard ring.
し作用］
ラテラル寄生トランジスタの電流増幅率は、トランジス
タのコレクタを奇生１−ランジスタのベースとしたとき
、ダイオードのアノードである奇生トランジスタのエミ
ッタとトランジスタのベースである寄生トランジスタの
コレクタとに挾まれるラテラル寄生トランジスタのベー
ス幅Ｗしの二乗に大きく依存し、その関係は逆比例の関
係である。 □′したがって、この発明の特徴で
あるトランジスタのベースとダイオードのアノードとに
挾まれた第１伝導型半導体領域内に形成される独立の第
２伝導型半導体層はキャリアの流れを阻止する機能を有
するので、ラテラル寄生トランジスタのベース幅Ｗしを
実質的に長くすることにより寄生トランジスタの電流増
幅率を小さくすることができる。The current amplification factor of a lateral parasitic transistor is the current amplification factor between the emitter of the parasitic transistor, which is the anode of the diode, and the collector of the parasitic transistor, which is the base of the transistor, when the collector of the transistor is the base of the parasitic transistor. It depends largely on the square of the base width W of the lateral parasitic transistor, and the relationship is inversely proportional. □'Therefore, the independent second conductivity type semiconductor layer formed within the first conductivity type semiconductor region sandwiched between the base of the transistor and the anode of the diode, which is a feature of the present invention, has the function of blocking the flow of carriers. Therefore, by substantially increasing the base width W of the lateral parasitic transistor, the current amplification factor of the parasitic transistor can be reduced.
［発明の実施例］
第１図は、この発明の特徴を最もよく示す半導体装置の
断面構造図である。第１図において、第３因の従来の装
置と同一の領域は同一の符号が付されているが、この発
明の特徴として新たに独立のＰ型頭域１１が設けられる
。[Embodiments of the Invention] FIG. 1 is a cross-sectional structural diagram of a semiconductor device that best illustrates the features of the present invention. In FIG. 1, the same regions as in the conventional device of the third factor are given the same reference numerals, but as a feature of the present invention, an independent P-shaped head region 11 is newly provided.
第５図は、この発明を高耐圧ダーリントントランジスタ
に適用した場合の半導体装置の断面構造図である。以下
、この発明の具体的効果について具体的な数字を挙げて
説明する。第５図に示されるダーリントントランジスタ
において、Ｎ″領域１は比抵抗４０〜５０Ω・ａｍ、厚
みはプレーナの表面より６０μ、Ｎ＋領域１はコレクタ
電極８に接する表面の１１１度はｆ３ ｘ １Ｑ ”
ａｔｏｎｅｓ ／ｃ１ｍ’以上であり、深さ１５０μの
拡散層、Ｐ領域はベースガードリング領域ともに表面濃
度５Ｘ１０＋♂ａｔｏｍｓ ／ｃ１．深さ２５μの拡散
層、Ｎ”ｆｌｐＩｌ、ハ、不純物濃度１Ｘ １Ｑ ”
ａｔｏＩｌｌｓ ／ｅ１ｍ２以上、深さ１０μの拡散
領域である。この発明によるＰ領域は、トランジスタの
ベースとダイオードのアノードに挾まれるＮ−領域に各
々よりマスク寸法上６０μＩｌ１１ｍｌシて形成される
。従来構造の場合のトランジスタのベースと分離された
ダイオードの７ノードの端までの距離はマスク寸法上６
０μｍである。回路構成を第５図に示される回路として
、負荷電流Ｉ、を１５Ａ流した場合の条件で、従来の半
導体装置と本発明による半導体装置におけるエミッター
ベース間に流れる電流ＩＩ！ａを比較す、る。FIG. 5 is a cross-sectional structural diagram of a semiconductor device in which the present invention is applied to a high voltage Darlington transistor. Hereinafter, specific effects of the present invention will be explained by citing specific numbers. In the Darlington transistor shown in FIG. 5, the N'' region 1 has a resistivity of 40 to 50 Ω·am, a thickness of 60 μm from the planar surface, and the N+ region 1 has a surface contacting the collector electrode 8 at an angle of 111 degrees f3 x 1Q”.
atones /c1m' or more, and the surface concentration of both the 150μ deep diffusion layer and the base guard ring region of the P region is 5×10+♂atoms/c1. Diffusion layer with a depth of 25μ, N"flpIl, C, impurity concentration 1X 1Q"
The diffusion region is at least atoIlls/e1m2 and has a depth of 10μ. The P regions according to the present invention are formed by 60 .mu.Il11 ml larger than each of the N- regions sandwiched between the base of the transistor and the anode of the diode on the mask dimension. In the case of the conventional structure, the distance between the base of the transistor and the end of the isolated diode's 7 nodes is 6 due to the mask dimension.
It is 0 μm. With the circuit configuration shown in FIG. 5, the current II! flowing between the emitter base in the conventional semiconductor device and the semiconductor device according to the present invention is under the condition that a load current I of 15 A is applied. Compare a.
第６Ａ図は従来の半導体装置を用いた場合の電流ＩＣＩ
ＩＥＩＩを示し、第６Ｂ図はこの発明による半導体装置
の電流！。、ＩＥＩＩをそれぞれ示す。Figure 6A shows the current ICI when using a conventional semiconductor device.
IEII is shown, and FIG. 6B shows the current of the semiconductor device according to the present invention! . , IEII are shown, respectively.
第６Ａ図、第６Ｂ図から見られるように従来の半導体装
置に比べてこの発明による半導体装置においてはエミッ
ターベース間電流ＩεＢは大幅に低減されていることが
わかる。As can be seen from FIGS. 6A and 6B, it can be seen that the emitter-base current IεB is significantly reduced in the semiconductor device according to the present invention compared to the conventional semiconductor device.
［発明の効果］
以上のように、この発明においては、ダイオード複合ト
ランジスタにおいて、トランジスタのベース領域とダイ
オードのアノード領域との間のコレクタ領域にキャリア
阻止用の領域を新たに設けたので、汀生トランジスタの
ベース領域の幅を実質的に長くすることができる。した
がって、寄生トランジスタの電流増幅率を低減すること
ができ、ダイオード複合トランジスタの（Ｉｖ、／ｄｔ
耐吊および耐圧を高めることができる。[Effects of the Invention] As described above, in the present invention, a carrier blocking region is newly provided in the collector region between the base region of the transistor and the anode region of the diode in the diode composite transistor. The width of the base region of the transistor can be substantially increased. Therefore, the current amplification factor of the parasitic transistor can be reduced, and (Iv, /dt
Can increase hanging resistance and pressure resistance.
第１図はこの発明の特徴を示す半導体装置の断面ＭＩｔ
造図である。第２図はこの発明の一実ａ例である半導体
装置の構造の断面図である。第３図は従来の半導体装置
の構造を示す断面図である。第４図は、第３図の半導体
装置の等価回路図である。
第５図は半導体装置の適用回路の動作を示すための図で
ある。第６Ａ図は従来の半導体装置の特性を示す図であ
る。第６Ｂ図はこの発明による半導体装置の特性を示す
図である。
図において、１はＮ＋コレクタ領域およびダイオードの
カソード領域、２はＮ−コレクタ＠域およびダイオード
のカソード領域、３，３ａ 、３ｂはＰ型ベース領域、
４．４ａ、４１１．４ｃはＮ−型エミッタ領域、５はＰ
型アノード領域、６は高耐圧化のためのガードリング、
７は表面保護のだめの絶縁膜、８はコレクタおよびカソ
ードの電極、９はベース電極、１ｏはエミッタおよびア
ノードの共通の電極、１１はこの発明の特徴である分離
Ｐ型領域である。
なお、図中、同符号は同一または相当部を示す。
代 理 人 大 岩 増 雄：で
乃１図
心２図
躬３図
６４図 心５図
心６Ａ図 ６６８図
手続補正書（自発）
１．事件の表示 特願昭５９−２３０６２３号２、
発明の名称
半導体装置
３、補正をする省
代表者片山仁へ部
４、代理人
５、補正の対象
明細書の発明の詳細な説明の欄および図面の簡単な説明
の欄
６、補正の内容
（１） 明細書第４頁第６行ないしＭ７行の「ブレナ」
を「プレーナ」に訂正する。
（２） ｕ書１６頁Ｍ１２行ｒＵ方向Ｊ ’Ｅ：「逆
方向」に訂正する。
（３） 明細書第９頁第１２行の「第５図」を「第２図
」に訂正する。
（４） 明細書第１２頁第４行ないし第５／Ｉテの「Ｎ
−型エミッタ」を「Ｎ＋型エミッタ」に訂正する。
以上
−Ａ凸１FIG. 1 shows a cross-section MIt of a semiconductor device showing the features of this invention.
It is a drawing. FIG. 2 is a sectional view of the structure of a semiconductor device which is an example of the present invention. FIG. 3 is a cross-sectional view showing the structure of a conventional semiconductor device. FIG. 4 is an equivalent circuit diagram of the semiconductor device of FIG. 3. FIG. 5 is a diagram showing the operation of the applied circuit of the semiconductor device. FIG. 6A is a diagram showing the characteristics of a conventional semiconductor device. FIG. 6B is a diagram showing the characteristics of the semiconductor device according to the present invention. In the figure, 1 is an N+ collector region and a diode cathode region, 2 is an N- collector @ region and a diode cathode region, 3, 3a, and 3b are P-type base regions,
4.4a, 411.4c are N-type emitter regions, 5 is P
type anode area, 6 is a guard ring for high voltage resistance,
7 is an insulating film for surface protection, 8 is a collector and cathode electrode, 9 is a base electrode, 1o is a common electrode for the emitter and anode, and 11 is an isolated P-type region, which is a feature of the present invention. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa: Deno 1 Zushin 2 Zuman 3 Diagram 64 Shin 5 Chushin 6A Diagram 668 Procedural Amendment (Voluntary) 1. Indication of incident Patent application No. 59-230623 2,
Name of the invention: Semiconductor device 3; Department representative Hitoshi Katayama making the amendment; Department 4; Attorney 5; Detailed explanation of the invention column and Brief explanation of drawings column 6 of the specification subject to the amendment; Contents of the amendment ( 1) “Brenna” on page 4, line 6 to line M7 of the specification
is corrected to "plana". (2) Book U, page 16, line M12, rU direction J'E: Correct to "reverse direction". (3) "Figure 5" on page 9, line 12 of the specification is corrected to "Figure 2." (4) “N” in page 12, line 4 to 5/I of the specification
- type emitter" is corrected to "N+ type emitter." Above-A convex 1
Claims (2)
導体基体内に形成され、前記トランジスタのコレクタ領
域と前記ダイオードのカソード領域とが同一の第１伝導
型半導体層を共有し、前記トランジスタのベース領域と
前記ダイオードのアノード領域とが互いに独立した第２
伝導型半導体層で形成され、前記トランジスタの前記ベ
ース領域の表面部の一部に第１伝導型半導体領域からな
るエミッタ領域を有し、前記トランジスタの前記エミッ
タ領域と前記ダイオードのアノード領域とが電気的に接
続される半導体装置であつて、前記トランジスタのベー
ス領域と前記ダイオードのアノード領域とにより挾まれ
た前記トランジスタのコレクタ領域内に前記ベース領域
と前記アノード領域とから分離された第２伝導型半導体
領域が形成された、半導体装置。(1) A bipolar transistor and a diode are formed in the same semiconductor substrate, the collector region of the transistor and the cathode region of the diode share the same first conductivity type semiconductor layer, and the base region of the transistor and the diode The anode region of the
The transistor is formed of a conductive semiconductor layer, and has an emitter region made of a first conductive semiconductor region in a part of the surface of the base region of the transistor, and the emitter region of the transistor and the anode region of the diode are electrically connected to each other. a semiconductor device of a second conductivity type separated from the base region and the anode region in the collector region of the transistor sandwiched between the base region of the transistor and the anode region of the diode; A semiconductor device in which a semiconductor region is formed.
Ｐ型である、特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the first conductivity type is an N type, and the second conductivity type is a P type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23062384A JPS61107773A (en) | 1984-10-30 | 1984-10-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23062384A JPS61107773A (en) | 1984-10-30 | 1984-10-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61107773A true JPS61107773A (en) | 1986-05-26 |
Family
ID=16910673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23062384A Pending JPS61107773A (en) | 1984-10-30 | 1984-10-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61107773A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0480047U (en) * | 1990-11-27 | 1992-07-13 | ||
| JP2008004582A (en) * | 2006-06-20 | 2008-01-10 | Sansha Electric Mfg Co Ltd | Vertical high-speed switching device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5227277A (en) * | 1975-08-25 | 1977-03-01 | Origin Electric Co Ltd | Darlington connction type semiconductor unit |
-
1984
- 1984-10-30 JP JP23062384A patent/JPS61107773A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5227277A (en) * | 1975-08-25 | 1977-03-01 | Origin Electric Co Ltd | Darlington connction type semiconductor unit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0480047U (en) * | 1990-11-27 | 1992-07-13 | ||
| JPH087629Y2 (en) * | 1990-11-27 | 1996-03-04 | 関西日本電気株式会社 | Transistor |
| JP2008004582A (en) * | 2006-06-20 | 2008-01-10 | Sansha Electric Mfg Co Ltd | Vertical high-speed switching device |
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