JPS61107471A - Parallel arithmetic processing device - Google Patents

Abstract

PURPOSE:To permit the limitting of number of a saving buffer for the same of original data for each command by controlling the extent of passing of arithmetic execution of a command within the number of preset commands. CONSTITUTION:Instruction words and operands read from a memory device 5 are sent to operators 7 and 10. An instruction number generator 4 generates an instruction number indicating the conceptual sequence for each instruction each time the instruction is decoded in an instruction decorder 2, and sends it to an instruction number register 8 or 11. Using instruction addresses of instructions which were input through signal conductors 54 and 55 and are currently performing arithmetics in the operators 7 and 10, an instruction difference detecting circuit 50 suspends the execution of the arithmetics, especially writing of the result, in the operator 7 if they satisfies certain conditions. The case of an instruction difference detecting circuit 51 is alike.

Description

Detailed Description of the Invention (Field of Application of the Invention) The present invention relates to a computer, such as a so-called general-purpose computer, in which instructions are conceptually processed one by one. This paper relates to a control method that is important in realizing a method for calculating multiple instructions in parallel.

[Background of the invention]

Among computers that conceptually process instructions one by one, Hitachi's HITA is one of the conventional examples of computers that operate on multiple instructions in parallel using multiple arithmetic units.
There is CS-810. In S-810, two conceptually ordered instructions can be operated on different arithmetic units, so the writing order of the results may be the opposite of the conceptual order.

In IBM's 370 architecture, S-
When a reversal of the writing order of results occurs, as occurs at 810, several problems arise.

This problem arises when conceptually the result of the preceding instruction is written, that is, when the execution of the operation is completed, and when it becomes necessary to interrupt the processing of the subsequent instruction, the memory has already been stored. This arises from the fact that if the result of the subsequent instruction is written to the device, the storage device must be restored to a state in which no result was written by the subsequent instruction, according to the specifications of the architecture. Restoring to the state before the result write was done in this way is called disabling the result write, if the result write could be disabled in order to do this.

Save the field data that will be lost due to writing (this is called original data) in advance, and if it becomes necessary to invalidate it after writing, write the saved original data to the field again. Action is required.

This group of registers for saving original data will be simply referred to as a save buffer. Regarding the number of registers that make up the save buffer, when it becomes necessary to interrupt instruction processing at the point when the operation execution of an arbitrary instruction is completed, the number of registers that make up the save buffer can be changed by the conceptually subsequent instruction that has completed the operation execution first. It is necessary to set the number of lines as necessary because all the original data of the field remains in the save buffer. To do this, conversely, it is necessary to know the maximum value M71 of the number of subsequent instructions whose arithmetic executions are completed first for a certain instruction.

[Purpose of the invention]

An object of the present invention is to have a control means for setting the maximum value of the number of subsequent instructions that complete arithmetic execution to a predetermined value M-1 for a certain instruction, thereby increasing the number of registers in the save buffer. The object of the present invention is to provide a parallel arithmetic processing device that can perform M-1 instructions.

[Summary of the invention]

In order to achieve such an objective, in the present invention, an instruction number indicating the conceptual execution order is generated when each instruction is decoded, and for each instruction, the instruction number and the instruction number of instructions in other operation execution means are generated. , and this is the predetermined value M
The feature is that when the value exceeds -1, execution of the operation of the instruction is suspended.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. 1st
FIG. 1 is a block diagram of a parallel processing device according to the present invention.

Reference numeral 1 denotes an instruction control unit that decodes instruction words, reads operands, etc., and includes an instruction decoder 2, an operand reading device 3, an instruction number generator 4, and the like. 5 is a storage device in which command words, operands, etc. are stored. 6 is an arithmetic unit that performs an operation specified by a command word, and arithmetic units 7. It consists of an instruction number register 8 and an instruction difference detection circuit 50.

9 is also an arithmetic unit similar to 6, and includes an arithmetic unit 1o, an instruction number register 11, and an instruction difference detection circuit 51.

The instruction word read from the storage device 5 is input to the instruction decoder 2 via the signal line 21 and decoded. The operands required for the operation specified by the instruction word are stored by the operand reading device 3 sending an operand reading request to the storage device 5 via the signal line 22 based on the decoding result of the instruction sent from the instruction decoder. Read from bag [5. The operand read from the storage device 5 is sent to the arithmetic unit 7 or 10 via the signal line 23. Among the information obtained as a result of decoding the instruction word by the instruction decoder 2, information necessary for executing the operation is sent to the arithmetic unit 7 or 10 via the signal line 24.

The instruction number generator 4 indicates to each instruction its conceptual order each time the instructions are decoded by the instruction decoder 2.

An instruction number is generated and sent to the instruction number register 8 or 11 via the signal line 25. Instruction number generator 4
initially sets the value 1 as the instruction number for the first instruction to be executed by the instruction processing device, and thereafter increments the value by l each time one instruction is decoded. However, in order to express the instruction number with a finite number of digits, when a suitable constant N is reached, the next instruction number is returned to the value l. This constant N is set to satisfy the following condition (1) using a predetermined natural number M (M≧1) and the number E of computing units (2 in Fig. 1, generally E≧2). do.

N>2・(M+'E-2) ・・・・・・Condition (1
) In this embodiment, it is assumed that both the arithmetic units 7 and 10 are configured to be able to perform arithmetic operations for all instructions. Therefore, if one of the arithmetic units 6 or 9 is vacant (not executing arithmetic operations), the vacant arithmetic unit, and if both the arithmetic units 6 and 9 are vacant, an appropriate one is selected. , the instruction word decoding information and instruction number from the instruction control unit 1, and the corresponding operand from the memory group W15 are set in the set store 1.
I get stabbed. If we consider an implementation in which the configurations of the arithmetic units 7 and 10 are not the same and a specific instruction can be executed only by one of the arithmetic units, then Setup must be configured to be performed on an arithmetic unit that can execute the instruction after the arithmetic unit becomes vacant.

Assuming that instructions are sent to the arithmetic unit 6 from 1 to 2, the arithmetic unit 7 executes the arithmetic operation specified by the instruction word. During this time.

The instruction number register 8 holds the instruction number of the instruction.

When the arithmetic operation in the arithmetic unit 7 is completed, the result is sent to the memory group ffi! via the signal line 52. 5 is written.

Further, when instructions are set up for the arithmetic unit 9, the arithmetic unit 10 executes the arithmetic operation specified by the instruction word. During this time, in the instruction number register 11,
The instruction number of the instruction is held. When the arithmetic operation in the arithmetic unit 10 is completed, the result is transferred to the signal line 53 and the storage device 5.
．． 2□Eyowa 1;

The instruction difference detection circuit 50 receives input via a signal line 54. The instruction number S of the instruction currently being executed by the arithmetic unit 7 is input via the signal line 55 . Using the instruction number T of the instruction being executed by the arithmetic unit 10, the signal line 56 is turned on while the instruction number T satisfies the following condition (2).

If SAT, then M+E-2≧S-T≧M If S<T, then N-(M+E-2)≦T-5: aN-M...Condition (2) While the signal line 56 is on is the calculation execution in the calculation unit 7,
In particular, writing the results will be suspended. For example, in the case of a microprogram-controlled arithmetic unit, this suspension of execution of arithmetic operations can be easily realized using conventional techniques, such as suspending the execution of a microprogram.

Similarly, the instruction difference detection circuit 51 also receives the instruction number T of the instruction being executed by the arithmetic unit 10, which is input via the signal line 55, and the instruction number T of the instruction which is being executed by the arithmetic unit 7, which is input via the signal line 54. Using the command number S of the command, the signal line 57 is turned on while this satisfies the condition obtained by replacing T and S in the above condition (2). While the signal line 57 is on, execution of arithmetic operations in the arithmetic unit 10, especially writing of results, is suspended.

As described above, by appropriately suspending the execution of arithmetic operations in the arithmetic unit 7 or 10 based on the output signal from the instruction difference detection circuit 50 or 51, the instructions after M instructions or more for any given instruction are executed first. Termination becomes impossible for the following reasons.

Let S be the instruction number of the instruction in the arithmetic unit to which the instruction difference detection circuit of interest belongs, let I (S) be the instruction, and check whether I (S) has been executed earlier. The instruction number of the instruction to be executed is T, and the instruction is I (
T).

(1) When instruction I (S) is a conceptual successor to instruction I (T).

In this case, if I (S) is more than M instructions after I (T), it is necessary to suspend the execution of the operation.

a) If the instruction number does not wrap around from N to 1 from the generation of instruction number T to the generation of instruction number S in the instruction number generator 4 In this case, as in (1) a) In addition, S>T, and the instruction number difference ST indicates the number of instruction r (s) with respect to instruction 1 (T).

Therefore, I (S) becomes I (T) from M or M+E-
If the range is within the range up to the second instruction, the first term of condition (2) is satisfied, and the execution of the operation of I (S) is suspended. The reason why the value of S to be held here is not only M but also a value within one interval (M, M+E-2) for ST is as follows. That is, in a certain instruction I(S'), S'-
When T reaches M, the operation of r(s') is suspended, but the instruction setup itself continues as long as there are free arithmetic units.

Generally speaking, there is a possibility that the M-th and subsequent instructions to be held in E-1 arithmetic units excluding the arithmetic unit with instruction I (T) among E arithmetic units may be set up. be. That is, with I (T) as the reference, M
This is because it is necessary to satisfy the suspension condition for the instructions in the range up to the +(E-1)-1=M+E-2nd instruction.

Also, as long as r (T) is executing an operation, instructions after the M+E-2nd instruction from I (T) will not be set up in the arithmetic unit. It is sufficient to set the suspension condition only for those cases.

In this way, if I (S) is a subsequent instruction of I (T) and S>T, then ST≦M+E-2...Equation (1) holds true.

On the other hand, as the value of S-T that satisfies the reservation condition, simply interval 1
:M, the reason why it was not set as a value in a) is that even if S>T, if ST is thicker than M+E-2, as described later,
If I (S) is an instruction that conceptually precedes I (T), and wraparound of instruction number generation occurs between S and T (see (2) below),
)b), so if the execution of the operation is suspended in this case, it should be executed before I (T)! This is because (S) is put on hold, which may cause the processing device to hang up, which is undesirable.

b) When there is a wraparound between the generation of instruction number T and the generation of instruction number S. In this case, as shown in Figure 2 (1) b), it is SAT, and the instruction number difference is T-8. The value N-(T-8) obtained by subtracting this from N indicates the number of the instruction r(s) with respect to the instruction I(T). Therefore, I (S) becomes I (
If T) falls within the range from M to M+E-2nd instruction, then M:5N-(T-3)≦M+E-2...Equation (2) holds true, which means that the second condition of condition (2) This means that the term holds true, and therefore the execution of the operation of I (S) is suspended.

In this way, as long as I (T) is executing an operation, instructions after the M+E-2 instruction from I (T) will not be set up in the arithmetic unit, so in this case, N -(T-5)≦M+E-2 or T-5≧N-(M+E-2) ...Formula (3)
holds true.

Furthermore, in this example, as is clear from the above condition (1), N-(M+E-2)>M+E-2, so from equation (3), in this case T-8>M+E
-2... It can also be seen that equation (4) holds true.

Note that T-8 is N-M as the value of S to be reserved here.
but also the interval (N-(M+E-2)).

The reason why the value is within [1°N-M] and [1°N-M
The reason for not using the values in ) is the same as in item a) above.

(2) When instruction r (s) is a conceptual predecessor instruction of instruction 1 (T) In this case, it is clear that there is no need to suspend the execution of the operation of I (S). However, in this case, the instruction number S
Unless it is confirmed that the above condition (2) is not satisfied, the processing device may hang up, which is undesirable.

a) If there is no wraparound between the generation of instruction number S and the generation of instruction number T In this case, as shown in Figure 2 (2) a), it is SAT, so the above (1) b) However, according to the control of an instruction difference detection circuit attached to an arithmetic unit with instruction I (T), T-5:&M+E-2...
- The fact that equation (5) holds is exactly the same as the reason for equation (1) to hold in (1) a), so it is clear that condition (2) cannot be satisfied.

b) If there is a wraparound between the generation of instruction number S and the generation of instruction number T. In this case, as shown in Figure 2 (2) b), it is SAT, so (1) a above. ), however, according to the control of an instruction difference detection circuit attached to an arithmetic unit with instruction T (I), S−T≧N−(M+E−
2) ...Formula (6) S-T>M+E-2...
- The fact that equation (7) holds is exactly the same as the reason for equation (4) in (1) b) above, so it is clear that condition (2) cannot be satisfied.

For the reasons (1) a), b) and (2) a), b) above, the output of the instruction difference detection circuit is turned on according to condition (2).1. :If the execution of the operation in the corresponding arithmetic unit is suspended accordingly, if the instruction (S) is conceptually more than M instructions after I (T), the operation will be executed after overtaking it. That would be impossible.

In the embodiment shown in FIG. 1, the number E of arithmetic units is 2, but in the embodiment where E is greater than 2, the conditions for suspending the execution of arithmetic operations are as follows. That is, let S be the instruction number currently being executed in the arithmetic unit whose execution is being looked at as to whether or not the execution of the operation is suspended.

The instruction numbers of the maximum E-1 instructions being executed in other E-1 arithmetic units are T, (i=1.2...
′□□1..., E-1), condition (2)
This is a condition that at least one of the E-1 conditions obtained by replacing T with T for each i is satisfied.

〔Effect of the invention〕

According to the present invention, in a parallel arithmetic processing device, the degree of overtaking of instruction execution is set by a preset number of instructions M−1.
Because it can be limited within.

This makes it possible to reduce the number of registers constituting a save buffer for saving the original data of each instruction, which is necessary when writing and invalidating the result of the execution of an instruction, to at most M-1 instructions. This is effective in suppressing unnecessary increase in hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a parallel arithmetic processing device to which the present invention is applied, and FIG. 2 is a diagram showing instruction numbers and ranges in which conditions for suspending arithmetic execution are met. 1... Instruction control unit, 4... Instruction number generator,
5... Storage device, 6, 9... Arithmetic unit, 7,
10... Arithmetic unit, 8, 11... Instruction number register,
50゜Atsushi #mouth

Claims (1)

[Claims] 1. In a data processing device in which instructions are conceptually processed one by one and the results are conceptually written sequentially to a storage device, a plurality of instructions can be executed in parallel. Detecting when the instruction being executed by each operation execution means is a predetermined number of instructions or more later than the instruction being executed by the other operation execution means. and the instruction I being executed by the operation execution means A by means of the detection means is an instruction that is the number of instructions or more later than the instruction being executed by some other operation execution means B. A parallel arithmetic processing device comprising an arithmetic execution suspending means for suspending the arithmetic execution of the instruction I by the arithmetic execution means A while the instruction I is being detected. 2. It has an instruction number generation means for generating an instruction number representing a conceptual execution order for each instruction, and holds the instruction number of the instruction being executed by the operation execution means in correspondence with each operation execution means. The detecting means detects based on the difference between the instruction number of the instruction being executed by each operation execution means and the instruction number of the instruction being executed by the other operation execution means. 2. The parallel arithmetic processing device according to claim 1, characterized in that: