JPS61105798A - P rom ic - Google Patents

P rom ic

Info

Publication number
JPS61105798A
JPS61105798A JP59227375A JP22737584A JPS61105798A JP S61105798 A JPS61105798 A JP S61105798A JP 59227375 A JP59227375 A JP 59227375A JP 22737584 A JP22737584 A JP 22737584A JP S61105798 A JPS61105798 A JP S61105798A
Authority
JP
Japan
Prior art keywords
write
data
memory cell
write data
product name
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59227375A
Other languages
Japanese (ja)
Inventor
Tadashi Takizawa
正 滝沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59227375A priority Critical patent/JPS61105798A/en
Publication of JPS61105798A publication Critical patent/JPS61105798A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable a storing of write-data names correspondent to the write data in a PROM (programmable read only memory) IC by providing a circuit dedicated to the write/read control to the write-data-name storing memory cell. CONSTITUTION:The write-data-name storing memory cell 7 is provided in the PROM memory cell 3. The writing in and reading out from the cell 7 are controlled through the decoder and the selecting circuit 8 that are dedicated to the cell 7. With this configuration, there is no necessity of writing names by imprinting and reading them out, and thus the PROM IC is made able to store the write names correspondent to the write data which are also able to be read out.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はF ROM IC(PROGRAMMABLE
READ ONLYMEMORY IC)の回路構成に
関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is directed to F ROM IC (PROGRAM MABLE)
This relates to the circuit configuration of the READ ONLY MEMORY IC.

(従来の技術) 従来、F ROM ICは第2図に示すように、行アド
レスデコーダ12列アドレスデコーダ2.メモリセル3
.データセレクタ4.出力制御回路5.出方2フフフ ル3にはアドレス信号A。−An,An+1〜AlTl
に対応したデータがマスター側よシ書き込まれており、
それ以外の書込データ品名等の情報を格納することは、
不可能であった。その為これらのP I’(OMICは
通常、書込データに対応する書込データ品名をF RO
M ICパッケージ表面に人手により捺印表示し、)9
ツケージに実装されている。
(Prior Art) Conventionally, an F ROM IC, as shown in FIG. 2, has a row address decoder, 12 column address decoders, and 2. memory cell 3
.. Data selector 4. Output control circuit 5. Output 2 fufuful 3 has address signal A. -An, An+1 ~ AlTl
The corresponding data is written to the master side,
Storing other write data such as product name, etc.
It was impossible. Therefore, these P I' (OMIC usually uses the write data product name corresponding to the write data as FRO
(The stamp is manually stamped on the surface of the MIC package.)9
Implemented in the package.

(発明が解決しようとする問題点) ところが、F ROM ICの場合、多品種少量生産の
為、以下の様な欠点がある。
(Problems to be Solved by the Invention) However, in the case of FROM IC, there are the following drawbacks due to high-mix, low-volume production.

第1には、捺印ミスによシ、書込データと書込データ品
名が異なる場合も多々あり、パッケージ検査または装置
検査にて検出され交換工数を増加させる原因となってい
る。
First, there are many cases where the written data and the written data product name are different due to a stamping error, which is detected during package inspection or equipment inspection, and causes an increase in the number of man-hours for replacement.

第2には捺印の場合、文字が不規則であり、かつ不鮮明
となる為、その後の検査、製造工程に於ける自動化シス
テムの構築がしにくい。
Second, in the case of stamping, the characters are irregular and unclear, making it difficult to construct an automated system for subsequent inspection and manufacturing processes.

第3にはマスターICとして使用する場合、管理が不充
分であると、前記のように捺印表示が不鮮明となり、他
のマスターICと区別が出来なく、使用不能となる。
Thirdly, when used as a master IC, if management is insufficient, the stamp display becomes unclear as described above, making it impossible to distinguish it from other master ICs and making it unusable.

本発明の目的は、書込データと対応する書込データ品名
を格納出来るようにしたF ROM ICを提供するこ
とにある。
An object of the present invention is to provide a FROM IC that can store write data and the corresponding write data product name.

(問題点を解決するための手段) 本発明は書込データ品名を格納する為の複数ワードのメ
モリセルと、そのメモリセルに対するデータ書込及び読
出しを制御する回路を備えていることをη青黴とするF
 ROM ICである。
(Means for Solving the Problems) The present invention includes a plurality of word memory cells for storing write data product names, and a circuit for controlling data writing and reading with respect to the memory cells. F
It is a ROM IC.

(実施例) 次に、本発明の実施例について図面を参照して詳細に説
明する。
(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

第1図は本発明に係るF ROM ICの回路構成を示
すO 第1図に於いて、F ROM ICはアドレス信号An
4−1〜Amで構成される行アドレスデコーダ1がメモ
リセル3に接続されている。また、アドレス信弓Am−
2〜Amと選択信号■8により構成されるデコーダ&選
択回路8は、前記メモリセル3に個別されている8ワー
ド構成の書込データ品名格納用メモリセルフに接続され
ている。
FIG. 1 shows the circuit configuration of the F ROM IC according to the present invention. In FIG. 1, the F ROM IC has an address signal An
A row address decoder 1 composed of 4-1 to Am is connected to the memory cell 3. Also, the address Shinyumi Am-
A decoder & selection circuit 8 constituted by 2 to Am and a selection signal 8 is connected to a memory cell for storing a write data product name of 8 words, which is provided individually in the memory cell 3.

前記メモリセル3及び書込データ品名格納用メモリ7に
1、データセレクタ4が接続されており、これにはアド
レス信号A。−Anで構成される列アドレスデコーダ2
が接続されている。
A data selector 4 is connected to the memory cell 3 and the memory 7 for storing the write data product name, and an address signal A is connected to this. -Column address decoder 2 consisting of An
is connected.

また、出力バッファ回路6には前記データセレクタ4と
出力制御回路5が接続されており、読出し及び書込デー
タを制御している。
Further, the data selector 4 and the output control circuit 5 are connected to the output buffer circuit 6, and control read and write data.

次に本発明に係るF ROM ICの動作を説明する。Next, the operation of the FROM IC according to the present invention will be explained.

デコーダ&選択回路8に於いて、選択信号TSがII 
OI+レベルの場合、アドレス信号Am−、〜Amニよ
り、8ワードから成る書込データ品名格納用メモリセル
フのいずれかのワードが選択される。
In the decoder & selection circuit 8, the selection signal TS is
In the case of the OI+ level, one of the words of the memory cell for storing the write data product name consisting of 8 words is selected from the address signals Am- to Am-.

寸だ、列アドレスデコーダ2へのアドレス信号Ao−A
n及びデータセレクタ4によりビット線が選択され、か
つ出力制御信号C及び出力制御回路5により、書込デー
タ品名格納メモリセルフに対する書込、読出しが可能と
なる。
Address signal Ao-A to column address decoder 2
The bit line is selected by n and the data selector 4, and the output control signal C and the output control circuit 5 enable writing to and reading from the write data product name storage memory self.

選択信号I8が“1″ルベルの場合には、書込データ品
名格納用メモリセルフは非選択となり、本来の書込デー
タ用のメモリセル3が選択される。
When the selection signal I8 is level "1", the memory cell for storing the write data product name is not selected, and the memory cell 3 for the original write data is selected.

尚、書込及び読出し方式に関しては従来のF ROMI
Cと同様の為、ここでは説明を省略する。
Regarding the writing and reading methods, the conventional F ROMI
Since it is similar to C, the explanation will be omitted here.

次に、本発明に係るF ROM ICの使用例を説明す
る。まずP ROM IC書込装置に書込データ及びそ
のデータに対応する書込データ品名が格納されていると
する。前記P ROM IC書込装置にF ROM I
Cを挿入し、書込動作を開始すれば、最初に書込データ
がメモリセル3に書き込捷れ、良の場合には書込データ
品名格納用メモリセルフが選択され、書込データ品名を
書き込み終了する。
Next, a usage example of the F ROM IC according to the present invention will be explained. First, it is assumed that write data and a write data product name corresponding to the data are stored in the PROM IC writing device. F ROM I in the P ROM IC writing device
When C is inserted and the write operation is started, the write data is written to memory cell 3 first, and if the data is good, the memory cell for storing the write data product name is selected, and the write data product name is stored. Writing ends.

岩込後のF ROM ICは自動化された捺印工程にて
捺印表示する場合、書込データ品名格納用メモリセルフ
の内容を読み出し、それに対応した捺印を実施すれば捺
印ミス等も無く、多品種少量生産に効果がある。
When stamping the F ROM IC after Iwakomi in an automated stamping process, if the contents of the memory self for storing the written data product name are read and the corresponding stamp is performed, there will be no stamping mistakes, and a wide variety of products in small quantities can be produced. It has an effect on production.

また、その後PROMICのファンクション及びAC特
性試験を実施する場合でも、書込データ品名の読出しに
より必要な試験データを索引し、F ROMIC試験装
置に入力する等の自動化がしやすくなり人手介在による
ミスの低減が可能となる。
In addition, even when performing PROMIC function and AC characteristic tests afterwards, it is easier to automate the process by reading the written data product name to index the necessary test data and inputting it into the F ROMIC test equipment, thereby reducing errors caused by manual intervention. reduction is possible.

前記以外に、・やソケージ実装後の電気検査に於いても
、書込データ品名の読み出しのみで、実装位置データの
版数等の確認により、実装されているF ROM IC
の保証が可能となる。
In addition to the above, during the electrical inspection after mounting the socket, the mounted F ROM IC can be inspected by simply reading the written data product name and checking the version number of the mounting position data.
can be guaranteed.

(発明の効果) 本発明は以」二説明したように書込データ品名格納用メ
モリセルとそのメモリセルに対するデータ書込及び読出
しを制御する回路とを備えたため、F ROM IC特
有の多品種少量生産に適した自動化システムを容易に実
現することができ、・クツケージ実装後の電気検査時に
於いては書込データ品名の読出しのみで、実装位置及び
書込データ版数等を確認し実装されているF ROM 
ICを保証することができる効果を有するものである。
(Effects of the Invention) As explained below, the present invention includes a memory cell for storing the product name of write data and a circuit for controlling data writing and reading to the memory cell, so that it is possible to reduce the number of products and products that are unique to F ROM ICs. An automated system suitable for production can be easily realized. - During electrical inspection after shoe cage mounting, the mounting position and written data version number etc. can be confirmed by simply reading the written data product name. F ROM
This has the effect of guaranteeing the IC.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明に係るF ROM ICの回路構成図
、第2図は従来のF ROM ICの回路構成図である
。 1・・・行アドレスデコーダ、2・・・列アドレスデコ
ーダ、3・・・メモリセル、4・・・データデコーダ、
5・・・出力制御回路、6・・・出力バッファ回路、7
・・・書込データ品名格納用メモリセル、8・・・デコ
ーダ&選択回路 亮1図 0ぴ      071 第2図
FIG. 1 is a circuit diagram of an F ROM IC according to the present invention, and FIG. 2 is a circuit diagram of a conventional F ROM IC. 1... Row address decoder, 2... Column address decoder, 3... Memory cell, 4... Data decoder,
5... Output control circuit, 6... Output buffer circuit, 7
...Memory cell for storing write data product name, 8...Decoder & selection circuit Ryo 1 Figure 0 pi 071 Figure 2

Claims (1)

【特許請求の範囲】[Claims] (1)書込データ品名を格納するための複数ワードのメ
モリセルと、そのメモリセルに対するデータ書込及び読
出しを制御する回路とを備えていることを特徴とするP
ROMIC。
(1) A P characterized by comprising a memory cell of multiple words for storing the write data product name and a circuit for controlling data writing and reading to the memory cell.
ROMIC.
JP59227375A 1984-10-29 1984-10-29 P rom ic Pending JPS61105798A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59227375A JPS61105798A (en) 1984-10-29 1984-10-29 P rom ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59227375A JPS61105798A (en) 1984-10-29 1984-10-29 P rom ic

Publications (1)

Publication Number Publication Date
JPS61105798A true JPS61105798A (en) 1986-05-23

Family

ID=16859819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59227375A Pending JPS61105798A (en) 1984-10-29 1984-10-29 P rom ic

Country Status (1)

Country Link
JP (1) JPS61105798A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6421952A (en) * 1987-07-16 1989-01-25 Nec Corp Read-only memory code number verification circuit
JPS6427097A (en) * 1987-07-23 1989-01-30 Mitsubishi Electric Corp Mask rom device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6421952A (en) * 1987-07-16 1989-01-25 Nec Corp Read-only memory code number verification circuit
JPS6427097A (en) * 1987-07-23 1989-01-30 Mitsubishi Electric Corp Mask rom device

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