JPS61104670A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS61104670A JPS61104670A JP22704284A JP22704284A JPS61104670A JP S61104670 A JPS61104670 A JP S61104670A JP 22704284 A JP22704284 A JP 22704284A JP 22704284 A JP22704284 A JP 22704284A JP S61104670 A JPS61104670 A JP S61104670A
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- thin film
- electrode material
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000010408 film Substances 0.000 claims abstract description 66
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 24
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 15
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 15
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 11
- 239000007772 electrode material Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 230000001681 protective effect Effects 0.000 claims description 17
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 abstract description 10
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 10
- 229910052682 stishovite Inorganic materials 0.000 abstract description 10
- 229910052905 tridymite Inorganic materials 0.000 abstract description 10
- 238000000354 decomposition reaction Methods 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 4
- 229910001120 nichrome Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は薄膜トランジスタの製造方法、詳しくはアモル
ファスシリコン（ａ−５ｉ） 薄膜トランジスタの製造
において、同トランジスタ上に二酸化シリコン（５ｉＯ
ｚ ）膜を成膜することによって、後にプラズマを用い
てなされる工程においてプラズマによる前記トランジス
タのチャンネル部の損傷を防止しうる薄膜トランジスタ
の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film transistor, specifically, in manufacturing an amorphous silicon (a-5i) thin film transistor, silicon dioxide (5iO
z) The present invention relates to a method for manufacturing a thin film transistor that can prevent damage to the channel portion of the transistor caused by plasma in a subsequent step using plasma by forming a film.
イメージセンサは一般に、光を電気的信号に変換するア
モルファスシリコンダイオードと、それをスキャンする
スイッチング用アモルファスシリコン薄膜トランジスタ
とによって構成される。そして、本発明はかかるａ−３
ｉ薄膜トランジスタの改良に関するものである。Image sensors are generally constructed from an amorphous silicon diode that converts light into an electrical signal and an amorphous silicon thin film transistor for switching that scans the diode. And, the present invention provides such a-3
This invention relates to improvements in thin film transistors.
ａ−５ｉ薄膜）・ランジスタを作った後に、例えばイン
パーク構成のために負荷抵抗、ダイオードなどを作ると
き、ａ−３ｔ膜をプラズマエツチングすることが行われ
る。そのときに、ゲート電極の上の部分がプラズマによ
って損傷を受け、薄膜トランジスタの特性が劣化する問
題がある。After making the transistor (a-5i thin film), plasma etching of the a-3t film is performed, for example when making load resistors, diodes, etc. for in-park configurations. At that time, there is a problem that the upper part of the gate electrode is damaged by the plasma, and the characteristics of the thin film transistor are deteriorated.
本発明は、上記問題点を解決するａ−５ｉ薄ＩＩ史１−
ランシスタの製造方法を提供するもので、その手段は、
アモルファスシリコン薄膜トランジスタの製造において
、該１−ランジスタ上に保護膜を成膜することを特徴と
する薄膜トランジスタの製造方法によってなされ、前記
保護膜は、グロー放電により形成された二酸化シリコン
膜を下層とし、その上部にグロー放電またはスパッター
により二酸化シリコン膜を形成することにより２Ｎの保
護膜とするものであり、該方法は、絶縁基板上にゲート
電極を形成する工程、全面にケート絶縁膜、活性層、チ
ャンネル部保護絶縁膜、を順に成膜する工程、前記ゲー
ト電極に対応するレシスＩ・膜をマスクにチャンネル部
保護糸色に矛映をエツチングする工程、オーミックコン
タク１−を形成しその上にソース、ドレイン電極月を被
着しリフトオフ法番こよりチャンネル部のレジスト膜を
除去する工程、電極相とオーミックコンタクト、活性層
を工・ノチングしてこれらのメサ構造を作る工程、全面
に保護膜を成膜しそれをパターニングする工程、を含む
ことを特徴とするものである。The present invention solves the above problems.
Provides a method for manufacturing Lancista, the means of which are:
In manufacturing an amorphous silicon thin film transistor, the method is performed by forming a protective film on the transistor, the protective film having a silicon dioxide film formed by glow discharge as an underlying layer; A 2N protective film is formed by forming a silicon dioxide film on the top using glow discharge or sputtering. A step of sequentially forming a protective insulating film for the channel portion, a step of etching a discrepancy in the protective thread color of the channel portion using the Resis I film corresponding to the gate electrode as a mask, forming an ohmic contact 1-, and forming a source layer on it. The process of depositing the drain electrode and removing the resist film on the channel part using the lift-off method, the process of etching and notching the electrode phase, ohmic contact, and active layer to create these mesa structures, and forming a protective film on the entire surface. and patterning it.
本発明は、ａ−３ｉ薄膜トランジスタが後工程において
プラズマによるＨ１傷を受けることを防止する方法の提
供を目的とするもので、薄膜１−ランジスク上に５ｉ０
２の保護膜を、グロー放電分解法またはスパックにより
成膜することにより、ケーＩ−チャンネル部を完全に保
護するものである。The purpose of the present invention is to provide a method for preventing a-3i thin film transistors from being subjected to H1 scratches caused by plasma in subsequent processes.
By forming the protective film No. 2 by the glow discharge decomposition method or spucking, the K-I channel portion is completely protected.
以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図に本発明の方法によって作られたａ−５ｔ薄膜ト
ランジスクが断面図で示され、同図において、１は絶縁
性基板（例えばガラス基板）、２はニッケル・クロム（
ＮｉＣｒ） 、クロム（Ｃｒ）またはモリブデン（ＭＯ
）で作ったゲート電極、３はシリコン窒化膜（Ｓｉ３Ｎ
＋＋膜）またはＳｉＯ２膜で構成される絶縁膜、４はａ
−５ｉの活性層、５はＳｉＯ２膜のチャンネル部保護膜
、７はオーミックコンタクト用のｎ＋ａ−５ｔ膜、８ａ
はドレイン電極、８ｂはソース電極、９はＳｉＯ２膜、
をそれぞれ示す。図示の薄膜トランジスタにおいては、
ゲート電極２の上方部分がＳｉＯ２膜によって二重に保
護されているので、後の工程において用いるプラズマに
よるチャンネル部の損傷が防止され、静特性の劣化が回
避される。FIG. 1 shows a cross-sectional view of an A-5T thin film transistor manufactured by the method of the present invention, in which 1 is an insulating substrate (for example, a glass substrate), 2 is a nickel chromium
NiCr), chromium (Cr) or molybdenum (MO
), 3 is a silicon nitride film (Si3N
++ film) or an insulating film composed of SiO2 film, 4 is a
-5i active layer, 5 is SiO2 film channel protection film, 7 is n+a-5t film for ohmic contact, 8a
is a drain electrode, 8b is a source electrode, 9 is a SiO2 film,
are shown respectively. In the illustrated thin film transistor,
Since the upper portion of the gate electrode 2 is doubly protected by the SiO2 film, the channel portion is prevented from being damaged by plasma used in later steps, and deterioration of static characteristics is avoided.
次に、第２図の断面図を参照して本発明の方法を実施す
る工程について説明する。Next, steps for carrying out the method of the present invention will be explained with reference to the cross-sectional view of FIG.
第２図ｆａｔ参照ニ
ガラス基板１上にゲート電極材を被着し、それをパター
ニングしてゲート電極２を形成する。Referring to FIG. 2, a gate electrode material is deposited on a glass substrate 1 and patterned to form a gate electrode 2.
第２図（ｂｌ参照：
全面ムこ、ゲート絶縁膜（ＳｉＯ２膜またはシリコン窒
化膜）３、ａ−３ｉの活性層４、ＳｉＯ２のチャンネル
部保護膜５を、グロー放電分解法により連続成膜する。Figure 2 (see BL): A gate insulating film (SiO2 film or silicon nitride film) 3, an a-3i active layer 4, and an SiO2 channel protective film 5 are successively formed by glow discharge decomposition method. .
第２図（Ｃ１参照：
チャンネル部をパターニングするためにレジスト膜を全
面に塗布し、それを露光、現像してゲート電極の寸法に
対応するレジスト膜１０を作る。FIG. 2 (See C1: To pattern the channel portion, a resist film is applied to the entire surface, exposed and developed to form a resist film 10 corresponding to the dimensions of the gate electrode.
第２図Ｆｄｌ参照ニ
レジスト膜１０をマスクにして、 ５ｉ０２の保護膜５
を選択エツチングする。Refer to FIG. 2 Fdl Using the resist film 10 as a mask, protect the protective film 5 of 5i02.
Select and etch.
第２図（Ｑｌ参照ニ
オーミックコンタクト用のｎ” ａ−３ｔ膜７をグロー
放電分解法により成膜し、ＮｉＣｒ、 Ｔｉ、またはＡ
Ａ’の電極材を被着し、ドレイン電極８ａ、ソース電極
８ｂをリフトオフ法で形成する。従って、レジスト膜１
０の上に被着していたｎ＋ａ−５ｔ膜と電極材は、レジ
スト膜と共に除去される。FIG. 2 (see Ql) An n''a-3t film 7 for niohmic contact was formed by glow discharge decomposition method, and NiCr, Ti, or A
An electrode material A' is deposited, and a drain electrode 8a and a source electrode 8b are formed by a lift-off method. Therefore, resist film 1
The n+a-5t film and electrode material deposited on the resist film are removed together with the resist film.
第２図（ｆ）参照：
ＮｉＣｒ等の電極材をエツチング除去し、次いでｎ ４
ａ−３ｉｌｐ５Ｊ、 ａ−５ｉｌＱもエツチングして、
図示の活性層、ｎ”型層、電極材のメサ型構造を作る。Refer to FIG. 2(f): The electrode material such as NiCr is removed by etching, and then n4
Also etched a-3ilp5J and a-5ilQ,
A mesa-type structure of an active layer, an n'' type layer, and an electrode material as shown in the figure is made.
第２図ｆｇ）参照：
次に、薄膜トランジスタ保護膜として５ｉＯ２１１Ｒ９
を全面にグロー放電分解法またはスパッタで成膜する。See Figure 2 fg): Next, as a thin film transistor protective film, 5iO211R9
A film is formed on the entire surface by glow discharge decomposition or sputtering.
以上の工程力ｑ、冬った後に、ドライエツチングまたは
ウェットエツチングで５ｉＯ２ＩＱ ９をエツチングす
ると、第１図に示されるＳｉＯ２膜で保護された薄膜ｌ
・ランジスタが完成する。When the 5iO2IQ 9 is etched by dry etching or wet etching after wintering using the above process power q, the thin film l protected by the SiO2 film shown in Fig. 1 is formed.
・Ran resistor is completed.
以上説明したように本発明によれば、アモルファスシリ
コン薄膜トランジスタ上に５ｉ０２膜を設けることによ
り、（友のプラズマを用いる工程において当該トランジ
スタのチャンネル部の損傷が防止され、静特性の安定し
た薄膜トランジスタが提供される。そして、かかる薄膜
］・ランジスタは、大面積デバイス例えば液晶駆動用の
トランジスタ、シフトレジスタ等に応用可能である。As explained above, according to the present invention, by providing a 5i02 film on an amorphous silicon thin film transistor, damage to the channel portion of the transistor is prevented during the process using plasma, and a thin film transistor with stable static characteristics is provided. Such thin film transistors can be applied to large-area devices such as transistors for driving liquid crystals, shift registers, and the like.
第１図は本発明実施例の断面図、第２図（ａｌないしく
ｇ）は第１図の実施例を形成する工程におりるその要部
の断面図である。
図中、１はガラス基板、２はケート電極、３はゲート絶
縁膜、４ば活性層、５ばチャンネル部保護絶縁膜、７は
オーミックコンタクＩ・（ｎ” ａ−５ｉＩＮＮ） 、
８ａはｌ・レイン電極、８ｂはソース電極、９はｓ；ｏ
２１１央（保護膜）、１０はレジスト膜、をそれぞれ示
す。
特 許 出１頭人 富士通株式会社’７：ＴＥＴ下。FIG. 1 is a cross-sectional view of an embodiment of the present invention, and FIG. 2 (al to g) is a cross-sectional view of essential parts of the embodiment of FIG. 1 in the process of forming it. In the figure, 1 is a glass substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is an active layer, 5 is a channel part protective insulating film, 7 is an ohmic contact I・(n''a-5iINN),
8a is l/rain electrode, 8b is source electrode, 9 is s;o
211 indicates a protective film, and 10 indicates a resist film. Patent: 1 person Fujitsu Limited '7: Under TET.
Claims (3)
おいて、該トランジスタ上に保護膜を成膜することを特
徴とする薄膜トランジスタの製造方法。(1) A method for manufacturing a thin film transistor, which comprises forming a protective film on the amorphous silicon thin film transistor.
化シリコン膜を下層とし、その上部にグロー放電または
スパッターにより二酸化シリコン膜を形成することによ
り２層の保護膜とすることを特徴とする特許請求の範囲
第１項記載の方法。(2) A patent characterized in that the protective film is a two-layer protective film by forming a silicon dioxide film formed by glow discharge as a lower layer and forming a silicon dioxide film on top thereof by glow discharge or sputtering. The method according to claim 1.
ゲート絶縁膜、活性層、チャンネル部保護絶縁膜、を順
に成膜する工程、前記ゲート電極に対応するレジスト膜
をマスクにアモルファスシリコン膜とチャンネル部保護
絶縁膜をエッチングする工程、オーミックコンタクトを
形成しその上にソース、ドレイン電極材を被着しリフト
オフ法によりチャンネル部のレジスト膜を除去する工程
、電極材とオーミックコンタクト、活性層をエッチング
してこれらのメサ構造を作る工程、全面に保護膜を成膜
しそれをパターニングする工程、を含むことを特徴とす
る特許請求の範囲第１項記載の方法。(3) A step of forming a gate electrode on an insulating substrate, a step of sequentially forming a gate insulating film, an active layer, and a channel protection insulating film on the entire surface, and forming an amorphous silicon film using a resist film corresponding to the gate electrode as a mask. and a step of etching the protective insulating film for the channel region, a step of forming an ohmic contact, depositing the source and drain electrode materials thereon, and a step of removing the resist film of the channel region using a lift-off method, and a step of etching the electrode material, ohmic contact, and active layer. 2. The method according to claim 1, comprising the steps of etching to form these mesa structures, and forming a protective film over the entire surface and patterning it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22704284A JPS61104670A (en) | 1984-10-29 | 1984-10-29 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22704284A JPS61104670A (en) | 1984-10-29 | 1984-10-29 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61104670A true JPS61104670A (en) | 1986-05-22 |
Family
ID=16854610
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22704284A Pending JPS61104670A (en) | 1984-10-29 | 1984-10-29 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61104670A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139069A (en) * | 1984-12-10 | 1986-06-26 | Fuji Xerox Co Ltd | Thin-film transistor and manufacture thereof |
-
1984
- 1984-10-29 JP JP22704284A patent/JPS61104670A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139069A (en) * | 1984-12-10 | 1986-06-26 | Fuji Xerox Co Ltd | Thin-film transistor and manufacture thereof |
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