JPS6110263A - Hybrid ic - Google Patents
Hybrid icInfo
- Publication number
- JPS6110263A JPS6110263A JP59132465A JP13246584A JPS6110263A JP S6110263 A JPS6110263 A JP S6110263A JP 59132465 A JP59132465 A JP 59132465A JP 13246584 A JP13246584 A JP 13246584A JP S6110263 A JPS6110263 A JP S6110263A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- multilayer wiring
- lead frame
- wiring substrate
- hybrid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
、産１ユ、ｌす１分！
この発明は近年益々小型化、多機能化、高密度実装化が
要求されているハイブリッドＩＣに関し、特にリードフ
レームを使用した構造のハイブリッドＩＣに関する。[Detailed description of the invention] , 1 yu, 1 minute! The present invention relates to hybrid ICs, which are increasingly required to be smaller, more multifunctional, and more densely packaged in recent years, and particularly to hybrid ICs having a structure using a lead frame.
従未皇肢血
現在一般的なハイブリッドＩＣは、配線や抵抗を印刷し
たセラミック基板上にＩＣペレットや個別半導体ペレッ
ト、コンデンサなどのチップ部品をマウントしてワイヤ
ボンディングにより接続した構造であるが、このハイブ
リッドＩＣは一般のモノリシックＩＣに比べ信頼性が低
い、生産性が劣る、高コスト化する、外形の標準化が雌
しくでＩＣ自動実装上不利であるといった問題を有して
いた。Currently common hybrid ICs have a structure in which chip parts such as IC pellets, individual semiconductor pellets, and capacitors are mounted on a ceramic substrate printed with wiring and resistors and connected by wire bonding. Compared to general monolithic ICs, hybrid ICs have problems such as lower reliability, lower productivity, higher costs, and poor standardization of external shapes, which is disadvantageous in terms of automatic IC mounting.
上記問題を解決するものとして、リードフレームの能動
素子搭載部、すなわち、ランド部上に複数の種類の半導
体ペレットをマウントして配線し、樹脂モールド成形し
たハイブリッドＩＣが開発されている。このリードフレ
ームを使ったハイブリッドＩＣは、リードフレームの１
つのランド部上に１個のＩＣペレットをマウントして配
線しモールド成形した一般のモノリシックＩＣと同じ製
造ラインで製造できるので、モノリシックＩＣと同様に
生産性、信頼性に優れるが、次の問題を有していた。In order to solve the above problem, a hybrid IC has been developed in which a plurality of types of semiconductor pellets are mounted and wired on the active element mounting part of a lead frame, that is, the land part, and resin molded. A hybrid IC using this lead frame is one of the lead frames.
Since it can be manufactured on the same production line as general monolithic ICs, in which one IC pellet is mounted on two lands, wired, and molded, it has the same productivity and reliability as monolithic ICs, but it also has the following problems: had.
交朋）（′シよ”
（Ａ）リードフレームのランド部上に、複数の半導体ペ
レットをマウントすると、マウントされる半導体ペレッ
トの数や種類の変更に応じたリードフレームの設計が必
要で、リードフレームの標準化が難しく、そのためリー
ドフレームの製作は、安価なプレス抜きよりも高価であ
るにもかかわらず、設計変更容易なエツチングにより行
われており、したがってハイブリッドＩＣの低コスト化
を難しくしていた。(A) When multiple semiconductor pellets are mounted on the land of a lead frame, it is necessary to design the lead frame to accommodate changes in the number and type of semiconductor pellets to be mounted. It is difficult to standardize frames, and as a result, lead frames are manufactured using etching, which is easier to change designs even though it is more expensive than cheaper stamping, making it difficult to reduce the cost of hybrid ICs. .
ＣＢ）リードフレームの１つのランド部上にマウントし
た複数の半導体ペレットと、ランド部周辺近傍から延び
る多数のリードとは、ボンディングワイヤで接続される
が、半導体ベレ・ノドとリドの配置関係上ワイヤに長過
ぎるもの、短か過ぎるもの、２本のワイヤがクロスする
ものなどがあって、ワイヤ垂れ下がりによるランド部へ
のシュート、ワイヤ切れ、ワイヤ同士のショートなどの
トラブルが発生し易く、歩留まりを低くしていた。CB) A plurality of semiconductor pellets mounted on one land of a lead frame and a number of leads extending from the vicinity of the land are connected with bonding wires, but due to the arrangement of the semiconductor bevel/nod and lid, the wires are not connected. There are wires that are too long, wires that are too short, and wires that cross each other, which can easily cause problems such as wires hanging down and shooting into the land, wire breakage, and shorting between wires, which reduces yield. Was.
〔Ｃ〕 １つのランド部上にマウントされた複数種類の
半導体ペレットの厚さは約２００μ−〜５００μｍと相
当広い範囲で、このように半導体ペレットの厚さが大き
く異なると、全てに良好なワイヤボンディングすること
が極めて難しくなり、信頼性に問題があった。[C] The thickness of multiple types of semiconductor pellets mounted on a single land portion ranges from about 200 μm to 500 μm, which is quite a wide range.If the thickness of the semiconductor pellets varies greatly like this, it is difficult to find a good wire for all of the semiconductor pellets. It became extremely difficult to bond, and there were problems with reliability.
ＣＤ）ランド部上に半導体ペレットと共に大容量素子や
大インダクタンス素子、大抵抗素子を組込むことができ
ず、大容量、大インダクタンス、大抵抗のハイブリッド
ＩＣを構成する場合は別品の大容量素子や大インダクタ
ンス素子、大抵抗素子を外付けするしか無く、ハイブリ
ッドＩＣの小形化を難しくしていた。CD) If it is not possible to incorporate a large capacitance element, large inductance element, or large resistance element together with the semiconductor pellet on the land part, and when configuring a hybrid IC with large capacity, large inductance, and large resistance, a separate large capacitance element or The only option was to externally attach large inductance elements and large resistance elements, making it difficult to miniaturize hybrid ICs.
□°の
本発明はリードフレームを使ったハイブリッドＩＣの上
記問題点に鑑みてなされたもので、この問題点を解決す
る本発明の技術的手段はリードフレームの能動素子搭載
部上に配線、受動素子パターンを含む回路素子パターン
を選択的に形成した複数の配線基板を積層して一体化し
た多層配線基板をマウントしたことである。The present invention □° was made in view of the above-mentioned problems of hybrid ICs using lead frames.The technical means of the present invention to solve these problems is to provide wiring and passive wiring on the active element mounting portion of the lead frame. A multilayer wiring board is mounted in which a plurality of wiring boards on which circuit element patterns including element patterns are selectively formed are laminated and integrated.
皿
上記技術的手段においては多層配線基板上やランド部上
にＩＣペレットなどの半導体ペレットが選択的にマウン
トされてワイヤボンディングにて接続される。この多層
配線基板には多数の受動素子、而も大容量、大インダク
タンス、大抵抗の受動素子の組込みが可能で、これによ
りハイブリッドＩＣのより小形化、高密度実装化、多機
能化を可能にする。またリードフレーム使用により一般
のモノリシックＩＣと同じ製造ラインで製造できる。更
にハイブリッドＩＣ回路の変更に多層配線基板を対応さ
せることにより、リードフレームの標準化を可能にする
。In the above-mentioned technical means, semiconductor pellets such as IC pellets are selectively mounted on a multilayer wiring board or land portion and connected by wire bonding. This multilayer wiring board can incorporate a large number of passive elements, including passive elements with large capacitance, large inductance, and large resistance, making it possible to make hybrid ICs smaller, more densely packaged, and more multifunctional. do. Furthermore, by using a lead frame, it can be manufactured on the same production line as general monolithic ICs. Furthermore, by adapting the multilayer wiring board to changes in the hybrid IC circuit, it is possible to standardize the lead frame.
また多層配線基板を介して半導体ペレットとリードを接
続するため、ボンディングワイヤの長さ等を最適値に設
計することが容易になり、ボンディング作業性が改善さ
れる。Furthermore, since the semiconductor pellet and the leads are connected via the multilayer wiring board, it becomes easy to design the length of the bonding wire to an optimum value, and bonding workability is improved.
叉ｌ孤 以下本発明の各実施例を図面を参照して説明する。quarrel Embodiments of the present invention will be described below with reference to the drawings.
第１図乃至第３図の第１実施例において、（１）はリー
ドフレームで、このリードフレーム（１）における（２
）は１つの矩形のランド部、（３）（３）−はランド部
（２）の近傍から延びる多数のリード、（４） （４
）〜は各リード（３）（３）−を連結一体化するクイバ
ーである。（５）はランド部（２）上にマウントされた
多層配線基板、（６）は多層配線基板（５）上にマウン
トされた半導体ベレット、（７）（７）−は半導体ペレ
ット（６）と多層配線基板（５）、リード（３）（３）
−を電気的接続するＡｕ線等のワイヤである。In the first embodiment shown in FIGS. 1 to 3, (1) is a lead frame, and (2) in this lead frame (1)
) is one rectangular land, (3) (3) - is a large number of leads extending from the vicinity of land (2), (4) (4
) ~ is a quiver that connects and integrates each lead (3) (3) -. (5) is a multilayer wiring board mounted on the land portion (2), (6) is a semiconductor pellet mounted on the multilayer wiring board (5), and (7) (7) - is a semiconductor pellet (6). Multilayer wiring board (5), lead (3) (3)
This is a wire such as an Au wire that electrically connects -.
多層配線基板（５）は例えば第３図に示すように３枚の
同一の矩形サイズの配線基板（８）（９） （１０）
を絶縁性ペーストや低融点ガラスなどの絶縁性接着剤（
１）） （１））を介して積層一体化したものである
。３枚の配線基板（８）（９） （１０）はセラミッ
クやポリイミド系樹脂などの同種或いは異質の絶縁基板
（８ａ） （９ａ）（１０ａ ）に配線や受動素子を
含む回路素子パターン（８ｂ） （９ｂ） （１０
ｂ ）を形成した異質機能のものである０例えば最下層
の配線基板（８）の回路素子パターン（８ｂ）は、複数
のインダクタンス素子パターンＬ、 、Ｌ２−を含み、
中間層の配線基板（９）の回路素子パターン（９ｂ）は
、複数のコンデンサ素子パターンＣ，、Ｃ２−を含む。For example, the multilayer wiring board (5) is composed of three wiring boards (8), (9), and (10) of the same rectangular size as shown in FIG.
Insulating paste or insulating adhesive such as low-melting glass (
1)) They are laminated and integrated via (1)). Three wiring boards (8), (9), and (10) are insulating boards (8a), (9a, and 10a) made of the same or different materials such as ceramic or polyimide resin, and circuit element patterns (8b) including wiring and passive elements. (9b) (10
For example, the circuit element pattern (8b) of the lowest layer wiring board (8) includes a plurality of inductance element patterns L, L2-,
The circuit element pattern (9b) of the intermediate layer wiring board (9) includes a plurality of capacitor element patterns C, C2-.
また最上層の配線基板（１０）の回路素子パターン（１
０ｂ ）は中央部に半導体ペレット（６）がマウントさ
れるベレットエリア（１２）と、ベレットエリア（１２
）の近傍に配された多数のポンディングパッド（１３）
（１３）−・−と、絶縁基板（１０ａ ）の周辺部
上に配された多数のポンディングパッド（１４） （
１４）・−と、各ポンディングパッド（１３） （１
３）・・・及び（１４） （１４）−間に選択的に形
成された抵抗素子パターンＲ１、Ｒ２−・−及び配線パ
ターン（１５） （１５）−を含む。各配線基板（８
） （９） （１０）間の電気的接続は例えば図示
しないが、絶縁基板（８ａ）（９ａ） （１０ａ ）
の要所にスルーホール及びこのスルーホール内に導電体
を形成して、三者基板（８） （９） （１０）の
積層時に前記導電体を利用して３つの回路素子パターン
（８ｂ） （９ｂ）（１０ｂ ）を結線することで行
われる。Also, the circuit element pattern (1) of the uppermost layer wiring board (10)
0b) has a pellet area (12) in which a semiconductor pellet (6) is mounted in the center, and a pellet area (12) in which a semiconductor pellet (6) is mounted.
) A large number of pounding pads (13) placed near the
(13) --- and a large number of bonding pads (14) (
14)・- and each pounding pad (13) (1
3)...and (14) (14)-- and wiring patterns (15) (15)-, which are selectively formed between resistor element patterns R1, R2-- and wiring patterns (15) (15)-. Each wiring board (8
) (9) (10) Although electrical connections are not shown, for example, the insulating substrates (8a) (9a) (10a)
Through-holes and conductors are formed in the through-holes at strategic points, and the conductors are used to form three circuit element patterns (8b) ( 9b) (10b).
このハイブリッドＩＣ製造は、リードフレーム（１）の
ランド部（２）への多層配線基板（５）のマウント、多
層配線基板（５）の最上層配Ｉｉ１基ｔＮ （１０）の
ベレー／ トエリア（１２） 上への半導体ペレット（
６）のマウント、マウントされた半導体ペレット（６）
の表面電極と鰻上層配線基板（１０）のボンディングバ
ンド（１３〉（１３） 、及び最上層配線基板（１０
）の周辺部のボンディングバンド（１４） （１４）
−とリード（３）（３）〜の内側先端部へのワイヤ
（７）（７） のボンディング、及び第１図と第２図の
鎖線で示す樹脂モールドパッケージ（１６）のモールド
成形、最後にリードフレーム（１）からタイバー（４）
（４）−を切断除去して個々のハイブリッドＩＣを得る
工程で行われる。このようなハイブリッドＩＣ製造は、
一般のモノリシックＩＣの製造ラインに多層配線基板マ
ウント工程を加えるだけで同じ製造設備、ラインを使っ
て行え、従ってモノリシックＩＣ同様に生産性良く、且
つ高信頼度でもって製造できる。This hybrid IC manufacturing involves mounting the multilayer wiring board (5) on the land portion (2) of the lead frame (1), and mounting the beret/toe area (12) of the top layer Ii1tN (10) of the multilayer wiring board (5). ) onto the semiconductor pellet (
6) Mounting, mounted semiconductor pellet (6)
The bonding band (13) of the surface electrode and the upper layer wiring board (10), and the uppermost layer wiring board (10)
) around the bonding band (14) (14)
- and the wires (7) (7) to the inner tips of the leads (3) (3) ~, and the molding of the resin mold package (16) shown by the chain lines in Figures 1 and 2. Finally, Lead frame (1) to tie bar (4)
(4) - is performed in the step of cutting and removing - to obtain individual hybrid ICs. This kind of hybrid IC manufacturing is
It can be carried out using the same manufacturing equipment and line by simply adding a multilayer wiring board mounting process to a general monolithic IC manufacturing line, and therefore can be manufactured with high productivity and reliability just like monolithic ICs.
上記多層配線基板（５）に多層に形成されたインダクタ
ンス、容量、抵抗の各受動素子は、十分に大インダクタ
ンス、大容量、大抵抗のものが得られ、これにより従来
外付けされていた大インダクタンス、大容量、大抵抗の
受動素子が省略できて、より小形、低コストのハイブリ
ッドＩＣが提供できる。また受動素子の多層配置構造に
より、１つのランド部（２）上でのＩＣ回路のより高密
度配置化が可能で、ハイプリントＩＣの小形化と共によ
り多機能化を図ることが可能となる。更に多層配線基板
（５）上のボンディングバンド（１３） （１３）−
・−１及び（１４）（１４）−ｍ−の位置の選択により
各ワイヤ（７）（７）−−の長さ等が最適に設定されて
、良好なワイヤボンディングが実施される。またハイブ
リッドｒｃの種類に応じ多層配線基板（５）を複数種類
用意することにより、一種類のリードフレーム（１）を
多品種のハイブリッドＩＣ製造に使用することができ、
このリードフレーム（１）の標準化によりリードフレー
ム（１）を安価なプレス抜きで製作することがを利とな
り、結果的にハイブリッドＩＣの低コスト化が可能とな
る。尚、多層配線基板（５）の種類変更は積層する配線
基板（８） （９） （１０）のサイズを標準化し
て、この３枚の内の全て或いは１枚、２枚のみを変更す
ることや、更に別の配線基板を追加して積層することな
どで簡単に実施される。The passive elements of inductance, capacitance, and resistance formed in multiple layers on the multilayer wiring board (5) have sufficiently large inductance, large capacitance, and large resistance. , passive elements with large capacitance and large resistance can be omitted, and a smaller, lower cost hybrid IC can be provided. Furthermore, the multilayer arrangement structure of passive elements allows IC circuits to be arranged at a higher density on one land (2), making it possible to miniaturize the high-print IC and make it more functional. Furthermore, bonding bands (13) (13)- on the multilayer wiring board (5)
- By selecting the positions of -1 and (14) (14) -m-, the lengths, etc. of each wire (7) (7) - are set optimally, and good wire bonding is performed. In addition, by preparing multiple types of multilayer wiring boards (5) depending on the type of hybrid RC, one type of lead frame (1) can be used for manufacturing various types of hybrid ICs.
This standardization of the lead frame (1) makes it advantageous to manufacture the lead frame (1) by inexpensive stamping, and as a result, it becomes possible to reduce the cost of the hybrid IC. In addition, to change the type of multilayer wiring board (5), standardize the size of the wiring boards (8), (9), and (10) to be laminated, and change all or only one or two of these three boards. Or, it can be easily implemented by adding and stacking another wiring board.
この第１実施例は多層配線基板〈５）上に１つの半導体
ペレット（６）をマウントしたもので説明したが、実際
のハイブリッドＩＣには、パワー系やシグナル系の複数
種類の半導体ペレットが使用され、特にパワー系半導体
ペレフトを使用したものにおいては次の各実施例のもの
が好適である。This first embodiment has been described with one semiconductor pellet (6) mounted on a multilayer wiring board (5), but in an actual hybrid IC, multiple types of semiconductor pellets for power system and signal system are used. In particular, the following embodiments are suitable for those using power semiconductor pellets.
第４図及び第５図の第２実施例は、リードフレーム（１
）のランド部（２）上に中央に矩形の貫通穴（１７）を
有する多層配線基板（１８）をマウントし、貫通穴（１
７）から覗くランド部（２）上にパワー系半導体ペレッ
ト（１９）を直接にマウントし、多層配線基板（１８）
上にシグナル系半導体ベレン） （２０） Ｃ２０）
をマウントしたものである。多層配線基板（１８）の構
造は、中央に貫通穴（１７）を形成したこと、最上層配
線基板上に複数の半導体ベレン） （２０） （２０
）をマウントしたこと以外は第１実施例のものと内容的
に同様なので、説明は省略する。The second embodiment shown in FIGS. 4 and 5 has a lead frame (1
) A multilayer wiring board (18) having a rectangular through hole (17) in the center is mounted on the land portion (2) of the through hole (1
A power system semiconductor pellet (19) is directly mounted on the land portion (2) seen from 7), and a multilayer wiring board (18) is mounted.
(20) C20)
is mounted. The structure of the multilayer wiring board (18) is that a through hole (17) is formed in the center, and a plurality of semiconductor beads are formed on the top layer wiring board (20) (20
) is the same as that of the first embodiment except that it is mounted, so a description thereof will be omitted.
この第２実施例のように、パワー系半導体ペレット（１
９）を貫通穴（１７）からランド部（２）上に直接にマ
ウントすることにより、パワー系半導体ペレフｌ−（１
９）の放熱性が十分に確保され、動作的に安定したハイ
ブリッドＩＣが得られる。またパワー系半導体ベレット
（１９）と多層配線基板（１８）の厚さを同程度に設定
することが可能で、このようにするとパワー系半導体ベ
レン） （１９）の表面電極と、多層配線基板（１８）
上のポンディングパッド（２１） （２１） −とが
同程度の高さになる。いわゆるディンプル構造となり、
ワイヤボンディングが良好に行える。As in this second embodiment, power semiconductor pellets (1
9) directly onto the land portion (2) from the through hole (17), the power semiconductor Pellef l-(1
9) Heat dissipation is sufficiently ensured, and an operationally stable hybrid IC can be obtained. Furthermore, it is possible to set the thickness of the power system semiconductor beret (19) and the multilayer wiring board (18) to be approximately the same, and in this way, the surface electrode of the power system semiconductor belet (19) and the multilayer wiring board ( 18)
The upper pounding pads (21) (21) - will be at about the same height. It has a so-called dimple structure,
Wire bonding can be performed well.
第６図の第３実施例はランド部（２）上にマウントされ
る多層配線基板（２２）の−辺中央に上下を貫通する切
欠き（２３）を設け、この切欠き（２３）からランド部
（２）上に大電力消費型半導体ベレット（１９）をマウ
ントし、多層配線基板（２２）上には小信号作動型半導
体ペレット（２０） （２０）をマウントしたもので
、内容的には第２実施例と同様である。In the third embodiment shown in FIG. 6, a notch (23) passing through the top and bottom is provided at the center of the - side of the multilayer wiring board (22) mounted on the land part (2), and the land A large power consuming semiconductor pellet (19) is mounted on the part (2), and small signal activated semiconductor pellets (20) (20) are mounted on the multilayer wiring board (22). This is the same as the second embodiment.
第７図の第４実施例のランド部（２）上にマウントされ
る多層配線基板（２４）は外形サイズが同じで内形サイ
ズが異なる３枚の口字状配線基板（２５＞ （２６）
（２７）を外周を揃えて内形サイズの小さいものか
ら順に積層したもので、中央部に内壁面が階段状になっ
た貫通穴（２８）が形成される。最下層の配線基板（２
５）と中間層の配線基板（２６）の階段状に露出する上
面内周部及び最上層の配線基板（２７）上の適所にボン
ディングバンド（２９） （２９）・−・が形成され
る。The multilayer wiring board (24) mounted on the land portion (2) of the fourth embodiment shown in FIG. 7 is composed of three mouth-shaped wiring boards (25> (26)
(27) are stacked one on top of the other in order from the smallest internal size with the outer peripheries aligned, and a through hole (28) with a stepped inner wall surface is formed in the center. Bottom layer wiring board (2
5), bonding bands (29) (29), etc. are formed at appropriate locations on the inner periphery of the upper surface exposed in a stepped manner of the intermediate layer wiring board (26) and on the uppermost layer wiring board (27).
この多層配線基板（２４）をランド部（２）上にマウン
トした後、貫通穴（２８）からランド部（２）上にパワ
ー系半導体ペレント（１９）がマウントされ、半導体ベ
レット（１９）の表面電極と各配線基板（２５） （
２６） （２７）のポンディングパッド（２９）
（２９）−・・、及び最上層配線基板（２７）の上面外
周部のボンディングバンド（２９’ ）（２９°）−・
・とリード（３）（３）−・・にワイヤ（７）（７）−
・がボンディングされる。After mounting this multilayer wiring board (24) on the land portion (2), a power semiconductor pellet (19) is mounted on the land portion (2) through the through hole (28), and the surface of the semiconductor bullet (19) is mounted. Electrodes and each wiring board (25) (
26) (27) Ponding pad (29)
(29) ---, and the bonding band (29') (29°) on the outer periphery of the top surface of the top layer wiring board (27) ---
- and lead (3) (3) - - wire (7) (7) -
・is bonded.
第８図の第５実施例の多層配線基板（３０）は内形サイ
ズ、外形サイズ共に異なる３、ＩＩｉの口字状配線基板
（３１） （３２） （３３）を内外壁面階段状に
して積層したもので、各配線基板（３１）（３２）
（３３）の露出する上面内外周部に、ポンディングパッ
ド（３４） （３４）・−・が形成される。The multilayer wiring board (30) of the fifth embodiment shown in FIG. 8 is a stack of 3. Each wiring board (31) (32)
Bonding pads (34) (34) are formed on the exposed inner and outer peripheral portions of the upper surface of (33).
この多層配線基板（３０）をランド部（２）上にマウン
トした後、中央の貫通穴（３５）からランド部（２）上
に大電力消費型半導体ベレット（１９）がマウントされ
ワイヤボンディングが行われるやこのワイヤボンディン
グは半導体ペレット（１９）と、各配線基板（３１）
（３２） （３３）の上面内周部上のポンディフグ
パッド（３４）（３４） −とで行われ、リード（３）
（３）・−と各配線基板（３１） （３２）
（３３）の上面外周部上のボンディングバンド（３４°
）（３４”）・・とで行われる。After this multilayer wiring board (30) is mounted on the land portion (2), a high power consuming semiconductor bullet (19) is mounted on the land portion (2) through the central through hole (35) and wire bonding is performed. This wire bonding process involves semiconductor pellets (19) and each wiring board (31).
(32) (33) This is done with the Pondifugu pad (34) (34) - on the inner periphery of the upper surface, and the lead (3)
(3)・- and each wiring board (31) (32)
(33) Bonding band on the outer periphery of the top surface (34°
)(34”)...
尚、多層配線基板は３層構造に限らず、２層、３層以上
にすることも可能である。Note that the multilayer wiring board is not limited to a three-layer structure, but can also have two, three or more layers.
名思及効１
本発明によれば一般のモノリシックＩＣと同じ製造ライ
ンを使っても製造が可能で、生産性、信頼性の良いハイ
ブリッドＩＣが提供できる。また多層配線基板使用によ
りリードフレームの標準化が容易、受動素子の外付は部
品の省略が可能でより小形化、低コスト化が図れ、また
ボンディングワイヤを最適な長さに設計することが可能
で、ワイヤボンディング性の良好なものが提供できる。DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, a hybrid IC can be manufactured using the same manufacturing line as a general monolithic IC, and has good productivity and reliability. In addition, the use of a multilayer wiring board makes it easy to standardize the lead frame, and it is possible to omit external parts for passive elements, resulting in smaller size and lower costs, and it is also possible to design the bonding wire to the optimal length. , it is possible to provide a product with good wire bonding properties.
第１図は本発明の第１実施例を示す平面図、第２図は第
１図のＡ−Ａ線に沿う断面図、第３図は第１図のハイブ
リッドＩＣにおける多層配線基板の分解斜視図、第４図
は本発明の第２実施例を示す部分斜視図、第５図は第４
図のＢ−Ｂ線に沿う断面図、第６図、第７図、第８図は
本発明の他の各実施例を示す各部分斜視図である。
（１）−リードフレーム、 （２）−ランド部、（５）
−多層配線基板、（８） （９） （１０）−配線
基板、＜８ｂ） （９ｂ） （１０ｂ ） −回路
素子パターン、（１８）−多層配線基板、（２２） −
多層配線基板、（２４）・−多層配線基板、（２５）（
２６） （２７）・−配線基板、（３０）−多層配線
基板、（３１） （３２） （３３） −・配線
基板。
特 許 出 願 人 関西日本電気株式会社代
理 人 江 原 省 合理
原 秀
１）１図
第２図
８５図
ＩＦＩａ図
簾７ｖ！ＪFIG. 1 is a plan view showing a first embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A in FIG. 1, and FIG. 3 is an exploded perspective view of the multilayer wiring board in the hybrid IC shown in FIG. 4 is a partial perspective view showing the second embodiment of the present invention, and FIG. 5 is a partial perspective view showing the second embodiment of the present invention.
A sectional view taken along line B-B in the figure, and FIGS. 6, 7, and 8 are partial perspective views showing other embodiments of the present invention. (1) - Lead frame, (2) - Land part, (5)
-Multilayer wiring board, (8) (9) (10) -Wiring board, <8b) (9b) (10b) -Circuit element pattern, (18) -Multilayer wiring board, (22) -
Multilayer wiring board, (24)・-Multilayer wiring board, (25)(
26) (27) - Wiring board, (30) - Multilayer wiring board, (31) (32) (33) - Wiring board. Patent applicant: Kansai NEC Co., Ltd.
Rational People Gangwon Province Rational
Hide Hara 1) Figure 1 Figure 2 Figure 85 IFIa Zuren 7v! J
Claims (1)
動素子パターンを含む回路素子パターンを選択的に形成
した複数の配線基板を積層して一体化した多層配線基板
をマウントしたことを特徴とするハイブリッドＩＣ。(1) A multilayer wiring board is mounted in which a plurality of wiring boards on which circuit element patterns including wiring and passive element patterns are selectively formed on the active element mounting portion of the lead frame are laminated and integrated. Hybrid IC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59132465A JPS6110263A (en) | 1984-06-26 | 1984-06-26 | Hybrid ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59132465A JPS6110263A (en) | 1984-06-26 | 1984-06-26 | Hybrid ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6110263A true JPS6110263A (en) | 1986-01-17 |
Family
ID=15082004
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59132465A Pending JPS6110263A (en) | 1984-06-26 | 1984-06-26 | Hybrid ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6110263A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6352956A (en) * | 1986-08-20 | 1988-03-07 | Toyoda Mach Works Ltd | Dimension measuring device using contact probe |
| US4754317A (en) * | 1986-04-28 | 1988-06-28 | Monolithic Memories, Inc. | Integrated circuit die-to-lead frame interconnection assembly and method |
| JPH02109659A (en) * | 1988-10-20 | 1990-04-23 | Niigata Eng Co Ltd | Detecting device for contact |
| JPH02126696A (en) * | 1988-11-07 | 1990-05-15 | Fujikura Ltd | Enameled wiring board and manufacture thereof |
| JPH0338867A (en) * | 1989-07-05 | 1991-02-19 | Nec Corp | Hybrid integrated circuit device |
| JPH04193460A (en) * | 1990-11-26 | 1992-07-13 | Yasuda Kogyo Kk | Measuring method for shape or profile irregularity and device used therefor |
| US5313366A (en) * | 1992-08-12 | 1994-05-17 | International Business Machines Corporation | Direct chip attach module (DCAM) |
| US5332864A (en) * | 1991-12-27 | 1994-07-26 | Vlsi Technology, Inc. | Integrated circuit package having an interposer |
| US5420758A (en) * | 1992-09-10 | 1995-05-30 | Vlsi Technology, Inc. | Integrated circuit package using a multi-layer PCB in a plastic package |
| US5548486A (en) * | 1994-01-21 | 1996-08-20 | International Business Machines Corporation | Pinned module |
| US5878483A (en) * | 1995-06-01 | 1999-03-09 | International Business Machines Corporation | Hammer for forming bulges in an array of compliant pin blanks |
| JP2002110892A (en) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | Multi-chip semiconductor device |
| EP1505645A2 (en) | 2003-08-08 | 2005-02-09 | Hitachi, Ltd. | Resin moulded electronic module |
-
1984
- 1984-06-26 JP JP59132465A patent/JPS6110263A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4754317A (en) * | 1986-04-28 | 1988-06-28 | Monolithic Memories, Inc. | Integrated circuit die-to-lead frame interconnection assembly and method |
| JPS6352956A (en) * | 1986-08-20 | 1988-03-07 | Toyoda Mach Works Ltd | Dimension measuring device using contact probe |
| JPH02109659A (en) * | 1988-10-20 | 1990-04-23 | Niigata Eng Co Ltd | Detecting device for contact |
| JPH02126696A (en) * | 1988-11-07 | 1990-05-15 | Fujikura Ltd | Enameled wiring board and manufacture thereof |
| JPH0338867A (en) * | 1989-07-05 | 1991-02-19 | Nec Corp | Hybrid integrated circuit device |
| JPH04193460A (en) * | 1990-11-26 | 1992-07-13 | Yasuda Kogyo Kk | Measuring method for shape or profile irregularity and device used therefor |
| US5332864A (en) * | 1991-12-27 | 1994-07-26 | Vlsi Technology, Inc. | Integrated circuit package having an interposer |
| US5313366A (en) * | 1992-08-12 | 1994-05-17 | International Business Machines Corporation | Direct chip attach module (DCAM) |
| US5420758A (en) * | 1992-09-10 | 1995-05-30 | Vlsi Technology, Inc. | Integrated circuit package using a multi-layer PCB in a plastic package |
| US5548486A (en) * | 1994-01-21 | 1996-08-20 | International Business Machines Corporation | Pinned module |
| US5715595A (en) * | 1994-01-21 | 1998-02-10 | International Business Machines Corporation | Method of forming a pinned module |
| US5878483A (en) * | 1995-06-01 | 1999-03-09 | International Business Machines Corporation | Hammer for forming bulges in an array of compliant pin blanks |
| JP2002110892A (en) * | 2000-09-27 | 2002-04-12 | Rohm Co Ltd | Multi-chip semiconductor device |
| EP1505645A2 (en) | 2003-08-08 | 2005-02-09 | Hitachi, Ltd. | Resin moulded electronic module |
| EP1505645A3 (en) * | 2003-08-08 | 2009-01-14 | Hitachi, Ltd. | Resin moulded electronic module |
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