JPS6110235A - Formation of electrode in semiconductor - Google Patents
Formation of electrode in semiconductorInfo
- Publication number
- JPS6110235A JPS6110235A JP59131515A JP13151584A JPS6110235A JP S6110235 A JPS6110235 A JP S6110235A JP 59131515 A JP59131515 A JP 59131515A JP 13151584 A JP13151584 A JP 13151584A JP S6110235 A JPS6110235 A JP S6110235A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- layer
- type layer
- alloy
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01052—Tellurium [Te]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
技術分野
本発明ｉｊ：Ｉ−Ｖ族化合物半導体のＮ形層にワイヤボ
ンデング性の良好な、ｌ又ＶｉＡ１合金オーミック電極
を形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a method for forming a l or ViA1 alloy ohmic electrode with good wire bondability on an N-type layer of an IV group compound semiconductor.
従来技術
ＡＪ又はｋ１合金（以下単にＡＩという）オーミック電
極’６、ｗ−ｖ族化合物半導体に取付ける場合、取付け
る半導体がＰ形であれば、ｚｎ１Ｂθ等を表面近傍に高
濃度に拡散させて合金化し、これとＡｅとをオーミック
接触づせて形成することが知られている。しかし、Ｎ形
に対しては、通常表面にＡｕ合金層およびＴ１、ＴｉＮ
等のバリヤ金属層を順次設け、さらにＡＪＩを設ける三
層構造が用いられている。これはバリヤ金属Ｒ’ｃ介在
させないと脆くなるためである。Conventional technology AJ or k1 alloy (hereinafter simply referred to as AI) ohmic electrode '6, when attached to a w-v group compound semiconductor, if the semiconductor to be attached is P type, zn1Bθ etc. are diffused in high concentration near the surface to form an alloy. , it is known to form this and Ae in ohmic contact. However, for N type, there is usually an Au alloy layer on the surface and T1, TiN
A three-layer structure is used in which barrier metal layers such as AJI are sequentially provided, and AJI is further provided. This is because the barrier metal R'c becomes brittle without intervening.
従来技術の問題点
ところで、上記Ｎ形層にＡＪオーミック電極を設ける上
記方法は、三層構造となるため、工程が複雑となり、量
産性が悪く、またバリヤ金属が劣化した場合信頼性に欠
け、寿命が短かくなる欠点があった。Problems with the Prior Art By the way, the above method of providing an AJ ohmic electrode on the N-type layer has a three-layer structure, which complicates the process, makes it difficult to mass-produce, and lacks reliability when the barrier metal deteriorates. The drawback was that the lifespan was shortened.
本発明の構成および目的
本発明は上記の事情に鑑み、Ｎ形層に容易にＡ／又は７
１合金のオーミック電極をとりつけることが出来、長寿
命でかつ費用のかからない、Ａｅ［極の形成方法を提供
することを目的とするもので、その要旨は、半導体のＮ
層表面に、蒸着等の手段によりＳｌ、ＧｏＳＳｎ、５ｅ
ＳＴｏのうち込ずれかの薄膜を形成し、この表面ＫＣＶ
Ｄ又は酸化等の手段により保護膜を形成し、これ全熱処
理して上記Ｎ層と薄膜物質境界に合金層を形成し、上記
保護膜および薄膜物質をエツチング和よって除去して表
面洗浄し、Ａｇ又けＡｅ合金を蒸着した後さらに熱処理
することを特徴とする半導体への電極形成方法にある。Structure and Object of the Present Invention In view of the above circumstances, the present invention provides an easy method for forming an N-type layer with A/ or 7
The purpose of this project is to provide a method for forming an Ae[pole] that can be attached to an ohmic electrode made of a single alloy, has a long life, and is inexpensive.
Sl, GoSSn, 5e are deposited on the surface of the layer by means such as vapor deposition.
A thin film is formed on either side of the STo, and this surface KCV
A protective film is formed by means such as D or oxidation, this is subjected to a total heat treatment to form an alloy layer at the boundary between the N layer and the thin film material, the protective film and the thin film material are removed by etching, the surface is cleaned, and Ag The present invention provides a method for forming electrodes on a semiconductor, which comprises further heat treatment after vapor-depositing the Ae alloy.
本発明の詳細な説明 本発明に用いられる璽族物質は、Ｇ ［Ｌ、Ｉ ｎ。Detailed description of the invention The A-group substances used in the present invention are G[L, In.
ＡＪｔ、Ｖ族物質はＡ８、ｐ、ｓｂ薄膜形成物質は、Ｇ
ｅ％Ｓｉ、Ｓｎ、Ｓｓ、’ｌ’ｅのうちいずれかである
。AJt, V group material is A8, p, sb thin film forming material is G
e% is any one of Si, Sn, Ss, and 'l'e.
上記璽族、Ｖ族化合物半導体のＮ形層表面に、蒸着或い
はスパッタリングにより、１０００〜２０００Ａの厚さ
Ｓｌ、Ｇｏ、Ｓｎ、Ｓｅ、Ｔｅ等の薄膜を形成する。次
いで、この薄膜の表面に８１０１等を含有する気体の化
学反応（ＣＶＤ）或いはスピンコードなど九よって保護
膜形成させ、上記薄膜物質或いＶｉＮ形層形成成分の蒸
発を防止し、Ｎ１、Ａｒ等の不活性雰囲気内で７００〜
９００℃の温度で１０〜！１０分間熱処理する。この熱
処理によって、上記薄膜とＮ形層の境界近傍に社、薄膜
物質が拡散し、合金層が形成される。次いで、上記保護
膜および薄膜物質を沸酸系あるいは硫酸系エッチャント
でエツチングして除去した後、エッチャントを洗浄し、
乾燥する。次いで、上記乾燥した面にＡＪを１〜３μ蒸
着させた後、Ｎｔ、Ａｒ等の不活性ガス雰囲気内で４０
０〜５００°Ｃの温度下、１０〜２０分熱処理する。こ
の熱処理により、ＡＪはＮ形層面に密着、固定され、良
好なＭオーミック電極が形成これる。A thin film of Sl, Go, Sn, Se, Te, etc. with a thickness of 1000 to 2000 Å is formed on the surface of the N-type layer of the above-mentioned A-group and V-group compound semiconductors by vapor deposition or sputtering. Next, a protective film is formed on the surface of this thin film by a chemical reaction (CVD) of a gas containing 8101, etc., or by a spin code, etc., to prevent the evaporation of the thin film material or the components forming the ViN type layer, and 700 ~ in an inert atmosphere of
10~ at a temperature of 900℃! Heat treat for 10 minutes. This heat treatment causes the thin film material to diffuse near the boundary between the thin film and the N-type layer, forming an alloy layer. Next, the above-mentioned protective film and thin film material are removed by etching with a hydrofluoric acid-based or sulfuric acid-based etchant, and then the etchant is washed away.
dry. Next, after evaporating 1 to 3μ of AJ on the dried surface, 40μ of AJ was deposited in an inert gas atmosphere such as Nt or Ar.
Heat treatment is performed at a temperature of 0 to 500°C for 10 to 20 minutes. By this heat treatment, AJ is closely attached and fixed to the N-type layer surface, and a good M ohmic electrode is formed.
上記ＡＪ電極には、フォトレジストを塗布し、フォトマ
スクを透して紫外線を照射し、現象液によってフォトレ
ジストを７オトマスクのパターに除去した後、エツチン
グする通常のフォトリソグラフィによって所定のパター
ンが形成され、しかる後ダイシングされ、ダイオード素
子に分割ばれる。A predetermined pattern is formed on the AJ electrode by normal photolithography, which involves applying a photoresist, irradiating it with ultraviolet light through a photomask, removing the photoresist to a pattern of 7 otomasks using a phenomenon liquid, and then etching it. It is then diced and divided into diode elements.
実施例 次に実施例を示して本発明を具体的に説明する。Example Next, the present invention will be specifically explained with reference to Examples.
第１図（ａ）は、Ｇ＋！Ｌ１Ａ１１のエピタキシャルウ
ェハー１でＮ形層２、Ｐ形層３よ一すなっている。この
Ｎ形層２の表面に、第１図（ｂ）に示すように、蒸着に
よりＧｅの厚さ１５００Ａの薄膜４を形成する。FIG. 1(a) shows G+! The epitaxial wafer 1 of L1A11 has an N type layer 2 and a P type layer 3. On the surface of this N-type layer 2, as shown in FIG. 1(b), a thin film 4 of Ge having a thickness of 1500 Å is formed by vapor deposition.
このＧｅ薄膜４の表面に、第１図（０）に示すようにス
パッタリングによって厚さ２０００ＡのＳ１０゜保護膜
５を形成し、これ’ｔＡｒの不活性雰囲気で・８００°
Ｃｌ２Ｏ分熱処理を施した。この熱処理によって第１図
（ａ） Ｋ示すようにＮ形層２０表面近傍にはＧｅが拡
散し、合金１６が形成される。次いでＰ形ＪＪ ３の表
面をラッピングおよびエツチングして、第１図（θ）に
示すように蒸着によりＡ ｕ、Ｂ ｅ電極７を形成した
。このＡｕ、Ｂθ電極７けワイヤボンデングしない電極
である。次いで、上記Ｓ１０．保護膜５、Ｇｅ薄膜４を
フッ酸によってエツチング除去し、第１図（ｒ） Ｋ示
すように合金６面を露出させるとともに、表面を洗浄、
乾燥する。４次いでｆＲ１図（ｇ）に示すように２μの
厚さにＡｌｆ層８を蒸着し、これ１！ｒＡｒ不活性雰囲
気中で４５０℃、１５分熱処理し、１１層８を密着させ
λｅオーミック電極Ｉｆを形成する。このＡＪオーミッ
ク電極８′は、フォトリソグラフィーによって、第１図
（ｈ）に示すようにパターン化されたＡｇ電極８′ と
され、次いでダイシングにより、第１ 因（１）に示す
ようなダイオードチップ９・・・に分割される。分割後
、第１図（ｊ）に示すごとくＮ層の表面拡散層６をエツ
チングにより除去する。On the surface of this Ge thin film 4, as shown in FIG.
Heat treatment was performed for Cl2O. As a result of this heat treatment, Ge diffuses near the surface of the N-type layer 20, forming an alloy 16, as shown in FIG. 1(a). Next, the surface of the P-type JJ 3 was lapped and etched, and the A u, B e electrodes 7 were formed by vapor deposition as shown in FIG. 1 (θ). This Au, Bθ electrode is an electrode that does not require wire bonding. Next, the above S10. The protective film 5 and the Ge thin film 4 are removed by etching with hydrofluoric acid to expose the alloy 6 surface as shown in FIG. 1(r)K, and the surface is cleaned.
dry. 4 Next, as shown in the fR1 diagram (g), an Alf layer 8 was deposited to a thickness of 2μ, and this 1! A heat treatment is performed at 450° C. for 15 minutes in an rAr inert atmosphere to bring the 11 layers 8 into close contact to form a λe ohmic electrode If. This AJ ohmic electrode 8' is formed into a patterned Ag electrode 8' by photolithography as shown in FIG. It is divided into... After the division, the N-layer surface diffusion layer 6 is removed by etching as shown in FIG. 1(j).
上記Ａｇオーミック電極８′は、ダイオード素子９のＮ
形層に直接強固に固定されており、ワイヤボンディング
性に優れ、経時的な劣化は全くない。The Ag ohmic electrode 8' is connected to the N of the diode element 9.
It is firmly fixed directly to the shape layer, has excellent wire bonding properties, and shows no deterioration over time.
本発明の効果
以上述べたように本発明和係るＡｅ電極形成方法は、従
来法に比して構造が簡易で量産性がよく、バリヤ金属の
不良による劣化の発生がなく、信頼性が高く、安価なダ
イオードチップｔｎ造することが出来る。Effects of the Present Invention As described above, the Ae electrode forming method according to the present invention has a simpler structure and better mass productivity than conventional methods, is free from deterioration due to defective barrier metals, and is highly reliable. It is possible to manufacture inexpensive diode chips.
第１図（、）〜θ）は本発明の方法による／ｉｔ電極の
形成方法の一実施例を用いたダイオードチップの製法を
順に示した図である。
１・・・・・・ウェハー、２・・・・・・Ｎ形層、３・
・・・・・Ｐ形層、４・・・・・・Ｇｏ薄膜、５・・・
・・・ＳＩＱ、保護膜、６・・・・・・合金層（拡散層
）、７・・・・・・Ｊｕ、Ｂｅ極、８・・・・・・ＡＪ
層、８′・・・・・・ＡＪ電極、８−・・・・・パター
ン化されたＡＪ電極、９・・・・・・ダイオードチップ
。
第１図FIGS. 1(, ) to θ) are diagrams sequentially showing a method for manufacturing a diode chip using an embodiment of the method for forming an /it electrode according to the method of the present invention. 1...Wafer, 2...N-type layer, 3.
... P type layer, 4 ... Go thin film, 5 ...
... SIQ, protective film, 6 ... alloy layer (diffusion layer), 7 ... Ju, Be electrode, 8 ... AJ
layer, 8'... AJ electrode, 8-... patterned AJ electrode, 9... diode chip. Figure 1
Claims (1)
ｎ、Ｓｅ、Ｔｅのうちいずれかの薄膜を形成し、この表
面に保護膜を形成し、これを熱処理して上記Ｎ層と薄膜
物質境界に合金層を形成し、上記保護膜および薄膜物質
をエッチングによつて除去して表面洗浄し、Ａｌ又はＡ
ｌ合金を蒸着した後さらに熱処理することを特徴とする
半導体への電極形成方法。Si, Ge, S
A thin film of any one of n, Se, and Te is formed, a protective film is formed on the surface of the thin film, an alloy layer is formed at the boundary between the N layer and the thin film material by heat treatment, and the protective film and the thin film material are removed. Remove by etching and surface cleaning, Al or A
1. A method for forming electrodes on a semiconductor, which comprises further heat treatment after vapor depositing the l-alloy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59131515A JPS6110235A (en) | 1984-06-26 | 1984-06-26 | Formation of electrode in semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59131515A JPS6110235A (en) | 1984-06-26 | 1984-06-26 | Formation of electrode in semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6110235A true JPS6110235A (en) | 1986-01-17 |
Family
ID=15059843
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59131515A Pending JPS6110235A (en) | 1984-06-26 | 1984-06-26 | Formation of electrode in semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6110235A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7074350B2 (en) | 2001-03-23 | 2006-07-11 | Citizen Watch Co., Ltd. | Brazing filler metal |
-
1984
- 1984-06-26 JP JP59131515A patent/JPS6110235A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7074350B2 (en) | 2001-03-23 | 2006-07-11 | Citizen Watch Co., Ltd. | Brazing filler metal |
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