JPS61102050A - Semiconductor memory storage - Google Patents

Semiconductor memory storage

Info

Publication number
JPS61102050A
JPS61102050A JP59224816A JP22481684A JPS61102050A JP S61102050 A JPS61102050 A JP S61102050A JP 59224816 A JP59224816 A JP 59224816A JP 22481684 A JP22481684 A JP 22481684A JP S61102050 A JPS61102050 A JP S61102050A
Authority
JP
Japan
Prior art keywords
layer
wiring layer
diffusion layer
semiconductor memory
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59224816A
Other languages
Japanese (ja)
Inventor
Hiroshi Shimizu
博史 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59224816A priority Critical patent/JPS61102050A/en
Publication of JPS61102050A publication Critical patent/JPS61102050A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To estimate an acceptable protective film or a defective one previously by forming another wiring layer onto the protective film and measuring characteristics between two of a wiring layer and another wiring layer when a diffusion layer is formed to the surface layer section of a semiconductor substrate, the whole surface containing the diffusion layer is coated with an oxide film, an opening is bored, the wiring layer being in contact with the diffusion layer is applied, the wiring layer is coated with the protective film and a memory storage is shaped. CONSTITUTION:A diffusion layer 2 is formed to the surface layer section of a semiconductor substrate 1, an oxide film 3 is applied onto the whole surface containing the layer 2, an opening is bored made to correspond to the diffusion layer 2, and an Al wiring layer 4 is shaped onto the whole surface while being brought into contact with the diffusion layer 2. The whole surface is coated with a passivation film 5, an opening is bored to a bonding pad section B, a bonding wire is connected to the wiring layer 4 and a memory storage is shaped, but another Al wiring 7 is formed previously only onto a memory section C at that time. According to such constitution, an acceptable passivation film 5 or a defective one and the deterioration of the film 5, which will be shaped afterwards, can also be decided when electrical characteristics are measured by using the wirings 7 and 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体メモリ装置に関し、特にプラスチック
パッケージによる半導体メモリ装置におけるメモリ部の
耐湿性改善に係るものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to improving the moisture resistance of a memory portion of a semiconductor memory device using a plastic package.

〔従来の技術〕[Conventional technology]

従来例によるこの種の半導体メモリ装置の概要構成を第
3図に示す、すなわち、この第3図において、符号Aは
半導体メモリチップを示し、lは同チップAのシリコン
半導体基板、2はこの半導体基板lの表面部に形成され
た拡散層、3は同半導体基板lの表面に形成されて絶縁
膜となる酸化膜、4は前記拡散M2に接続されたアルミ
ニウム配線層、5はこれらの表面を被覆するパシベーシ
ョン膜、6は前記配&1層4に接続されたポンディング
線であって1通常、そのボンディング部日については前
記パシベーシ、ンll!i5の被覆を欠いた構造となっ
ている。
A schematic configuration of this type of semiconductor memory device according to a conventional example is shown in FIG. 3. In other words, in FIG. A diffusion layer formed on the surface of the substrate l; 3 an oxide film formed on the surface of the semiconductor substrate l to serve as an insulating film; 4 an aluminum wiring layer connected to the diffusion M2; 5 these surfaces. The passivation film 6 is a bonding wire connected to the layer 4, and the bonding portion is normally connected to the passivation layer 4. It has a structure lacking the i5 coating.

こ−で一般的に、半導体集積回路においては、電子機器
の小型化、軽琶化、低価格化などの要望に応するための
開発が進められており、そして装置パッケージとしても
、*品開発、量産の初期には、チップサイズの制限も比
較的に緩くて、信頼性確保の容易なセラミックパッケー
ジが採用されていたが、製品価格の低下にあわせて、次
第により低価格のプラスチックパッケージに移行してき
ている。
Therefore, in general, development of semiconductor integrated circuits is progressing to meet the demands of electronic devices becoming smaller, lighter in weight, and lower in price. In the early stages of mass production, ceramic packages were used, as they had relatively loose restrictions on chip size and were easy to ensure reliability, but as product prices fell, they gradually shifted to lower-priced plastic packages. I've been doing it.

第4図には前記半導体メモリ装置に対するプラスチック
パッケージの構成を示しである。すなわち、この第4図
において、符号8は前記半導体メモリチップAを搭載す
るメタルフレーム、9は外部接続のためのリードビンで
あって、前記ポンディング線6を接続してあり、これら
はリードピン3の取り出し脚部を除いて、プラスチック
ioにより封止パッケージされている。
FIG. 4 shows the structure of a plastic package for the semiconductor memory device. That is, in FIG. 4, reference numeral 8 is a metal frame on which the semiconductor memory chip A is mounted, and 9 is a lead bin for external connection, to which the bonding wire 6 is connected. Except for the take-out legs, it is sealed and packaged with plastic IO.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来例でのプラスチックパッケージによる半導体メモリ
装置はこのように構成されており、こ−でのプラスチッ
クパッケージ化に伴なう最大の問題点は、プラスチック
パッケージの非気密性を理由とする耐湿性である。
Conventional semiconductor memory devices using plastic packages are configured as described above, and the biggest problem with plastic packaging is moisture resistance due to the non-airtightness of plastic packages. .

すなわち、前記半導体メモリチップAにおいては、信頼
性の確保をチップ面上のパシベーション膜5による被覆
に依存しているが、このパシベーションl]i5にクラ
ック(ひ−割れ)とかピンホールなどの障害部分11が
あると、プラスチック10の封止部分からの、矢印12
に示す外部雰囲気中の水分の侵入により、この障害部分
11を通しチップ内のアルミニウム配線層4が腐食して
接続不良を生ずることがある。
That is, in the semiconductor memory chip A, ensuring reliability depends on the passivation film 5 covering the chip surface. 11, the arrow 12 from the sealing part of the plastic 10
Intrusion of moisture from the external atmosphere as shown in FIG. 1 may corrode the aluminum wiring layer 4 within the chip through this faulty portion 11, resulting in connection failure.

そしてこのアルミニウム配線N4に腐食を生じている半
導体メモリチップAを動作させても、この配線層4が完
全に断線するまでは不良にはならず、例えばCl40S
デバイスなどのようにリーク電流の少ないものは、この
リーク電流の増加という前兆があるが、リーク電流増加
が即、腐食とはならないもので、通常のデバイスではそ
の兆候すら見出し難く、結局、この腐食はパッケージを
開いてみつけるしかない、また外観的にも、電気的特性
にも異常のないときですら、その腐食は徐々に進行する
ために、あるとき突然に装置が誤動作するといった可能
性があり、このように半導体メモリチップでは、#湿性
の低下、アルミニウム配線層の腐食は製品自体の信頼性
上から好ましくなく、また製造時点において、パシベー
ション膜に欠陥などがあっても、初期のテスト段階では
良品としか判定できず、これが将来、アルミニウム腐食
を生じて装置の誤動作を招くなどの問題点を有するもの
であった。
Even if the semiconductor memory chip A whose aluminum wiring layer N4 is corroded is operated, it will not become defective until the wiring layer 4 is completely disconnected.
For devices with low leakage current, there are signs of an increase in leakage current, but an increase in leakage current does not immediately lead to corrosion, and it is difficult to detect even the signs of corrosion in normal devices. The only way to find out is by opening the package, and even when there are no abnormalities in appearance or electrical characteristics, corrosion progresses gradually, so there is a possibility that the equipment may suddenly malfunction. As described above, in semiconductor memory chips, #decreased humidity and corrosion of the aluminum wiring layer are undesirable from the viewpoint of reliability of the product itself, and even if there are defects in the passivation film at the time of manufacture, it will not be possible at the initial testing stage. It could only be judged as a non-defective product, which would cause future problems such as corrosion of aluminum and malfunction of the equipment.

この発明は従来のこのような問題点を解決するためにな
されたものであって、初期のテスト段階でアルミニウム
配線層の腐食につながる製品を見出すことのできる半導
体メモリ装置を得ることを目的とするものである。
This invention has been made to solve these conventional problems, and aims to provide a semiconductor memory device that can detect products that cause corrosion of aluminum wiring layers at an early testing stage. It is something.

〔問題点を解決するための手段〕[Means for solving problems]

前記目的を達成するため、この発明は、バシベーシ璽ン
膜下のアルミニウム配線層に加えて、このハシヘーシ、
ン膜上に対しても、アルミニウム配線被覆層を形成し、
これらの2層からなる両配線居間で電気的特性を計測し
得るようにしたものである。
In order to achieve the above-mentioned object, the present invention provides an aluminum wiring layer under the aluminum wiring layer, as well as the aluminum wiring layer under the aluminum wiring layer.
An aluminum wiring coating layer is also formed on the aluminum film.
The electrical characteristics can be measured in both wiring rooms made up of these two layers.

〔作   用〕[For production]

従ってこの発明に係る半導体メモリ*aにおいては、装
置製造時に2N!からなる両配線歴間での電気的特性テ
ストをなすことにより、この両配線層間に介在されるパ
シベーション膜の良否、欠陥の有無などを判定し得るの
である。
Therefore, in the semiconductor memory *a according to the present invention, 2N! By performing an electrical characteristic test between the two wiring layers, it is possible to determine whether the passivation film interposed between the two wiring layers is good or not, and whether there are any defects.

〔実 施 例〕〔Example〕

以下この発明に係る半導体メモリ装置の一実施例につき
、第1図および第2図を参照して詳細に説明する。
Hereinafter, one embodiment of a semiconductor memory device according to the present invention will be described in detail with reference to FIGS. 1 and 2.

第1図はこの実施例装置を前記第3図従来例装置に対応
させて示す装置要部の断面図であり、また第2図は同上
装置の全体構成を示す平面説明図である。
FIG. 1 is a sectional view of the main parts of this embodiment of the apparatus in correspondence with the conventional apparatus shown in FIG. 3, and FIG. 2 is an explanatory plan view showing the overall structure of the same apparatus.

そしてこれらの第1図および第2図実施例において、前
記第3図従来例と同一符号は同一または相当部分を示し
ており、この各実施例では、前記パシベーション膜5上
に対し、アルミニウム配線被wI層7を被覆させたもの
であり、このアルミニウム配線被覆57は1例えば従来
から公知の2層配線手段によって容易に形成できる。
In the embodiments shown in FIGS. 1 and 2, the same reference numerals as in the conventional example shown in FIG. This aluminum wiring coating 57 can be easily formed by, for example, a conventionally known two-layer wiring method.

こ−で前記アルミニウム配線被覆層7の被覆範囲につい
ては、第3図に示すように、メモリ部Cの望城全体であ
って良く、こ−ではメモリ部C上に形成されるパシベー
シ、ン膜5の異常、もしくは欠陥検出に有効であり、葭
大範囲としては、必要に応じてポンディングパッド部を
除く全領域を被撰させても何等差し支えはない。
In this case, the coverage range of the aluminum wiring coating layer 7 may be the entire area of the memory section C, as shown in FIG. It is effective for detecting abnormalities or defects in the area, and there is no problem in covering the entire area except for the bonding pad portion as necessary.

従って、この実施例構成の場合には、パシベーション1
15!5にクラックとかピンホールなどの障害部分11
などが発生していると、前記酸化H3上に選択的に形成
されるアルミニウム配線層4と、同配線層4上にパシベ
ーション膜5を介して全面被覆形成されるアルミニウム
配線被覆層7との間が短絡された形となり、その結果と
して、これらの両氏線膜4.7間における装置製造後の
初期の電気的特性テストにより製品の不良を判定できる
ものであり、このために長時間に亘るバーンインとか高
温高湿試験、およびプレッシャクンカー試験などの耐湿
性評価試験の以前にあって、この不良品を排除し得るの
である。
Therefore, in the case of this embodiment configuration, the passivation 1
Obstacles such as cracks and pinholes on 15!5 11
etc., between the aluminum wiring layer 4 selectively formed on the oxidized H3 and the aluminum wiring covering layer 7 formed entirely on the same wiring layer 4 with a passivation film 5 interposed therebetween. As a result, it is possible to determine whether the product is defective by testing the electrical characteristics between these two membranes 4.7 at an early stage after manufacturing the device. This makes it possible to eliminate defective products before conducting moisture resistance evaluation tests such as high-temperature, high-humidity tests, and pressure-kunker tests.

〔発明の効果〕〔Effect of the invention〕

以上詳述したようにこの発明によれば、半導体メモリ装
置の構成において、パシベーション膜下のアルミニウム
配線層と共に、その後、このパシベーション膜上に対し
ても、アルミニウム配線被覆層を被覆形成して、これら
の2層からなる両氏線層間で、装置構成の電気的特性を
計測し得るようにしたから、パシベーション膜に不良、
欠陥などのあるメモリチップ、換言すると将来に亘つて
アルミニウム配線層に腐食を生ずる可能性のあるメモリ
チップを初期テストで排除することができるほか、併せ
てパシベーシ77M上でのアルミニウム配線波′m層の
形成は、一方で装置の耐湿性を向上させ、他方ではその
全面被覆形成土から生ずるバッファ効果により、プラス
チック封止の際の耐圧、防護性を充分に高め得られ、し
かも構成的にも簡単で容易に実施できるなどの特長を有
するものである。
As described in detail above, according to the present invention, in the configuration of a semiconductor memory device, an aluminum wiring covering layer is formed not only on the aluminum wiring layer under the passivation film but also on the passivation film. Since it is possible to measure the electrical characteristics of the device configuration between the two layers, it is possible to detect defects in the passivation film.
Memory chips with defects, in other words memory chips that may cause corrosion of the aluminum wiring layer in the future, can be eliminated in the initial test. On the one hand, the formation of this material improves the moisture resistance of the device, and on the other hand, due to the buffer effect generated from the soil that covers the entire surface, it is possible to sufficiently increase the pressure resistance and protection properties during plastic sealing, and it is also simple in construction. It has the advantage of being easy to implement.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明に係る半導体メモリ装置の一実施例に
よる装置要部の断面図、第2図は同上装置の全体構成を
示す平面説明図であり、また第3す横断面図である。 A・・・・半導体メモリチップ、B・・・・ポンディン
グバット部、C・・・・メモリ部、1・・・・シリコン
半導体基板、2・・・・拡散層、3・・・・酸化膜、4
・・・・アルミニウム配線層、5・・・・パシベーショ
ン膜、6・・・・ボンディング線、7・・・・アルシミ
ニウ装配置a被覆層、ゲート電極、8・・・・メタルフ
レーム、9・・・・リードピン、10・・・・封止プラ
スチック。 代理人  大  岩  増  雄 第1図 1;4尋4シ幕オ丸    5:ハ0ンべ一ンヨン嗅第
2図 第3図 第4図 手続補正書(自発) 昭和60年3 月19 日 2、発明の名称 半導体メモリ装置 3、補正をする者 (1)明細書の図面の簡単な説明の欄 −四
FIG. 1 is a cross-sectional view of a main part of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is an explanatory plan view showing the overall structure of the same device, and FIG. 2 is a cross-sectional view. A: Semiconductor memory chip, B: Ponding butt portion, C: Memory portion, 1: Silicon semiconductor substrate, 2: Diffusion layer, 3: Oxidation membrane, 4
... Aluminum wiring layer, 5 ... Passivation film, 6 ... Bonding wire, 7 ... Aluminum wiring arrangement a coating layer, gate electrode, 8 ... Metal frame, 9 ... ...Lead pin, 10...Sealing plastic. Agent Masuo Oiwa Figure 1 1; 4 fathoms 4 curtains 5: 4 fathoms Figure 2 Figure 3 Figure 4 Procedural amendment (voluntary) March 19, 1985 2 , Title of the invention: Semiconductor memory device 3, Person making the amendment (1) Brief description of drawings in the specification - 4

Claims (1)

【特許請求の範囲】[Claims]  アルミニウム配線層上に、ボンディングパット部を除
いてパシベーション膜を形成した構成において、少なく
とも前記パシベーション膜上にアルミニウム配線被覆層
を被覆形成したことを特徴とする半導体メモリ装置。
1. A semiconductor memory device having a configuration in which a passivation film is formed on an aluminum wiring layer except for a bonding pad portion, and an aluminum wiring coating layer is formed to cover at least the passivation film.
JP59224816A 1984-10-24 1984-10-24 Semiconductor memory storage Pending JPS61102050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59224816A JPS61102050A (en) 1984-10-24 1984-10-24 Semiconductor memory storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59224816A JPS61102050A (en) 1984-10-24 1984-10-24 Semiconductor memory storage

Publications (1)

Publication Number Publication Date
JPS61102050A true JPS61102050A (en) 1986-05-20

Family

ID=16819645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59224816A Pending JPS61102050A (en) 1984-10-24 1984-10-24 Semiconductor memory storage

Country Status (1)

Country Link
JP (1) JPS61102050A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06154388A (en) * 1992-09-01 1994-06-03 Nordica Spa Brake gear
JPH06198023A (en) * 1992-10-21 1994-07-19 Nordica Spa Skate braking device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06154388A (en) * 1992-09-01 1994-06-03 Nordica Spa Brake gear
JPH06198023A (en) * 1992-10-21 1994-07-19 Nordica Spa Skate braking device

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