JPH03278552A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH03278552A JPH03278552A JP2079219A JP7921990A JPH03278552A JP H03278552 A JPH03278552 A JP H03278552A JP 2079219 A JP2079219 A JP 2079219A JP 7921990 A JP7921990 A JP 7921990A JP H03278552 A JPH03278552 A JP H03278552A
- Authority
- JP
- Japan
- Prior art keywords
- pads
- pellet
- wiring
- bonding
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000008188 pellet Substances 0.000 claims abstract description 28
- 239000004020 conductor Substances 0.000 abstract description 15
- 230000007797 corrosion Effects 0.000 abstract description 12
- 238000005260 corrosion Methods 0.000 abstract description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 2
- 230000009545 invasion Effects 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 3
- 238000012790 confirmation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に導体腐食によ
る断線を検出する機構に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a mechanism for detecting disconnection due to conductor corrosion.
従来、モールドパッケージを使用した半導体集積回路装
置は外部環境からモールドパッケージへ水分が侵入し、
半導体ペレット上のボンディングパツド等の導体パター
ンが腐食し断線に至る事故が発生していた。モールドパ
ッケージの中でもフラットパッケージ等の小型かつ薄型
のパッケージにおいて特にこの問題が顕著となっていた
。Conventionally, semiconductor integrated circuit devices using molded packages have been exposed to water entering the molded package from the external environment.
Accidents have occurred in which conductor patterns such as bonding pads on semiconductor pellets corrode and lead to disconnections. Among molded packages, this problem has become particularly noticeable in small and thin packages such as flat packages.
従来の半導体ペレットの一例としては第３図（ａ）、
（ｂ）に示すような構造のものが用いられていた。An example of a conventional semiconductor pellet is shown in Fig. 3(a).
A structure as shown in (b) was used.
そのため封止樹脂表面、外部リード等から侵入した水分
は直接、あるいはボンディングワイヤ（図示せず）を介
してボンディングパツド１１に達し、ペレット１０上の
導体を腐食する欠点があった。Therefore, moisture entering from the surface of the sealing resin, external leads, etc. reaches the bonding pad 11 either directly or via a bonding wire (not shown), and corrodes the conductor on the pellet 10.
最近の半導体集積回路装置を使用した電子装置は小型、
薄型化の傾向にあり、その電子装置に使用される半導体
集積回路装置も小型、薄型化の要求が強い。さらに電子
装置の小型、薄型化と共に使用される環境は高温、高湿
な環境での使用も多くなっているため、小型、薄型のモ
ールドパッケージの耐湿性を向上させる事が重要である
。しかし小型、薄型のモールドパッケージの耐湿性は、
セラミックのハーメチックシールパッケージ等と比較し
明らかに悪い。Electronic devices using recent semiconductor integrated circuit devices are small and
There is a trend toward thinner electronic devices, and there is a strong demand for semiconductor integrated circuit devices used in such electronic devices to be smaller and thinner. Furthermore, as electronic devices become smaller and thinner, they are increasingly being used in environments with high temperatures and humidity, so it is important to improve the moisture resistance of small and thin molded packages. However, the moisture resistance of small and thin molded packages is
This is clearly worse than ceramic hermetically sealed packages.
本発明の目的は、半導体ペレット上に水分の侵入による
内部導体の断線を検出する機構を備え、外部端子により
断線を監視できる半導体集積回路装置を提供することに
ある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that is equipped with a mechanism for detecting disconnection of an internal conductor due to moisture intrusion onto a semiconductor pellet, and can monitor disconnection using an external terminal.
本発明の半導体集積回路装置は半導体ペレットの一生面
に形成されたボンディングパツド部外周のペレット縁辺
部に設けられた配線と、この配線の両端に接続され、外
部リードにワイヤーポンディングされる第１及び第２の
パッドと、この配線の途中の任意の箇所に任意の個数形
成され、ワイヤーボンディングされない第３のバットと
、半導体ペレットの一生面を覆い、ボンディングパツド
部、第１．第２および第３のパッド部に開口部が設けら
れた絶縁膜とを有している。The semiconductor integrated circuit device of the present invention includes wiring provided on the edge of the pellet on the outer periphery of a bonding pad portion formed on the whole surface of a semiconductor pellet, and wire bonding wires connected to both ends of this wiring and wire-bonded to external leads. 1 and 2nd pads, a third butt which is formed in an arbitrary number at an arbitrary location in the middle of the wiring and is not wire bonded, and which covers the whole surface of the semiconductor pellet and covers the bonding pad portion, the first . and an insulating film in which openings are provided in the second and third pad portions.
このような構成により、半導体ペレットを封止した樹脂
モールド外から水分が侵入した場合に、ボンディングパ
ツド部外周に設けられた配線の途中に形成された第３の
パッドが他のパッドより先に腐食、断線を生じ、第１．
第２のパッド間の導通を断つ。そのため、第１．第２の
パッドに接続された外部リードを監視することにより、
水分の侵入状況を把握できるものである。With this configuration, if moisture intrudes from outside the resin mold that seals the semiconductor pellet, the third pad formed in the middle of the wiring provided around the outer periphery of the bonding pad will be able to reach the third pad before the other pads. Corrosion and wire breakage occur, and 1.
Breaking the conduction between the second pads. Therefore, the first. By monitoring the external lead connected to the second pad,
This allows the situation of moisture intrusion to be ascertained.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、 （ｂ）に本発明の第１の実施例の半導
体集積回路装置を示す。第１図（ａ）のように半導体ペ
レット１００の中央部には内部回路１０７が設けられ、
その外周に外部リードと接続されるボンディングパツド
１０５が配置されている。これらのボンディングパツド
１０５と半導体ペレット１００の縁辺部との間には、複
数μｍの導通確認用配線１０１が半導体ペレット１００
の四辺に沿って設けられている。さらにこの配線の両端
には第１および第２のパッド１０２，１０３が設けられ
、配線の途中の任意箇所に第３のパッド１０４が設けら
れている。FIGS. 1(a) and 1(b) show a semiconductor integrated circuit device according to a first embodiment of the present invention. As shown in FIG. 1(a), an internal circuit 107 is provided in the center of the semiconductor pellet 100,
A bonding pad 105 connected to an external lead is arranged on its outer periphery. Between these bonding pads 105 and the edge of the semiconductor pellet 100, a conduction check wiring 101 of several μm is connected to the semiconductor pellet 100.
located along the four sides of the Further, first and second pads 102 and 103 are provided at both ends of this wiring, and a third pad 104 is provided at an arbitrary location along the wiring.
第１および第２のパッド１０２．１０３は他のパッケー
ジパッド同様金属ワイヤにより半導体集積回路装置の外
部リード端子（図示せず）と電気的に接続される。第３
のパッド１０４は、第１図（ｂ）に示すように外部リー
ド端子と接続するためのワイヤーポンディングは実施し
ないが、半導体ペレット１００の主面を覆う保護膜１０
６には、第３のパッド１０４上にも他のボンディングパ
ツド同様、開口部が設けられる。The first and second pads 102 and 103, like other package pads, are electrically connected to external lead terminals (not shown) of the semiconductor integrated circuit device by metal wires. Third
As shown in FIG. 1(b), the pad 104 does not perform wire bonding for connection to an external lead terminal, but is formed using a protective film 10 that covers the main surface of the semiconductor pellet 100.
6, an opening is provided on the third pad 104 as well as on the other bonding pads.
一般にモールドパッケージの耐湿性試験を実施した場合
、保護膜により半導体ペレットの表面を覆われていない
ボンディングパツド部より導体腐食が始まる傾向が強い
。さらにボンディングパツド部の導体腐食をボンディン
グワイヤの有無により比較した場合、ボンディングワイ
ヤのない方がボンディングワイヤのある場合よりも導体
腐食が発生しやすい。したがって第１図に示す様に、導
体確認用配線１０１は半導体チップの周辺部のボンディ
ングパツド近傍に配置し、さらに第１および第２のパッ
ド１０２，１０３間にワイヤーポンディングを行なわな
い腐食、断線検出用の第３のパッド１０４を挿入するこ
とにより半導体腐食による断線の検出感度を高めること
ができる。Generally, when a moisture resistance test is conducted on a molded package, conductor corrosion tends to start at the bonding pad where the surface of the semiconductor pellet is not covered with a protective film. Furthermore, when comparing the conductor corrosion in the bonding pad portion with and without the bonding wire, conductor corrosion is more likely to occur without the bonding wire than with the bonding wire. Therefore, as shown in FIG. 1, the conductor confirmation wiring 101 is placed in the vicinity of the bonding pads on the periphery of the semiconductor chip, and furthermore, corrosion is prevented by not performing wire bonding between the first and second pads 102 and 103. By inserting the third pad 104 for detecting disconnection, the sensitivity for detecting disconnection due to semiconductor corrosion can be increased.
このような構成により第１および第２のパッド１０２．
１０３にワイヤー接続された外部リードでパッケージ内
部の導体腐食、断線の状況を外部から検出できる。ここ
で、導体確認用配線１０１は内部回路１０７で使用され
る配線と同時に形成されることが望ましく、配線幅も内
部回路１０７で使用される最小配線幅と同一程度とする
ことが好ましい。With this configuration, the first and second pads 102.
Corrosion of the conductor or disconnection inside the package can be detected from the outside using an external lead connected to the wire 103. Here, the conductor confirmation wiring 101 is desirably formed at the same time as the wiring used in the internal circuit 107, and the wiring width is also preferably approximately the same as the minimum wiring width used in the internal circuit 107.
第２図（ａ）、 （ｂ）に本発明の第２の実施例を示す
。本実施例は第１の実施例と比較し、ボンディングを実
施しない第３のパッド２０４を半導体ぺレット２００の
四隅にそｈぞれ１個、計４個配置することにより導体腐
食による断線の検出感度を高めている。A second embodiment of the present invention is shown in FIGS. 2(a) and 2(b). In comparison with the first embodiment, this embodiment detects disconnection due to conductor corrosion by arranging a total of four third pads 204 that do not perform bonding, one at each of the four corners of the semiconductor pellet 200. Increased sensitivity.
以上説明したように本発明は、導体腐食による断線第１
および第２のパッド間に設けられた腐食、断線検出用の
第３のパッドにより導体状態を検出監視することができ
るため、動作不良又は近い将来動作不良となる可能性の
高い半導体集積回路装置を検出することが可能である。As explained above, the present invention is capable of handling the first wire breakage due to conductor corrosion.
The conductor condition can be detected and monitored by the third pad for detecting corrosion and disconnection provided between the second pads, so semiconductor integrated circuit devices that are malfunctioning or are likely to malfunction in the near future can be It is possible to detect.
そのため、多数個の半導体集積回路装置が実装されたプ
リント基板上において、動作不良又は近い将来動作不良
となる可能性の高い半導体集積回路装置を検出する拳は
、半導体集積回路装置を使用した電子装置の修理又は保
守を実施する上において、非常に有益である。Therefore, the best way to detect semiconductor integrated circuit devices that are malfunctioning or are likely to malfunction in the near future on a printed circuit board on which a large number of semiconductor integrated circuit devices are mounted is to detect electronic devices using semiconductor integrated circuit devices. This is very useful when carrying out repair or maintenance.
以上の説明ではモールドパッケージの場合について説明
したが電子装置の小型化、薄型化のために半導体ペレッ
トを直接プリント基板上に実装するという実装方式も考
えられ、この場合においても本発明の効果は大きい。The above explanation deals with the case of a molded package, but in order to make electronic devices smaller and thinner, a mounting method in which semiconductor pellets are directly mounted on a printed circuit board can also be considered, and the effects of the present invention are significant even in this case. .
第１図（ａ）は本発明の第１の実施例を示す平面図、第
１図（ｂ）は第１図（ａ）のＡ−Ａ’断面図、第２図（
ａ）は本発明の第２の実施例を示す平面図、第２図（ｂ
）は第２図（ａ）のＢ−Ｂ’断面図、第３図（ａ）は従
来例を示す平面図、第３図（ｂ）は第３図（ａ）のｃ−
ｃ’断面図を示す。
１００．２００．１０・・・・・・半導体ペレット、ｌ
ｏｔ、２０１・・・・・・導通確認用配線、１０２゜２
０２・・・・・・第１のパッド、１０３，２０３・・・
・・・第２のパッド、１０４，２０４・・・・・・第３
のパッド、１０５．２０５．１１・・・・・・ボンディ
ングパツド、１０６．２０６．１２・・・・・・保護膜
、１０７，２０７゜１３・・・・・・内部回路。FIG. 1(a) is a plan view showing the first embodiment of the present invention, FIG. 1(b) is a sectional view taken along line AA' in FIG. 1(a), and FIG.
a) is a plan view showing the second embodiment of the present invention, FIG. 2(b)
) is a sectional view taken along line BB' in FIG. 2(a), FIG. 3(a) is a plan view showing the conventional example, and FIG. 3(b) is a sectional view taken along line c--in FIG.
A c′ cross-sectional view is shown. 100.200.10... Semiconductor pellet, l
ot, 201... Wiring for continuity check, 102゜2
02...First pad, 103,203...
...Second pad, 104,204...Third
Pad, 105.205.11... Bonding pad, 106.206.12... Protective film, 107,207°13... Internal circuit.
Claims (1)
ングパツド部と前記半導体ペレット縁辺部との間に前記
半導体ペレットの外周に沿って設けられた配線と、前記
配線の両端に形成され、ワイヤーボンディングの施され
た第１及び第２のパッドと、前記配線の途中の任意の箇
所に任意の個数設けられたワイヤーボンディングが施さ
れない第３のパッドと、前記ボンディングパツド部と前
記第１、第２、第３のパッド上に開口部が設けられ、前
記半導体ペレット上を覆う絶縁膜とを有することを特徴
とする半導体集積回路装置。A wiring provided along the outer periphery of the semiconductor pellet between a bonding pad portion disposed along the periphery of the semiconductor pellet and an edge portion of the semiconductor pellet, and a wiring formed at both ends of the wiring for wire bonding. the first and second pads to which wire bonding is applied; a third pad to which wire bonding is not applied and which is provided in an arbitrary number at an arbitrary point in the wiring; and the bonding pad portion and the first and second pads. . A semiconductor integrated circuit device, comprising: an opening provided on a third pad; and an insulating film covering the semiconductor pellet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2079219A JPH03278552A (en) | 1990-03-28 | 1990-03-28 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2079219A JPH03278552A (en) | 1990-03-28 | 1990-03-28 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03278552A true JPH03278552A (en) | 1991-12-10 |
Family
ID=13683814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2079219A Pending JPH03278552A (en) | 1990-03-28 | 1990-03-28 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03278552A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007027685A (en) * | 2005-06-17 | 2007-02-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
| JP2011142211A (en) * | 2010-01-07 | 2011-07-21 | Mitsubishi Electric Corp | Semiconductor device |
-
1990
- 1990-03-28 JP JP2079219A patent/JPH03278552A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007027685A (en) * | 2005-06-17 | 2007-02-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
| US7595557B2 (en) | 2005-06-17 | 2009-09-29 | Panasonic Corporation | Semiconductor device and manufacturing method thereof |
| JP4592634B2 (en) * | 2005-06-17 | 2010-12-01 | パナソニック株式会社 | Semiconductor device |
| JP2011142211A (en) * | 2010-01-07 | 2011-07-21 | Mitsubishi Electric Corp | Semiconductor device |
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