JPS61101855A - 多重仮想記憶システムにおけるｔｌｂ制御方式 - Google Patents

多重仮想記憶システムにおけるｔｌｂ制御方式

Info

Publication number
JPS61101855A
JPS61101855A JP59223240A JP22324084A JPS61101855A JP S61101855 A JPS61101855 A JP S61101855A JP 59223240 A JP59223240 A JP 59223240A JP 22324084 A JP22324084 A JP 22324084A JP S61101855 A JPS61101855 A JP S61101855A
Authority
JP
Japan
Prior art keywords
tlb
logical address
registered
address
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59223240A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0351015B2 (enrdf_load_stackoverflow
Inventor
Tsuyoshi Mori
森　強
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59223240A priority Critical patent/JPS61101855A/ja
Publication of JPS61101855A publication Critical patent/JPS61101855A/ja
Publication of JPH0351015B2 publication Critical patent/JPH0351015B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP59223240A 1984-10-24 1984-10-24 多重仮想記憶システムにおけるｔｌｂ制御方式 Granted JPS61101855A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59223240A JPS61101855A (ja) 1984-10-24 1984-10-24 多重仮想記憶システムにおけるｔｌｂ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59223240A JPS61101855A (ja) 1984-10-24 1984-10-24 多重仮想記憶システムにおけるｔｌｂ制御方式

Publications (2)

Publication Number Publication Date
JPS61101855A true JPS61101855A (ja) 1986-05-20
JPH0351015B2 JPH0351015B2 (enrdf_load_stackoverflow) 1991-08-05

Family

ID=16794992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59223240A Granted JPS61101855A (ja) 1984-10-24 1984-10-24 多重仮想記憶システムにおけるｔｌｂ制御方式

Country Status (1)

Country Link
JP (1) JPS61101855A (enrdf_load_stackoverflow)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553077A (en) * 1978-06-23 1980-01-10 Fujitsu Ltd Multi-virtual data processing system
JPS56163570A (en) * 1980-05-16 1981-12-16 Fujitsu Ltd Multiple imaginary storage control system for multiple virtual computer system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553077A (en) * 1978-06-23 1980-01-10 Fujitsu Ltd Multi-virtual data processing system
JPS56163570A (en) * 1980-05-16 1981-12-16 Fujitsu Ltd Multiple imaginary storage control system for multiple virtual computer system

Also Published As

Publication number Publication date
JPH0351015B2 (enrdf_load_stackoverflow) 1991-08-05

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