JPS56163570A - Multiple imaginary storage control system for multiple virtual computer system - Google Patents

Multiple imaginary storage control system for multiple virtual computer system

Info

Publication number
JPS56163570A
JPS56163570A JP6483880A JP6483880A JPS56163570A JP S56163570 A JPS56163570 A JP S56163570A JP 6483880 A JP6483880 A JP 6483880A JP 6483880 A JP6483880 A JP 6483880A JP S56163570 A JPS56163570 A JP S56163570A
Authority
JP
Japan
Prior art keywords
flag
tlb
imaginary
register
common
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6483880A
Other languages
Japanese (ja)
Other versions
JPS5925303B2 (en
Inventor
Hitoshi Mogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55064838A priority Critical patent/JPS5925303B2/en
Publication of JPS56163570A publication Critical patent/JPS56163570A/en
Publication of JPS5925303B2 publication Critical patent/JPS5925303B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To increase the application efficiency of a TLB, by storaging the TLB only with an entry for the region which is common among plural imaginary spaces and using in common the entry to the plural imaginary spaces. CONSTITUTION:A common region indicating flag 123 and an identification (ID) bit 124 are provided in a TLB12. The flag is ''1'' with the common region and otherwise ''0''. The ID bit stores the imaginary storage space ID (substitute with STO-ID obtained by adding ID number to head address of corresponding segment table) when the flag is ''1'' and stores a imaginary computer (VM)ID when the flag is ''0'' respectively. An index is given to the TLB12 through a part 112 of a logic address register 11, and a comparator 18 compares a part 121 of the output with a part 111 of an address register. At the same time, a multiplexer 16 selects an STO-ID register 15 or a VM-ID register 14 according to the value of the flag and then compares 19 the corresponding contents with the ID output 124 of the TLB. When both comparators 18 and 19 coincide, the output 122 of the TLB becomes identical with the desired real address.
JP55064838A 1980-05-16 1980-05-16 Multiple virtual memory control method in multiple virtual computer system Expired JPS5925303B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55064838A JPS5925303B2 (en) 1980-05-16 1980-05-16 Multiple virtual memory control method in multiple virtual computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55064838A JPS5925303B2 (en) 1980-05-16 1980-05-16 Multiple virtual memory control method in multiple virtual computer system

Publications (2)

Publication Number Publication Date
JPS56163570A true JPS56163570A (en) 1981-12-16
JPS5925303B2 JPS5925303B2 (en) 1984-06-16

Family

ID=13269771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55064838A Expired JPS5925303B2 (en) 1980-05-16 1980-05-16 Multiple virtual memory control method in multiple virtual computer system

Country Status (1)

Country Link
JP (1) JPS5925303B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61101855A (en) * 1984-10-24 1986-05-20 Fujitsu Ltd Tlb controlling system in multiple virtual memory system
JPS6437635A (en) * 1987-08-04 1989-02-08 Fujitsu Ltd Inter-cpu communication instruction executing system in virtual computer
JPH01255945A (en) * 1988-04-06 1989-10-12 Hitachi Ltd Address converter in virtual computer
JP2008512758A (en) * 2004-09-07 2008-04-24 フリースケール セミコンダクター インコーポレイテッド Virtual address cache and method for sharing data stored in virtual address cache

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61101855A (en) * 1984-10-24 1986-05-20 Fujitsu Ltd Tlb controlling system in multiple virtual memory system
JPH0351015B2 (en) * 1984-10-24 1991-08-05 Fujitsu Ltd
JPS6437635A (en) * 1987-08-04 1989-02-08 Fujitsu Ltd Inter-cpu communication instruction executing system in virtual computer
JPH01255945A (en) * 1988-04-06 1989-10-12 Hitachi Ltd Address converter in virtual computer
JP2008512758A (en) * 2004-09-07 2008-04-24 フリースケール セミコンダクター インコーポレイテッド Virtual address cache and method for sharing data stored in virtual address cache

Also Published As

Publication number Publication date
JPS5925303B2 (en) 1984-06-16

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