JPS61100953A - Package for semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a package having excellent thermal conductivity and assembly operating properties without increasing heat resistance due to the cracks and voids of a semicondutor element by forming a plating layer, which consists of a base metal having thermal conductivity higher than a base material for a heat sink and has thickness of a specific value or more, to the heat sink. CONSTITUTION:A heat sink 301 is constituted in such a manner that a plating layer 301-2, which is composed of a base metal having thermal conductivity higher than a base material 301-1 such as Cu and has thickness of 10mum or more, and a Ni plating layer 304 and an Au plating 305 deposited on the layer 301-2 in succession are formed onto the base material 301-1 consisting of an alloy, such as a CuW alloy, Kovar, a FeNi alloy, etc. Accordingly, since the base material 301-1 is processed to a required shape and the Cu plating layer 301-2 can be formed on the whole surface in uniform thickness while being fast stuck to the base material 301-1, the thickness of the Cu plating layer 301-2 is brought to 10mum or more in order to prevent the warp of the heat sink 301 and stress on the processing of the heat sink 301, thus acquiring the radiator plate having low heat resistance.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a container for semiconductor devices.

[Conventional technology]

Generally, a t5 output semiconductor device 7iJ container has a heat sink for fixing a semiconductor element and for dissipating heat from the semiconductor element. The material for this heat sink is copper, steel.
Tungsten alloy, iron-nickel alloy, Kovar, etc. are used for the casing, and the surface of the heat sink is coated with nickel plating to improve the wearability of the solder metal for bonding semiconductor elements and to prevent corrosion of the heat sink. After that, gold plating or follow-up plating is performed. The thickness of the plating layer is nickel plating = 0.5 to 6 μm, gold plating: 0.1 to 6 μm.
10 μm, silver plating: 1 to 15 μm is common, but in particular, gold plating, free plating, etc. are smoked precious metals, and as the plating thickness increases, the price increases, so it is necessary to match the quality required for semiconductor devices. Therefore, the plating thickness is made as thin as possible.

GaAsFET mounted in these semiconductor device containers
As semiconductor devices such as In order to lower the abrasive resistance, elements have become thinner.

Therefore, as a container for semiconductor devices, Heat Transfer 2! In addition to the real problem of direct failure, it is also an important issue to prevent cracks in semiconductor devices due to the thermal tension difference between the heat sink used and the semiconductor device.

However, when steel is used as the heat sink material, the thermal resistance is low (high thermal conductivity), but since copper has a large coefficient of thermal expansion, if the external diameter of the element exceeds about 2 mm, cracks are likely to occur in the element. Become. In addition, when Kovar material is used as the heat sink material, there is no problem of cracking of the element due to thermal stress, but due to the low thermal conductivity of Kovar material,
This has the problem of high thermal resistance. In order to make these relationships easier to understand, typical heat sink materials are summarized in a table along with their heat conduction coefficients and coefficients of thermal expansion, as shown in Table 1.

The following methods have been proposed as methods for improving such containers for semiconductor devices.

(1) A disk made of a material with high thermal conductivity such as Gu is bonded to a material with a small thermal expansion coefficient and low thermal conductivity (for example, Kovar iron-nickel alloy, etc.) using a brazing material such as AnSn alloy. , a method of fixing semiconductor elements on a disk.

(2) A material with high thermal conductivity such as KCu, a base material with a small coefficient of thermal expansion and low thermal conductivity, is bonded (by pressure bonding, etc.) in advance, processed into an appropriate shape, and used as a heat sink. Method.

Notes to Table 1 ◎: Good Δ: Unsuitable depending on conditions in,
FIG. 3(B) is an enlarged sectional view of part A in FIG. 3(JL).

Fig. 2, Fig. 3 (a) Kite, heat sink 101, 201
Side wall members 102, 202 made of 1-alumina or the like are fixed on top, and external lead-out terminals 103, 203 are provided on these side wall members 102, 202. Also, heat sink 101.
For corrosion prevention of 201 fC, as shown in Figure 3(b),
An Au plating layer 205 is provided with a Ni plating layer 204 as a base.

In addition, in the conventional semiconductor device container shown in FIGS. 3(&) and (b)K, as described in method (2) above,
The heat sink 201 is made of a material having a small coefficient of thermal expansion, such as Kovar,
A plate material 202 having high thermal conductivity, such as Cu, is bonded to a base material 201-1 made of a FeNi alloy or the like.

[Problem that the invention seeks to solve]

In the conventional semiconductor device container shown in FIG.
As the material of 1, for example, CuW alloy, copal, FeN
When using alloys such as i, these alloys have low thermal conductivity, so in order to increase thermal resistance, the heat sink 10
When Cu, which has a high thermal conductivity, is used as the material for the heat dissipation plate 101, there is a problem that the element tends to crack due to thermal stress caused by the difference in thermal expansion between the semiconductor element and the heat sink 101. The base material 201-1 and the plate material 201-2 tend to warp due to the difference in thermal expansion coefficient between the material 201-1 and the plate material 201-2, stress during external shaping of the heat sink 201, and thermal stress during the container assembly process. There is a problem that peeling easily occurs at the joint between the two.

The method (1) above has problems in that voids are generated in the brazing material layer, increasing thermal resistance and increasing the number of parts, resulting in high cost.

Therefore, the present invention combines the problems of conventional containers for semiconductor devices, and provides a semiconductor device with no increase in thermal resistance due to semiconductor element glue, voids, good thermal conductivity, and excellent assembly workability. The purpose is to provide containers for

[Means for solving problems]

The container for a semiconductor device of the present invention is a container for a semiconductor device having a heat sink, in which the heat sink is provided in close contact with a base material of the heat sink, and has a thickness made of a base metal having a higher thermal conductivity than that of the base material. It has a plating layer of 10 μm or more.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1(a) is a sectional view showing one embodiment of the present invention, and FIG. 1(a) is an enlarged sectional view of section B in FIG. 1(a).

In this embodiment, the heat sink 301 is made of, for example, a CuW alloy.

A base material 301-1 made of Kovar, FeNi alloy, etc.
A base metal with higher thermal conductivity than the base material 301-1, such as Cu
A plating layer 301-2 with a thickness of 10 μm or more consisting of
It is composed of a Ni plating layer 304 and an Au plating layer 305 deposited sequentially thereon.

In addition, in FIG. 1(a), 302 is a side wall member;
This is a 3D lead-out terminal.

According to this embodiment, after processing the base material 301-1 into the required shape, the Cu plating layer 301-2 is applied to the base material 301-2 with a uniform thickness over the entire surface.
Since the Cu plating layer 3 can be formed in close contact with the heat sink 301, the warping of the heat sink 301 and the stress caused by the application of the heat sink 301 can be avoided.
No peeling of 01-2 occurs. Furthermore, since the thickness of the Cu plating layer 301-2 is set to 10 μm or more, a heat sink having a low thermal resistance as shown in Table 2 can be obtained.

Table 2 shows heat sinks having the structure of the semiconductor device container of the present invention, with various thicknesses of the Cu plating layer, and heat sinks of the conventional semiconductor device container shown in FIG. The thermal resistance, thermal expansion coefficient, and pattern are shown for the case where the substrate is CuW alloy and Kovar. Note that the numerical values are expressed as relative ratios with the conventional example as a reference value lθ0.

As is clear from this result, in terms of thermal resistance, Cu
When the plating thickness is 5 μm or less, no effect is observed, whereas when the plating thickness is 10 μm or more, the effect is remarkable. Further, regarding the coefficient of thermal expansion, almost no change is observed in the Cu plating thickness.

Table 2 Note) Ratio 412 condition heat sink thickness: 1. O (n times) Heat source size: ' Q, 5 (mm) Exterior plating thickness Ni plating: 5e = 1 [μm] A section plating: J = 2C
[μm] Although the embodiments using the Cu plating layer of the present invention have been described above, the non-invention is applicable regardless of the shape of the semiconductor device container, the material of the heat sink base material, etc. It goes without saying that it can also be used commercially for plating layers of base metals.

〔Effect of the invention〕

As described in detail above, according to the present invention, the heat sink has a plated layer having a thickness of 10 μm or more and made of a base metal having a higher thermal conductivity than the base material, which is provided in close contact with the base material of the heat sink. Therefore, it is possible to obtain a container for a #-conductor device that has good thermal conductivity and excellent assembly workability without increasing thermal resistance due to semiconductor element glue or voids.

4. Brief explanation of the drawings Figure 1(a) is a cross-sectional view showing one embodiment of the present invention, Figure 1(a) is an enlarged cross-sectional view of section B in Figure 11d(a), and cylinder 2 is a conventional semiconductor. A sectional view showing an example of a device container, FIG.
) is a sectional view showing another example of a conventional container for semiconductor devices, and FIG. 3(b) is an enlarged sectional view of section A in FIG. 3(a).

301... Heat sink, 301-1... Base material, 301-2... Cu plating +1.302.
...Side wall member, 303...External lead-out terminal, 304...Ni plating%, 305...
・Au plating layer.

sieve $/figure Graduation 2nd figure (a) (L) Figure 3 12F+8-

Claims (1)

[Claims] In a semiconductor device container having a heat sink, the heat sink has a plating layer with a thickness of 10 μm or more made of a base metal having a higher thermal conductivity than the base material, which is provided in close contact with the base material of the heat sink. Container for semiconductor devices with special features.