JPS61100663A - Smoothing circuit - Google Patents

Smoothing circuit

Info

Publication number
JPS61100663A
JPS61100663A JP22319584A JP22319584A JPS61100663A JP S61100663 A JPS61100663 A JP S61100663A JP 22319584 A JP22319584 A JP 22319584A JP 22319584 A JP22319584 A JP 22319584A JP S61100663 A JPS61100663 A JP S61100663A
Authority
JP
Japan
Prior art keywords
circuit
output
voltage
input
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22319584A
Other languages
Japanese (ja)
Inventor
Kiyoshi Inoue
井上 喜芳
Tsutomu Sato
勉 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP22319584A priority Critical patent/JPS61100663A/en
Publication of JPS61100663A publication Critical patent/JPS61100663A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make it possible to miniaturize a smoothing circuit and to enhance the economical efficiency thereof by reducing the electrostatic capacity of the condenser for constituting an integrating circuit, by comparing the output of the integrating circuit with a predetermined threshold value by a comparing circuit. CONSTITUTION:When the input signal vl inputted to an input terminal 1 is 0 volt, the output voltage v2 outputted from a gate 2 is held to +5 volt and, because a condenser 4 is charged through a resistor 3, a comparing circuit 7outputs a logical value 1. When a call-out signal arrives the input terminal in this state, the condenser 4 repeats charging and discharging at every half cycle of 16 Hz. At this time, by setting the resistance value of the resistor 3 and the electrostatic capacity value of the condenser 4 so that outlet voltage v3 does not exceed threshold value voltage Vt, an output signal v4 comes to a logical value 0 and it can be succeedingly displayed that the call-out signal arrived the input terminal 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は交流信号を検出する回路における平滑化回路の
改良に関す。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in smoothing circuits in circuits for detecting alternating current signals.

例えば自動交換機において、電話機の呼出信号に使用さ
れる交流信号(例えば16ヘルツ)を検出する必要が生
ずる場合が多い。
For example, in automatic switchboards, it is often necessary to detect alternating current signals (eg, 16 Hertz) used for telephone ringing signals.

〔従来の技術〕[Conventional technology]

第3図はこの種呼出信号検出回路における従来ある平滑
化回路の一例を示す図であり、第4図は第3図における
各部の信号波形の一例を示す図である。第3図において
、入力端子lはゲート2を介して抵抗3およびコンデン
サ4から構成される積分回路5に接続され、該積分回路
5は出力端子6に接続されている。
FIG. 3 is a diagram showing an example of a conventional smoothing circuit in this type of calling signal detection circuit, and FIG. 4 is a diagram showing an example of signal waveforms at various parts in FIG. In FIG. 3, the input terminal l is connected via the gate 2 to an integrating circuit 5 composed of a resistor 3 and a capacitor 4, and the integrating circuit 5 is connected to an output terminal 6.

第3図および第4図において、入力端子1に入力される
入力信号v1が0ボルトの場合には、ゲート2から出力
される出力電圧v2は所定電圧■0(例えば+5ボルト
)に維持される。かがる状態においては、コンデンサ4
は抵抗3を経由して充電され、出力端子6に出力する出
力電圧v3を+5ボルトに設定する。
In FIGS. 3 and 4, when the input signal v1 input to the input terminal 1 is 0 volts, the output voltage v2 output from the gate 2 is maintained at a predetermined voltage 0 (for example, +5 volts). . In the bending state, capacitor 4
is charged via the resistor 3, and sets the output voltage v3 outputted to the output terminal 6 to +5 volts.

かかる状態で、時点tQに入力端子1に呼出信号が到着
し、入力信号v1がO乃至+5ボルト間を16ヘルツで
振動すると、ゲート2から出力される出力電圧v2は入
力信号v1が0乃至+2゜5ボルトを示す場合(時点t
Q乃至t1、t2乃至t3、t4乃至t5、・・・)に
+5ボルトに設定され、また出力電圧v2が+2.5乃
至+5ボルトを示す場合(時点tl乃至t2、t3乃至
t4、・・・)にOボルトに設定される。出力電圧v2
がOボルトに設定される時点tl等においてコンデンサ
4はゲート2を介して直ちに放電され、出力電圧v3を
0ボルトに設定する。また出力電圧v2が+5ボルトに
設定され時点t2等において、コンデンサ4は抵抗3を
経由して充電され、出力電圧■3は抵抗3の抵抗値およ
びコンデンサ4の静電容量値により定まる時定数に基づ
き徐々に上昇する。然し16ヘルツの半周期(即ち31
.25ミリ秒)経過した時点t3等において、出力電圧
■2は再びOポルトとなる為コンデンサ4は再び放電さ
れ、出力電圧v3は再びOボルトに設定される。
In this state, when a call signal arrives at the input terminal 1 at time tQ and the input signal v1 oscillates between 0 and +5 volts at 16 hertz, the output voltage v2 output from the gate 2 will change when the input signal v1 is 0 to +2.゜When indicating 5 volts (time t
Q to t1, t2 to t3, t4 to t5, . . . ) is set to +5 volts, and the output voltage v2 shows +2.5 to +5 volts (times tl to t2, t3 to t4, . . . ). ) is set to O volts. Output voltage v2
At a time tl, etc., when V is set to O volts, the capacitor 4 is immediately discharged via the gate 2, setting the output voltage v3 to 0 volts. In addition, when the output voltage v2 is set to +5 volts, the capacitor 4 is charged via the resistor 3 at a time point t2, etc., and the output voltage V2 becomes a time constant determined by the resistance value of the resistor 3 and the capacitance value of the capacitor 4. increase gradually based on However, the half period of 16 Hz (i.e. 31
.. At a time point t3 (25 milliseconds) has elapsed, the output voltage (2) becomes O volts again, so the capacitor 4 is discharged again, and the output voltage v3 is set to O volts again.

今例えば抵抗3を1.2キロオーム、コンデンサ4を約
150マイクロフアラドに設定すれば、時点t3におい
ても出力電圧v3は0.8ボルトを越えることは無く、
例えばOボルト乃至0.8ボルトを論理値0、+2.4
乃至+5ボルトを論理値1と判定するT T L 論理
回路を出力端子6に接続した場合、該論理回路は時点t
1以降出力電圧■3が継続的に論理値Oに設定されてい
ると識別し、呼出信号が到着したと判定する。
For example, if the resistor 3 is set to 1.2 kilohms and the capacitor 4 is set to about 150 microfarads, the output voltage v3 will not exceed 0.8 volts even at time t3.
For example, O volts to 0.8 volts are logical values 0, +2.4
When a T T L logic circuit that determines a logic value of 1 to +5 volts is connected to the output terminal 6, the logic circuit is connected to the output terminal 6.
1 and thereafter, it is determined that the output voltage (3) is continuously set to the logical value O, and it is determined that the calling signal has arrived.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

以上の説明から明らかな如く、従来ある平滑化回路にお
いては、入力端子1に呼出信号が到着したことを継続的
に表示する為に積分回路5の出力電圧v3を直接出力し
た為、コンデンサ4の静電容量値を大きく設定する必要
があり、当該平滑化回路の小型化および経済化を妨げる
結果となる。
As is clear from the above explanation, in a conventional smoothing circuit, the output voltage v3 of the integrating circuit 5 is directly outputted in order to continuously display that the call signal has arrived at the input terminal 1, so the capacitor 4 It is necessary to set a large capacitance value, which hinders miniaturization and economicalization of the smoothing circuit.

〔問題点を解決するための手段〕[Means for solving problems]

前記問題点は、ゲート回路の出力端子に抵抗およびコン
デンサから構成される積分回路を接続し、所定周波数の
交流信号が前記ゲート回路に入力された場合に前記積分
回路の出力を所定電圧範囲に維持する回路において、前
記積分回路の出力を比較回路の一方の入力端子に入力し
、該比較回路の他方の端子に所定の閾値電圧を入力し、
前記ゲート回路に前記交流信号が入力された場合に該比
較回路の出力を所定電位に維持することを特徴とする本
発明により解決される。
The above problem is solved by connecting an integrating circuit consisting of a resistor and a capacitor to the output terminal of the gate circuit, and maintaining the output of the integrating circuit within a predetermined voltage range when an AC signal of a predetermined frequency is input to the gate circuit. In the circuit, the output of the integrating circuit is inputted to one input terminal of a comparison circuit, and a predetermined threshold voltage is inputted to the other terminal of the comparison circuit,
The problem is solved by the present invention, characterized in that when the alternating current signal is input to the gate circuit, the output of the comparator circuit is maintained at a predetermined potential.

〔作用〕[Effect]

即ち本発明によれば、積分回路の出力は比較回路により
所定の閾値電圧と比較される為、閾値電圧を充分高く設
定することにより、積分回路の時定数を小さく設定する
ことが可能となり、当該平滑化回路の小型化および経済
化が図られる。
That is, according to the present invention, since the output of the integrating circuit is compared with a predetermined threshold voltage by the comparing circuit, by setting the threshold voltage sufficiently high, it is possible to set the time constant of the integrating circuit to be small. The smoothing circuit can be made smaller and more economical.

〔実施例〕〔Example〕

以下、本発明の一実施例を図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例による平滑化回路を示す図で
あり、第2図は第1図における各部の信号波形の一例を
示す図である。なお、全図を通じて同一符号は同一対象
物を示す。
FIG. 1 is a diagram showing a smoothing circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of signal waveforms at various parts in FIG. 1. Note that the same reference numerals indicate the same objects throughout the figures.

第1図においては、抵抗3およびコンデンサ4から構成
される積分回路5の出力電圧v3は比較回路7の一方の
入力端子(+)に入力さ・れ、比較回路7の他方の入力
端子(−)には閾値電圧Vtが入力される。比較回路7
は出力電圧v3と閾値電圧Vtとを比較し、出力電圧v
3が閾値電圧Vtを越えれば、出力信号v4を論理値1
に設定し、出力電圧v3が閾値電圧Vt以下であれば出
力信号v4を論理値0に設定する。なお閾値電圧■【は
、積分回路5の時定数を考慮した上で充分高い電圧(例
えば+4ボルト)に設定されている。更に比較回路7の
出力信号v4は出力端子6に出力される。
In FIG. 1, an output voltage v3 of an integrating circuit 5 composed of a resistor 3 and a capacitor 4 is input to one input terminal (+) of a comparator circuit 7, and the other input terminal (- ) is inputted with the threshold voltage Vt. Comparison circuit 7
compares the output voltage v3 and the threshold voltage Vt, and calculates the output voltage v
3 exceeds the threshold voltage Vt, the output signal v4 becomes a logical value 1.
, and if the output voltage v3 is less than or equal to the threshold voltage Vt, the output signal v4 is set to a logical value of 0. Note that the threshold voltage {circle around (2)} is set to a sufficiently high voltage (for example, +4 volts) in consideration of the time constant of the integrating circuit 5. Furthermore, the output signal v4 of the comparison circuit 7 is outputted to the output terminal 6.

第1図および第2図において、入力端子1に人力される
入力信号vlが0ボルトの場合には、ゲート2から出力
される出力電圧v2は第3図における生同様所定電圧V
O(例えば+5ボルト)に維持される。かかる状態にお
いては、コンデンサ4は抵抗3を経由して充電され、出
力電圧■3を+5ボルトに設定する。比較回路7は出力
電圧V3と閾値電圧Vtとを比較し、出力電圧v3が閾
値電圧Vtより高電圧であることを識別すると、出力端
子6に出力する出力信号v4を論理値1に設定する。
In FIGS. 1 and 2, when the input signal vl input to the input terminal 1 is 0 volts, the output voltage v2 output from the gate 2 is a predetermined voltage V as in FIG.
(e.g. +5 volts). In this state, the capacitor 4 is charged via the resistor 3, setting the output voltage 3 to +5 volts. The comparator circuit 7 compares the output voltage V3 and the threshold voltage Vt, and when it identifies that the output voltage v3 is higher than the threshold voltage Vt, sets the output signal v4 outputted to the output terminal 6 to a logic value of 1.

かかる状態で、時点toに入力端子1に呼出信号が到着
すると、ゲート2から出力される出力電圧■2は第4図
におけると同様に時点to乃至tiStz乃至t3、t
4乃至t5、・・・において+5ボルトに設定され、ま
た時点tl乃至t2、t3乃至t4、・・・においてO
ポルトに設定される。
In this state, when a call signal arrives at the input terminal 1 at the time to, the output voltage 2 output from the gate 2 changes from the time to to tiStz to t3, t as in FIG.
4 to t5, . . . and set to +5 volts at times tl to t2, t3 to t4, .
Set in Porto.

その結果コンデンサ4は時点tl等においてゲート2を
介して直ちに放電され、また時点t2等において抵抗3
を経由して充電され、出力電圧v3は抵抗3の抵抗値お
よびコンデンサ4の静電容量値により定まる時定数に基
づき徐々に上昇する。
As a result, capacitor 4 is immediately discharged via gate 2 at time tl, etc., and resistor 3 at time t2, etc.
The output voltage v3 gradually increases based on a time constant determined by the resistance value of the resistor 3 and the capacitance value of the capacitor 4.

然し16ヘルツの半周期(即ち31.25ミリ秒)経過
した時点t3等において、出力電圧v2は再び0ボルト
に設定され、コンデンサ4は再び放電され、出力電圧v
3は再び0ポルトに設定される。
However, at a time point t3, etc., after a half period of 16 Hz (i.e. 31.25 milliseconds), the output voltage v2 is again set to 0 volts, the capacitor 4 is discharged again, and the output voltage v
3 is again set to 0 port.

今抵抗3の抵抗値を1.2キロオーム、コンデンサ4の
静電容量値を約17マイクロフアラドに設定すれば、時
点t3等においても出力電圧v3は閾値電圧Vt(=4
ボルト)を越えぬ為、比較回路7は時点t1以降継続的
に出力信号v4を論理値Oに設定する。
If we now set the resistance value of resistor 3 to 1.2 kilohms and the capacitance value of capacitor 4 to approximately 17 microfarads, the output voltage v3 will be the threshold voltage Vt (=4
volts), the comparator circuit 7 continuously sets the output signal v4 to the logical value O after time t1.

以上の説明から明らかな如く、本実施例によれば、積分
回路5の出力電圧v3は比較回路7により閾値電圧Vt
と比較される為、閾値電圧Vtを充分高電圧(前例では
+4ボルト)に設定してお(ことにより、積分回路5の
時定数が小さくとも16ヘルツの半周期の間、出力信号
v4を論理値0に維持することが可能となり、コンデン
サ4の静電容量値が小さく設定可能となる。
As is clear from the above description, according to this embodiment, the output voltage v3 of the integrating circuit 5 is determined by the comparator circuit 7 to be the threshold voltage Vt.
Therefore, the threshold voltage Vt is set to a sufficiently high voltage (+4 volts in the previous example). It becomes possible to maintain the value at 0, and the capacitance value of the capacitor 4 can be set small.

なお、第1図および第2図はあく迄本発明の一実施例に
過ぎず、例えば入力信号v1の周波数、電圧VOおよび
閾値電圧Vtの電圧値、抵抗3の抵抗値およびコンデン
サ4の静電容量値は図示されるものに限定されることは
無く、他に幾多の変形が考慮されるが、何れの場合にも
本発明の効果は変らない。また入力信号v1、出力電圧
v2およびv3、出力信号v4の波形は図示されるもの
に限定されることは無く、他に幾多の変形が考慮される
が、何れの場合にも本発明の効果は変らない。
Note that FIGS. 1 and 2 are only one embodiment of the present invention, and for example, the frequency of the input signal v1, the voltage values of the voltage VO and the threshold voltage Vt, the resistance value of the resistor 3, and the electrostatic capacitor 4 The capacitance value is not limited to what is shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case. Further, the waveforms of the input signal v1, output voltages v2 and v3, and output signal v4 are not limited to those shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not be affected in any case. It doesn't change.

〔発明の効果〕〔Effect of the invention〕

以上、本発明によれば、前記積分回路5を構成するコン
デンサの静電容量が削減され、当該平滑化回路の小型化
および経済化を向上することが出来る。
As described above, according to the present invention, the capacitance of the capacitor constituting the integrating circuit 5 is reduced, and the smoothing circuit can be made smaller and more economical.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例による平滑化回路を示す図、
第2図は第1図における各部の信号波形の一例を示す図
、第3図はこの種呼出信号検出回路における従来ある平
滑化回路の一例を示す図、第4図は第3図における各部
の信号波形の一例を示す図である。 図において、1は入力端子、2はゲート、3は抵抗、4
はコンデンサ、5は積分回路、6は出力端子、7は比較
回路、tQ乃至t5は時点、VOは電圧、vlは入力信
号、v2はゲートの出力電圧、v3は積分回路5の出力
電圧、v4は出力信号、vtは閾値電圧、を示す。 第1図 第2図
FIG. 1 is a diagram showing a smoothing circuit according to an embodiment of the present invention;
2 is a diagram showing an example of the signal waveform of each part in FIG. 1, FIG. 3 is a diagram showing an example of a conventional smoothing circuit in this kind of ringing signal detection circuit, and FIG. 4 is a diagram showing an example of the signal waveform of each part in FIG. 3. FIG. 3 is a diagram showing an example of a signal waveform. In the figure, 1 is an input terminal, 2 is a gate, 3 is a resistor, and 4
is a capacitor, 5 is an integrating circuit, 6 is an output terminal, 7 is a comparison circuit, tQ to t5 are time points, VO is a voltage, vl is an input signal, v2 is the output voltage of the gate, v3 is the output voltage of the integrating circuit 5, v4 is the output signal, and vt is the threshold voltage. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] ゲート回路の出力端子に抵抗およびコンデンサから構成
される積分回路を接続し、所定周波数の交流信号が前記
ゲート回路に入力された場合に前記積分回路の出力を所
定電圧範囲に維持する回路において、前記積分回路の出
力を比較回路の一方の入力端子に入力し、該比較回路の
他方の端子に所定の閾値電圧を入力し、前記ゲート回路
に前記交流信号が入力された場合に該比較回路の出力を
所定電位に維持することを特徴とする平滑化回路。
In the circuit that connects an integrating circuit composed of a resistor and a capacitor to an output terminal of a gate circuit, and maintains the output of the integrating circuit within a predetermined voltage range when an alternating current signal of a predetermined frequency is input to the gate circuit. The output of the integrating circuit is input to one input terminal of the comparator circuit, a predetermined threshold voltage is input to the other terminal of the comparator circuit, and the output of the comparator circuit is determined when the alternating current signal is input to the gate circuit. A smoothing circuit that maintains a predetermined potential.
JP22319584A 1984-10-24 1984-10-24 Smoothing circuit Pending JPS61100663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22319584A JPS61100663A (en) 1984-10-24 1984-10-24 Smoothing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22319584A JPS61100663A (en) 1984-10-24 1984-10-24 Smoothing circuit

Publications (1)

Publication Number Publication Date
JPS61100663A true JPS61100663A (en) 1986-05-19

Family

ID=16794285

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22319584A Pending JPS61100663A (en) 1984-10-24 1984-10-24 Smoothing circuit

Country Status (1)

Country Link
JP (1) JPS61100663A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52123669A (en) * 1976-04-09 1977-10-18 Mitsubishi Electric Corp Frequency abnormality detector
JPS5844644B2 (en) * 1975-01-16 1983-10-04 ライオン株式会社 Neri toothpaste

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5844644B2 (en) * 1975-01-16 1983-10-04 ライオン株式会社 Neri toothpaste
JPS52123669A (en) * 1976-04-09 1977-10-18 Mitsubishi Electric Corp Frequency abnormality detector

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