JPS54105583A - Peak detection circuit - Google Patents
Peak detection circuitInfo
- Publication number
- JPS54105583A JPS54105583A JP1259578A JP1259578A JPS54105583A JP S54105583 A JPS54105583 A JP S54105583A JP 1259578 A JP1259578 A JP 1259578A JP 1259578 A JP1259578 A JP 1259578A JP S54105583 A JPS54105583 A JP S54105583A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- term
- appears
- input signal
- peak value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To keep the peak value holding time sufficiently long and satisfy the follow-up of fluctuations of peak values at the same time, a detecting and holding the peak value alternately by using two peak detection circuits.
CONSTITUTION: When clock signals are supplied from clock signal wires 27 to 29 for driving SW, in term T1, SW 11, 12 are ON, SW 19, 20 are OFF, SW 23 is ON, and SW 24 is OFF. Accordingly, when an input signal is supplied from an input signal wire 30, capacitors C 17, 18 are charged at the time constant determined by R 31 and C17, 18, and the voltage at approximately maximum input signal level is maintained throughout the term T1. Since SW 23 is ON, a voltage nearly equal to the voltage of C 17 appears in an output wire 26. Next, in term T2, SW 11, 20, 23 are OFF, and SW 12, 19, 24 are ON, so that C17 is discharged, and the voltage of C18 appears in the output wire 26. Thus, since the two detection circuits are alternately cleared by force, while one detection circuit is cleared, the other one is detecting, so that the peak value appears in the output terminal 26.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1259578A JPS54105583A (en) | 1978-02-07 | 1978-02-07 | Peak detection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1259578A JPS54105583A (en) | 1978-02-07 | 1978-02-07 | Peak detection circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54105583A true JPS54105583A (en) | 1979-08-18 |
Family
ID=11809694
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1259578A Pending JPS54105583A (en) | 1978-02-07 | 1978-02-07 | Peak detection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54105583A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59109869A (en) * | 1982-12-16 | 1984-06-25 | Hioki Denki Kk | Signal recording device |
JPH0246570A (en) * | 1988-08-07 | 1990-02-15 | Nec Ic Microcomput Syst Ltd | Demodulating circuit |
-
1978
- 1978-02-07 JP JP1259578A patent/JPS54105583A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59109869A (en) * | 1982-12-16 | 1984-06-25 | Hioki Denki Kk | Signal recording device |
JPH0246570A (en) * | 1988-08-07 | 1990-02-15 | Nec Ic Microcomput Syst Ltd | Demodulating circuit |
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