JPS6098669A - Power transistor - Google Patents
Power transistorInfo
- Publication number
- JPS6098669A JPS6098669A JP20617883A JP20617883A JPS6098669A JP S6098669 A JPS6098669 A JP S6098669A JP 20617883 A JP20617883 A JP 20617883A JP 20617883 A JP20617883 A JP 20617883A JP S6098669 A JPS6098669 A JP S6098669A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- emitter
- region
- collector
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 18
- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000011796 hollow space material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明はパワートランジスタ、特にリング状エミッタ領
域乞有するパワートランジスタの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an improvement in a power transistor, particularly a power transistor having a ring-shaped emitter region.
（ロ）従来技術
パワーアンプ等を半導体集積回路に組み込む場合パワー
トランジスタがチップの大部分を占めるため、出来るだ
け小面積で高効率のノくワートランジスタの実現が望ま
れている。リング状エミッタ領域乞有するパワートラン
ジスタはベース電極に面するエミッタベース接合２最も
長く取れるので、面積的に効率が良（半導体集積回路に
組込む）（ワートランジスタとしては最適である。(b) Prior Art When a power amplifier or the like is incorporated into a semiconductor integrated circuit, the power transistor occupies most of the chip, so it is desired to realize a highly efficient power transistor with as small an area as possible. Since a power transistor having a ring-shaped emitter region can have the longest emitter-base junction 2 facing the base electrode, it is efficient in terms of area (incorporated into a semiconductor integrated circuit) (optimal as a power transistor).
従来用いていたリング状エミッタ領域を有するパワート
ランジスタを第１図および第２図ン参照し”（説明する
。このパワートランジスタはＰ型の半導体基板（１）上
にコレクタ領域となるＮ型のエピタキシャル層（２）乞
設け、エピタキシャル層（２）の底面にはコレクタ領域
の取出し抵抗２下げるためにＮ＋型の埋め込み層（３）
？：設け、エピタキシャル層（２）表面にはＮ＋型のコ
レクタコンタクト領域（４）？平行に帯状に設け、コレ
クタコンタクト領域（４）間のエピタキシャル層（２）
表面に帯状にＰ型のベース領域（５）を設け、ベース領
域（５）表面に連続したＮ＋型のリング状エミッタ領域
（６）ヲ設け、コレクタコンタクト領域（４）ベース領
域（５）およびエミッタ領域（６１に夫々オーミック接
触する点線で示すコレクタ電極（７）ベース電極（８）
およびエミッタ電極（９）設けて形成される。A conventionally used power transistor having a ring-shaped emitter region will be explained with reference to FIGS. Layer (2) is provided, and an N+ type buried layer (3) is provided on the bottom surface of the epitaxial layer (2) to lower the extraction resistance of the collector region.
? : An N+ type collector contact region (4) is provided on the surface of the epitaxial layer (2). The epitaxial layer (2) is provided in parallel strips between the collector contact regions (4).
A belt-shaped P-type base region (5) is provided on the surface, a continuous N+-type ring-shaped emitter region (6) is provided on the surface of the base region (5), a collector contact region (4), a base region (5), and an emitter region. The collector electrode (7) and the base electrode (8) shown by dotted lines make ohmic contact with the regions (61), respectively.
and an emitter electrode (9).
しかしながら上述した単層配線のリング状エミッタ領域
を有するパワートランジスタでは、エミッタ電極（９）
ンベース電極（８）とコレクタ電極（７）の間に配置し
なければならず、この部分のリング状エミッタ領域（６
）τ中広に形成する必要があった。この結果エミッタ電
極（９）乞設けない中挟のエミッタ領域（６）にはベー
スバイアスが良（かかりきわめて活性に働く反面、エミ
ッタ電極（９）ン設げた巾広のエミッタ領域（６）には
ベースバイアスが良くかからず不活性となる。このため
にエミッタ領域（６）でありながら良く働らかない部分
があり、面積的なロスを生ずる。またエミッタ領域（６
）の働き方のアンバランスから安全動作領域（Ａ、Ｓ、
０、）もストライプ型のパワートランジスタに比べて狭
くなり破壊に弱くなる。However, in the above-mentioned power transistor having a ring-shaped emitter region of single-layer wiring, the emitter electrode (9)
The ring-shaped emitter region (6) must be located between the base electrode (8) and the collector electrode (7).
) It was necessary to form the τ medium wide. As a result, the base bias is good in the middle emitter region (6) where the emitter electrode (9) is not provided, and works extremely active, whereas the wide emitter region (6) where the emitter electrode (9) is provided is The base bias is not applied well and it becomes inactive.For this reason, there is a part that does not work well even though it is an emitter region (6), resulting in area loss.Also, the emitter region (6)
) due to an imbalance in the way they work, the safe operating area (A, S,
0, ) is also narrower than a stripe-type power transistor, making it more susceptible to destruction.
（ハ）発明の目的
本発明は斯点に鑑みてなされ、従来の欠点を大巾に改善
したリング状エミッタ領域を有するパワートランジスタ
乞実現することを目的とする。(c) Purpose of the Invention The present invention has been made in view of the above points, and an object of the present invention is to realize a power transistor having a ring-shaped emitter region, which greatly improves the conventional drawbacks.
に）発明の構成
本発明に依れば第３図乃至第５図に示す如く、−導電型
の半導体基板０１）と、基板ａυ上に設けた逆導電型で
コレクタ領域となるエピタキシャル層ａｚと、エピタキ
シャル層（１２１表面に設けた逆導電型のコレクタコン
タクト領域（１４１と一４電型のベース領域Ｑ（ｉ）お
よび逆導電型のリング状エミッタ領域α力と、エピタキ
シャル層（１２１表面ゼ被覆する第１の絶縁膜０８）と
、コレクタコンタクト領域（１４）にオーミック接触す
る第１コレクタ電極θ９と、ゴミツタ領域（Ｉ７）にオ
ーミック接触する第１エミツタ電極（２（力と、エミッ
タ領域０ηに囲まれたベース領域００にオーミック接触
し第１の絶縁膜（ｉ印上ゲ延在されるベース電極（２Ｉ
）と、第１コレクタ電極０湧第１エミツタ電極弦））お
よびベース電極＆ｌｌを被接する第２の絶縁膜（２ｚと
、２ｆ、１コレクタ゛？ｌｌ、極（１９および第１エミ
ツタ′目を極（２０＋？夫々］！］（結して第２の絶紛
膜（２？１上に延在さｎる第２コレクタ′市極Ｃ２３１
および第２エミツタ電極Ｃ４）とより構成されている。B) Structure of the Invention According to the present invention, as shown in FIGS. 3 to 5, a - conductivity type semiconductor substrate 01), an opposite conductivity type epitaxial layer az provided on the substrate aυ and serving as a collector region. , a collector contact region (141) of opposite conductivity type provided on the surface of epitaxial layer (121), a base region Q(i) of 14 conductivity type and a ring-shaped emitter region α of opposite conductivity type, and a collector contact region (141) of opposite conductivity type provided on the surface of epitaxial layer (121 the first insulating film 08) that contacts the collector contact region (14), the first collector electrode θ9 that makes ohmic contact with the collector contact region (14), and the first emitter electrode (2) that makes ohmic contact with the dust ivy region (I7) and the emitter region 0η. A base electrode (2I) is in ohmic contact with the surrounded base region 00 and extends over the first insulation film (i mark
) and the second insulating film (2z, 2f, 1 collector ゛?ll, pole (19 and first emitter electrode string)) which is in contact with the first collector electrode 0 and the first emitter electrode (20+? respectively]!) (In conclusion, the second insulating film (2?1) extends over the
and a second emitter electrode C4).
（７１１実施例
本発明に依ルば、Ｐ型の半導体基板０１）と、基板圓上
に設けたコレクタ領域として働くエピタキシャル層（１
２１と、エピタキシャル層Ｏ９底面に設けたＮ＋型の埋
め込み層θ３）と、エピタキシャル層（１２）表面に’
Ｍｌに平行に設けられたＮ＋型のコレクタコンタクト領
域（１４）と、コレクタコンタクト領域（１４）と埋め
込み層（１３１Ｙ連結するＮ＋型のコレクタ導出領域０
５）と、コレクタコンタクト領域（１４）間のエビタキ
シャ／Ｉ／）Ｎα２表面に帯状に且つコレクタコンタク
ト領域α４沈平行に設けろｎだＰ型のベース領域Ｑ６）
と、ペース領域１０表面に設けた等間隔で中空部公有す
る連続したリング状のエミッタ領域（１７）と、エピタ
キシャル層０２表面を被覆するシリコン酸化膜より成る
第１の絶縁膜α＆と、コレクタコンタクト領域０４）お
よびエミッタ領域ａηにオーミック接触する第１コレク
タ電極Ｈおよび第１エミツタ電極（２）めと、リング状
のエミッタ領域σηに囲まれたベース領域（１６１にオ
ーミック接触し第１の絶縁膜Ｑ８１上に第１コレクタ電
極αｊ８よび第１エミツタ電極囚と短絡しない様に延在
さｎるベース電極ｅυと、−１４目の第１コレクタ電極
（ＩＩＩ第１エミッタ電極（２０）およびペース電極シ
υ乞被覆して層間絶縁ぞ行うポリイミド等より成る第２
の絶縁膜（２のと、複数の第１コレクタ電極Ｈおよび第
１エミツタ電極（２０）を連結し第２の絶縁膜Ｃ２２）
上に延在される第２コレクタ電極（２３）および第２エ
ミツタ電極Ｃカとを具備している。(Embodiment 711 According to the present invention, a P-type semiconductor substrate 01) and an epitaxial layer (1) serving as a collector region provided on the substrate circle
21, an N+ type buried layer θ3) provided on the bottom surface of the epitaxial layer O9, and a '
An N+ type collector contact region (14) provided parallel to Ml, and an N+ type collector lead-out region 0 connected to the collector contact region (14) and a buried layer (131Y).
5) and the collector contact region (14), a P-type base region Q6) should be provided in a belt shape on the surface of Nα2 and parallel to the collector contact region α4.
, a continuous ring-shaped emitter region (17) provided on the surface of the space region 10 and sharing a hollow space at equal intervals, a first insulating film α& made of a silicon oxide film covering the surface of the epitaxial layer 02, and a collector contact. The first collector electrode H and the first emitter electrode (2) are in ohmic contact with the region 04) and the emitter region aη, and the base region (161 is in ohmic contact with the first insulating film) surrounded by the ring-shaped emitter region ση. A base electrode eυ extends on Q81 so as not to short-circuit with the first collector electrode αj8 and the first emitter electrode, and the -14th first collector electrode (III first emitter electrode (20) and pace electrode series). The second layer is made of polyimide, etc., which is coated to provide interlayer insulation.
(a second insulating film C22 connecting the plurality of first collector electrodes H and first emitter electrodes (20))
It has a second collector electrode (23) and a second emitter electrode (C) extending upwardly.
本発明の特徴の１つは電極ン２Ｒ４構造としだ点にある
。即ち第１コレクタ電極（１９＋第１エミツタ電極いＩ
ＩＮよびベース電極ＣＤは第１層目の電極（第３図で点
線で示す）であり、第２コレクタ電極（ハ）第２エミツ
タ電極（２旬は第２層目の電極（第３図で一点破線で示
す）である。第１コレクタ電極（１つは第３図から明ら
かな様にコレクタコンタクト領域Ｑ４）上に一定間隔で
点在しており、第１エミツタ電極（２０）はリング状の
エミッタ領域０７）のベース領域０６）ヲ露出した部分
の間に一定間隔で点在している。また第１コレクタ電極
α９と第１エミツタ電極翰は隣接させて同一間隔で設け
ている。リング状のエミッタ領域ＯＤより中央に露出し
たベース領域Ｑ６）に夫々ベース電極Ｃ’ｌ） ’！’
オーミック接触し且つ第１コレクタ電極αｌおよび第１
エミツタ電極（２υ間のすきま？一方向にストライプ状
に第１の絶縁膜０ね上に延在させてすべてのベース領域
α６）乞連結を行う。第２コレクタ電極（ハ）および第
２エミツタ電極０４）は第２の絶縁膜（２つ上乞一方向
にストライプ状に延在し、点在する第１コレクタを極（
ｊおよび第１エミツタ電極（２υの連結を行う。これＶ
こよりベース電極Ｃυと第２コレクタ電極（ハ）および
第２エミツタ電極（２４）は第５図の如く、第２の絶縁
膜Ｃ！功により電気的に絶縁されている。またベース電
極（２Ｊ）の延在方向と第２コレクタ電極（ハ）および
第２エミツタ電極（２）の延在方向は直交あるいはそれ
に近い状態であるのがパターン設計上望ましい。One of the features of the present invention is that the electrode has a 2R4 structure. That is, the first collector electrode (19+first emitter electrode I
IN and base electrode CD are the electrodes of the first layer (indicated by dotted lines in Figure 3), the second collector electrode (C) and the second emitter electrode (2 are the electrodes of the second layer (indicated by dotted lines in Figure 3). The first emitter electrodes (20) are dotted at regular intervals on the first collector electrode (one is the collector contact region Q4 as is clear from FIG. 3), and the first emitter electrode (20) is ring-shaped. The emitter regions 07) and the base regions 06) are scattered at regular intervals between the exposed portions of the base regions 06). Further, the first collector electrode α9 and the first emitter electrode wire are provided adjacent to each other at the same interval. Each base electrode C'l)'! '
are in ohmic contact with the first collector electrode αl and the first
The emitter electrodes (with a gap of 2υ, extending in a stripe pattern in one direction over the first insulating film 0 and all the base regions α6) are connected. The second collector electrode (c) and the second emitter electrode 04) extend in a stripe shape in one direction, and the scattered first collector electrodes (
j and the first emitter electrode (2υ is connected. This is V
From this, the base electrode Cυ, the second collector electrode (c), and the second emitter electrode (24) are connected to the second insulating film C!, as shown in FIG. It is electrically insulated due to its strength. Further, in terms of pattern design, it is desirable that the extending direction of the base electrode (2J) and the extending directions of the second collector electrode (c) and the second emitter electrode (2) be orthogonal to each other or nearly so.
本発明に依れば、ベース電極（２１Ｊと第２コレクタ電
極（２３）および第２エミツタ電極（２４） ｗ延在方
向を交叉できるので、リング状のエミッタ領域０７）ｖ
均等の巾に形成できるのである。この結果リング状のエ
ミッタ領域０７）は全部が均一に且つ効率良く働き、総
合的には従来より以上に効率を高め且つ働き方のアンバ
ランスを除去できるのである。According to the present invention, since the extending directions of the base electrode (21J, the second collector electrode (23), and the second emitter electrode (24) w can intersect with each other, the ring-shaped emitter region 07) v
It can be formed to have an even width. As a result, the entire ring-shaped emitter region 07) works uniformly and efficiently, making it possible to improve overall efficiency more than ever before and eliminate imbalance in the way it works.
更に本発明では第１エミツタ電極（社）との接続を行う
第２の絶縁膜（２ｚに設けるスルーホールの大ぎさ乞調
節することにより、第１エミツタ電極（２０ｊと第２エ
ミツタ電極（２４）間に直列に抵抗を形成できる。Furthermore, in the present invention, by adjusting the size of the through hole provided in the second insulating film (2z) that connects with the first emitter electrode (20j), the first emitter electrode (20j) and the second emitter electrode (24) A resistor can be formed in series between them.
そしてこの抵抗はエミッタ抵抗として働さ、パワートラ
ンジスタの安全動作領域ゼムげるバラスト抵抗の役割を
果たせる。またスルーホールの太きさによりエミッタ抵
抗値ン任意に選択できる。This resistor acts as an emitter resistor, and can play the role of a ballast resistor that extends the safe operating range of the power transistor. Furthermore, the emitter resistance value can be arbitrarily selected depending on the thickness of the through hole.
（へ）発明の効果
本発明に依れば２層配線構造の採用によりリング状のエ
ミッタ領域ａ７１の巾を均等に形成でき、パワートラン
ジスタの効率を従来より向上できた。(F) Effects of the Invention According to the present invention, by employing a two-layer wiring structure, the width of the ring-shaped emitter region a71 can be made uniform, and the efficiency of the power transistor can be improved compared to the conventional one.
これにより従来より少ない面精でパワートランジスタ乞
形成でさ、集積回路の集積度乞向上できる。As a result, the degree of integration of the integrated circuit can be improved by forming power transistors with less effort than in the past.
ま７Ｌ パワートランジスタのリング状のエミッタ領域
の働き方のアンバランスを除去でき、パワートランジス
タの安全動作領域乞拡大できる。更に第２の絶縁膜＠の
スルーホールの形状の選択によりバラスト抵抗７組み込
むことができ、パワートランジスタの安全動作領域乞よ
り拡大できる。7L It is possible to eliminate the imbalance in the way the ring-shaped emitter region of the power transistor works, and it is possible to expand the safe operating range of the power transistor. Furthermore, by selecting the shape of the through hole in the second insulating film, the ballast resistor 7 can be incorporated, and the safe operation range of the power transistor can be expanded.
第１図は従来のリング状エミッタ領域を有するパワート
ランジスタの上面図、第２図は第１図のＩＩ −ＩＩ線
断面図、第３図は本発明のパワートランジスタの上面図
、第４図は第３図のＩＶ−ＩＶ ｉ断面図、第５図は第
３図の■−ｖ線断面図である。
主な図番の説明
α１）は半導体基板、（１２１はエピタキシャル層、０
４）はコレクタコンタクト領域、ｕ叫まベース領域、ａ
力はリング状のエミッタ領域、α＆は第１の絶縁膜、θ
ａは第１コレクタ電極、 （２０）は第１エミツタ電極
、（２］）ハヘース電極、（２３は第２の絶縁膜、（ハ
）は第２コレクタ電極、（２（イ）は第２エミツタ電極
である。FIG. 1 is a top view of a conventional power transistor having a ring-shaped emitter region, FIG. 2 is a sectional view taken along the line II--II of FIG. 1, FIG. 3 is a top view of the power transistor of the present invention, and FIG. 3 is a cross-sectional view taken along line IV-IV i, and FIG. 5 is a cross-sectional view taken along line ■-v in FIG. Explanation of main figure numbers α1) is the semiconductor substrate, (121 is the epitaxial layer, 0
4) Collector contact area, base area, a
force is the ring-shaped emitter region, α & is the first insulating film, θ
a is the first collector electrode, (20) is the first emitter electrode, (2) is the heath electrode, (23 is the second insulating film, (c) is the second collector electrode, (2 (a) is the second emitter electrode) It is an electrode.
Claims (1)
電型でコレクタ領域となるエピタキシャル層と、該エピ
タキシャル層表面に設けた逆導電型のコレクタコンタク
ト領域と一導電型のベース領域および逆導電型のリング
状エミッタ領域と、前記エピタキシャル層表面な被覆す
る第１の絶縁膜と、前記コレクタコンタクト領域にオー
ミック接触する第１コレクタ電極と、前記エミッタ領域
にオーミック接触する第１エミツタ電極と、前記エミッ
タ領域に囲まれた前記ベース領域にオーミック接触し前
記第１の絶縁膜上を延在されるベース電極と、前記第１
コレクタ電極第１エミツタ電極およびベース電極を被覆
する第２の絶縁膜と、前記第１コレクタを極第１エミッ
タ′ｒ■を極な夫々連結し前記第２の絶縁膜上に延在さ
れる第２コレクタ電極および第２エミツタ電極とを具備
すること乞特徴とするパワートランジスタ。 （２、特許請求の範囲第１項に於いて、前記ベース電極
の延在方向と前記第２コレクタ電極および第２エミツタ
電極の延在方向を父叉すること欠特徴とするパワートラ
ンジスタ。[Claims] (11- A semiconductor substrate of a conductivity type, an epitaxial layer of an opposite conductivity type provided on the substrate and serving as a collector region, and a collector contact region of an opposite conductivity type provided on a surface of the epitaxial layer. a base region of conductivity type, a ring-shaped emitter region of opposite conductivity type, a first insulating film covering the surface of the epitaxial layer, a first collector electrode in ohmic contact with the collector contact region, and an ohmic contact with the emitter region. a first emitter electrode that is in ohmic contact with the base region surrounded by the emitter region and extends over the first insulating film;
a second insulating film covering the collector electrode and the first emitter electrode and the base electrode; A power transistor comprising two collector electrodes and a second emitter electrode. (2. The power transistor according to claim 1, characterized in that the extending direction of the base electrode and the extending direction of the second collector electrode and the second emitter electrode are opposite to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20617883A JPS6098669A (en) | 1983-11-02 | 1983-11-02 | Power transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20617883A JPS6098669A (en) | 1983-11-02 | 1983-11-02 | Power transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6098669A true JPS6098669A (en) | 1985-06-01 |
| JPH0348653B2 JPH0348653B2 (en) | 1991-07-25 |
Family
ID=16519101
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20617883A Granted JPS6098669A (en) | 1983-11-02 | 1983-11-02 | Power transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6098669A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1082422C (en) * | 1995-12-07 | 2002-04-10 | 松下电器产业株式会社 | Process for manufacturing resin-encapsulated electronic product |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5165585A (en) * | 1974-12-04 | 1976-06-07 | Hitachi Ltd | |
| JPS57197863A (en) * | 1982-04-12 | 1982-12-04 | Hitachi Ltd | Semiconductor integrated circuit device |
-
1983
- 1983-11-02 JP JP20617883A patent/JPS6098669A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5165585A (en) * | 1974-12-04 | 1976-06-07 | Hitachi Ltd | |
| JPS57197863A (en) * | 1982-04-12 | 1982-12-04 | Hitachi Ltd | Semiconductor integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1082422C (en) * | 1995-12-07 | 2002-04-10 | 松下电器产业株式会社 | Process for manufacturing resin-encapsulated electronic product |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0348653B2 (en) | 1991-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4012764A (en) | Semiconductor integrated circuit device | |
| US4081697A (en) | Semiconductor memory device | |
| KR0155991B1 (en) | Mos-pilot structure for an insulated gate transistor | |
| JPH0156531B2 (en) | ||
| JPH0346981B2 (en) | ||
| JPS6098669A (en) | Power transistor | |
| JP3515298B2 (en) | Semiconductor device | |
| JP2504498B2 (en) | Semiconductor device | |
| JP2903452B2 (en) | Field effect transistor | |
| JPS5938056Y2 (en) | semiconductor switchgear | |
| JP2613939B2 (en) | Semiconductor device | |
| JP2825039B2 (en) | Semiconductor storage device | |
| JPS601843A (en) | Semiconductor integrated circuit | |
| JPS5925389B2 (en) | semiconductor equipment | |
| JPS59215771A (en) | Comb-shaped emitter transistor | |
| JPH0637098A (en) | Semiconductor device and manufacture thereof | |
| JP2669384B2 (en) | Semiconductor device | |
| JPH0333067Y2 (en) | ||
| JP2982435B2 (en) | Resistor | |
| JPH07107904B2 (en) | Semiconductor device | |
| JPS59127865A (en) | Semiconductor device | |
| JPH0148662B2 (en) | ||
| JPS63160269A (en) | Semiconductor storage device | |
| JPS6352473B2 (en) | ||
| JPH0258869A (en) | Memory device |