JPS6097653A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6097653A
JPS6097653A JP20520583A JP20520583A JPS6097653A JP S6097653 A JPS6097653 A JP S6097653A JP 20520583 A JP20520583 A JP 20520583A JP 20520583 A JP20520583 A JP 20520583A JP S6097653 A JPS6097653 A JP S6097653A
Authority
JP
Japan
Prior art keywords
semiconductor device
leads
main body
lead
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20520583A
Other languages
Japanese (ja)
Inventor
Hirofumi Nakajima
中島 宏文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP20520583A priority Critical patent/JPS6097653A/en
Publication of JPS6097653A publication Critical patent/JPS6097653A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • H01L23/49555Cross section geometry characterised by bent parts the bent parts being the outer leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To produce multiple pin resin sealed semiconductor device subject to easy installation with less lead bending by a method wherein the external leads bent inward along the resin main body and the other external leads bent outward and stepwise are alternately arranged. CONSTITUTION:External lead 3a bent outward and stepwise outside a resin main body 1 and the other external leads 3b bent inward along the resin main body 1 are alternately arranged at the side of the resin main body 1. The bottom points of the leads 3b and 3a are made flush to make installation of wiring pads 12, 13 for contact on a print wiring substrate 11 easier. The outside wiring pads 12 and the inside wiring pads 13 are also alternately arranged so that the pad width size may be designed wider requiring less precision of the wiring pattern as well as less precision of locating semiconductor device on the substrate 11 in case of installation.

Description

【発明の詳細な説明】 イ、産業上の利用分野 本発明は、樹脂封止型半導体装置に関し、特に外部リー
ド端子の多い多ピン型半導体装置に関するものでるる。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a resin-sealed semiconductor device, and particularly to a multi-pin semiconductor device having many external lead terminals.

口、従来技術 最近、時計、電子卓上計算機等の電子機器が小型化され
、液晶等の表示素子を直接半導体素子で駆動するように
なるにつれて、半導体素子からの外部リード端子の多い
多ピン型半導体装置がめられるようになってきた。一方
、上記のような電子機器に使用する半導体装置は、封止
用樹脂の信頼性の向上等によシ、従来のごとく、高価な
セラミックケースは使わずに、安価な樹脂封止を行うの
が一般化している。
BACKGROUND ART Recently, as electronic devices such as watches and electronic desktop calculators have become smaller and display elements such as liquid crystals have come to be directly driven by semiconductor elements, multi-pin type semiconductors with many external lead terminals from semiconductor elements have become available. I'm starting to get used to the equipment. On the other hand, in order to improve the reliability of the encapsulating resin, semiconductor devices used in electronic devices such as those mentioned above are being encapsulated with inexpensive resin instead of using the conventional expensive ceramic case. is becoming common.

多ピン型半導体装置として、従来からリードが樹脂本体
からほぼ水平方向に出ているフラット型半導体装置や、
シュリンクDIP半導体装置がある。
Multi-pin type semiconductor devices have traditionally included flat type semiconductor devices in which the leads protrude from the resin body in an almost horizontal direction,
There is a shrink DIP semiconductor device.

従来の7ラツト型半導体装置は、第1図の斜視図に示す
如く、樹脂本体1の4箇所の側部から出た外部リード端
子2が階段状に曲けられている。
In the conventional seven-rat type semiconductor device, as shown in the perspective view of FIG. 1, external lead terminals 2 extending from four sides of a resin body 1 are bent in a step-like manner.

このような、従来の7ラツト型半導体装置では、外部リ
ード端子が100ピン迄は可能であるが、外部リード端
子の幅が狭くなる為に、リード曲シが生じやすく、隣接
するリードが互いに接触したシ、プリント基板に実装す
る際の基板と半導体装置の位置合わせ精度が高く要求さ
れ、実装しにくい等の問題がめった。一方、処在セラミ
ックパッケージでは200ピン程度の外部リード端子を
有する製品が生産されているが、コストダウンの為に、
樹脂封止型半導体装置による200ピン程度の実現も検
討されている。
In such a conventional 7-rat type semiconductor device, it is possible to have up to 100 external lead terminals, but because the width of the external lead terminals is narrow, lead bending is likely to occur, and adjacent leads may come into contact with each other. However, when mounting the semiconductor device on a printed circuit board, a high degree of alignment accuracy was required between the board and the semiconductor device, which often led to problems such as difficulty in mounting. On the other hand, products with external lead terminals of about 200 pins are produced in ceramic packages, but in order to reduce costs,
The realization of about 200 pins using a resin-sealed semiconductor device is also being considered.

ハ0発明の目的 本発明は上記の状況に鑑みてなされたものであシ、リー
ド曲シが生じに<<、実装しやすい100ピン以上の樹
脂封止型半導体装置を提供することを目的としている。
Purpose of the Invention The present invention has been made in view of the above-mentioned situation, and an object of the present invention is to provide a resin-sealed semiconductor device with 100 pins or more that is easy to mount and is easy to mount. There is.

二0発明の構成 本発明の樹脂封止型半導体装置は、樹脂本体から出てい
る外部リードが樹脂本体に沿って内側にげられたり′−
ドが交互に配置されておシ、該リードの最下点が全て同
一平面上にある構成を有する。
20 Structure of the Invention In the resin-sealed semiconductor device of the present invention, the external leads protruding from the resin body are bent inward along the resin body.
The leads are arranged alternately and the lowest points of the leads are all on the same plane.

ホ、実施例 以下本発明を実施例によシ説明する。E, Example The present invention will be explained below using examples.

第2図(a)は本発明の第1の実施例の斜視図でめシ、
同図(b)は同図(a)の半導体装置をプリント回路基
板に実装した状態のA−A断面図である。これらの図に
おいて、樹脂本体1の4箇所の側部から出た外部リード
は、樹脂本体1の外側に階段状に曲げられたリード3a
と、樹脂本体の側面に沿って内側に曲げられたリード3
bが交互に配置されている。
FIG. 2(a) is a perspective view of the first embodiment of the present invention.
FIG. 5B is a sectional view taken along line A-A of the semiconductor device shown in FIG. 1A mounted on a printed circuit board. In these figures, the external leads coming out of the four sides of the resin body 1 are the leads 3a bent in a step-like manner to the outside of the resin body 1.
and the lead 3 bent inward along the side of the resin body.
b are arranged alternately.

このような本発明の半導体装置では、外部リード3a同
志のピッチ間隔は、第1図に示した従来の半導体装置の
外部リード2同志のピッチ間隔の2倍なので、リード同
志がショートすることがない。また、プリント回路基板
11に実装した場合、樹脂本体1に沿って内側に曲げら
れたり一ド3bと外方向に曲げられたリード3aの最下
点は同一平面であるので、プリント回路基板11上のコ
ンタクト用配線パッド12.13に容易に実装できるO 第3図は従来の7ラツト半導体装置用プリント基板21
のコンタクト用配線パッド22のパターンである。コン
タクト用配線パッド22のパッド間ピッチは、第1図に
示すような、実装するフラット半導体装置のリード2の
ピッチと等しくしなければならないので、外部リード端
子数が増加するのに従ってピッチが小さくなシ、コンタ
クト用配線パッド22のパッド幅が狭く、プリント基板
製造時の高いエツチング精度が要求される。また、フリ
ント基板21のコンタクト用配線パッド22の幅も狭い
ので、実装時にはプリント基板に対する半導体装置の位
置合わせ精度が非常に高く要求される。
In such a semiconductor device of the present invention, the pitch between the external leads 3a is twice the pitch between the external leads 2 of the conventional semiconductor device shown in FIG. 1, so that short-circuits between the leads do not occur. . Furthermore, when mounted on the printed circuit board 11, the lowest points of the leads 3a bent inwardly along the resin body 1 and outwardly bent with the lead 3b are on the same plane. Figure 3 shows a conventional printed circuit board 21 for a 7-rat semiconductor device.
This is a pattern of contact wiring pads 22. The pitch between the contact wiring pads 22 must be equal to the pitch of the leads 2 of the flat semiconductor device to be mounted, as shown in FIG. 1, so as the number of external lead terminals increases, the pitch becomes smaller. Second, the pad width of the contact wiring pad 22 is narrow, and high etching accuracy is required during the manufacture of the printed circuit board. Further, since the width of the contact wiring pad 22 of the flint board 21 is narrow, very high precision is required for positioning the semiconductor device with respect to the printed circuit board during mounting.

一方、第4図は本発明による半導体装置用プリント基板
11のコンタクト用配線パッドのパターン12.13で
ある。コンタクト用配線パッドは外周の配線パッド12
と内周の配線パッド13が交互に配置されているので、
配線パッド幅寸法が大きく設計できる。従って、配線パ
ターンの精度も高度のものは要求されず、かつ実装時に
はプリント基板に対する半導体装置の位置合わせ精度も
従来に比較して低くて済む。このように、プリント基板
の設計や実装に利点を有する本発明は、更に多ピン型半
導体装置の製造方法においても利点を有する。
On the other hand, FIG. 4 shows patterns 12 and 13 of contact wiring pads of the printed circuit board 11 for a semiconductor device according to the present invention. The contact wiring pad is the outer wiring pad 12.
Since the wiring pads 13 on the inner periphery are arranged alternately,
Wiring pad width dimension can be designed larger. Therefore, high accuracy of the wiring pattern is not required, and the positioning accuracy of the semiconductor device with respect to the printed circuit board during mounting can also be lower than in the past. As described above, the present invention, which has advantages in designing and mounting printed circuit boards, also has advantages in manufacturing methods for multi-pin semiconductor devices.

第5図は本発明の第2の実施例について説明するための
図で、同図(a)は従来のフラット半導体装置の切断曲
げ前の平面図でロシ、樹脂本体1から外部リード2が出
ておシ、タイツ(−4によってリードが保持されている
。従来のフラット半導体装置の製造方法によれば、この
タイツ(−4を切断用ポンチ31で切抜いて分離した後
にリード折シ曲げを行なう。その為に隣接する外部リー
ド2の間には切断用ポンチ31の入る十分な間隔が必要
でめった。第5図(b)は本発明による第2の実施例で
アシ、樹脂部本体1から幅の広い外部リード5aと幅の
狭い外部リード5bが出ている。外部リード5aは樹脂
本体1の外方向に階段状に曲げる為に、リード幅が広く
設計してアシ、リード変形が生じにくい効果を有する。
FIG. 5 is a diagram for explaining the second embodiment of the present invention. FIG. The leads are held by the tights (-4).According to the conventional manufacturing method for flat semiconductor devices, the leads are bent after the tights (-4) are cut out and separated with a cutting punch 31. For this reason, it is necessary to provide sufficient space between the adjacent external leads 2 to allow the cutting punch 31 to fit therein. FIG. A wide external lead 5a and a narrow external lead 5b are protruding.Since the external lead 5a is bent in a stepped manner toward the outside of the resin body 1, the lead width is designed to be wide to prevent reeds and lead deformation. have an effect.

また、外部リード5bは樹脂本体1に沿って内側に曲げ
られるので、リード変形が生ずる可能性はなく、ピン数
を増す目的でリード幅を狭くしてらる。外部リード5a
Furthermore, since the external leads 5b are bent inward along the resin body 1, there is no possibility of lead deformation, and the lead width is narrowed in order to increase the number of pins. External lead 5a
.

5bを保持するタイバー6は従来のように切断用ポンチ
で切シ抜くのではなく、切断兼臼げ金型32によって外
部リード5bを切シ曲げて外部リード5aと外部リード
5bを分離する。この方法によれば、リード間隔は狭い
程タイバー6はリード成形後にタイバー残ル部分が目立
たなくなるので、従来の半導体装置のようにリード間隔
を一十分空けることは不必要である。また、従来のリー
ド変形に対しても外部リードのリード幅を広くできる為
に、半導体装置への衝撃に対する強度が強くなシ、リー
ド変形を減少させることができる。
The tie bar 6 holding the external lead 5b is not cut out with a cutting punch as in the conventional case, but is cut and bent using a cutting and crushing die 32 to separate the external lead 5a and the external lead 5b. According to this method, the narrower the lead spacing, the less noticeable the remaining portion of the tie bar 6 after lead molding becomes, so it is unnecessary to leave the lead spacing ten minutes apart as in conventional semiconductor devices. In addition, since the lead width of the external lead can be increased against conventional lead deformation, the semiconductor device has strong strength against impact, and lead deformation can be reduced.

二1発明の効果 このように、本発明によれば、10oピン以上の多ピン
化を可能にし、プリント基板への実装を容易にする。し
かも、本発明の半導体装置はセラミック半導体装置に比
較して非常に安価に製造できるという長所がるる。
21 Effects of the Invention As described above, according to the present invention, it is possible to increase the number of pins to 100 pins or more, and to facilitate mounting on a printed circuit board. Moreover, the semiconductor device of the present invention has the advantage that it can be manufactured at a much lower cost than ceramic semiconductor devices.

なお、実施例には樹脂本体から外部リード端子が4方向
に出ているフラット半導体装置について示したが、外部
リード端子が2方向に出ているミニフラット半導体装置
にも適用でき、何ら4方向の半導体装置に限定するもの
ではない。
Although the example shows a flat semiconductor device in which the external lead terminals protrude from the resin body in four directions, it can also be applied to a mini-flat semiconductor device in which the external lead terminals protrude in two directions. The invention is not limited to semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のフラット半導体装置の斜視図、第2図(
a)は本発明によるフラット半導体装置の第1の実施例
の斜視図、同図(b)同図(a)の半導体装置をプリン
ト回路基板に実装した状態のA−A断面図、第3図は従
来のフラット半導体装置を実装するプリント基板のコン
タクト用配線パッドパターンの平面図、第4図は本発明
によるフラット半導体装置を実装するプリント基板のコ
ンタクト用配線パッドパターンの平面図、第5図(a)
は切断曲げ前の状態の従来のフラット半導体装置の部分
平面図、第5図(b)は切断曲げ前の状態の本発明によ
る第2の実施例のフラット半導体装置の部分平面図でる
る。 1・・・・・・樹脂本体、2・・・・・・従来の外部リ
ード、3a、5a・・・・・・外方に引出した外部リー
ド、3b。 5b・・・・・・内側に折曲げた外部リード、4.6・
・・・・・タイバー、11.21・・・・・・プリント
回路基板、12.13.22・・・・・・コンタクト用
配線パッド、31・・・・・・タイバー打抜き用ポンチ
、32・・団・タイバー切断兼リード曲げ金型。 第 1区 (幻 Uり 第Z図 又 h 裁 2
Figure 1 is a perspective view of a conventional flat semiconductor device, and Figure 2 (
(a) is a perspective view of a first embodiment of a flat semiconductor device according to the present invention; FIG. 3 (b) is a sectional view taken along line A-A of the semiconductor device shown in FIG. 4 is a plan view of a contact wiring pad pattern of a printed circuit board on which a conventional flat semiconductor device is mounted, FIG. 4 is a plan view of a contact wiring pad pattern of a printed circuit board on which a flat semiconductor device according to the present invention is mounted, and FIG. a)
5(b) is a partial plan view of a conventional flat semiconductor device in a state before cutting and bending, and FIG. 5(b) is a partial plan view of a flat semiconductor device according to a second embodiment of the present invention in a state before cutting and bending. DESCRIPTION OF SYMBOLS 1...Resin main body, 2...Conventional external lead, 3a, 5a...External lead pulled out outward, 3b. 5b... External lead bent inward, 4.6.
... Tie bar, 11.21 ... Printed circuit board, 12.13.22 ... Wiring pad for contact, 31 ... Punch for punching tie bar, 32. - Group/tie bar cutting and lead bending mold. Ward 1

Claims (1)

【特許請求の範囲】[Claims] たり一ドと樹脂本体の外方向に階段状に曲げたリードと
から構成され、かつ、これらのリードは交互に配置され
ていることを特徴とする半導体装置。
What is claimed is: 1. A semiconductor device comprising a single lead and a lead bent stepwise outward from a resin body, and wherein these leads are arranged alternately.
JP20520583A 1983-11-01 1983-11-01 Semiconductor device Pending JPS6097653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20520583A JPS6097653A (en) 1983-11-01 1983-11-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20520583A JPS6097653A (en) 1983-11-01 1983-11-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6097653A true JPS6097653A (en) 1985-05-31

Family

ID=16503136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20520583A Pending JPS6097653A (en) 1983-11-01 1983-11-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6097653A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4794446A (en) * 1985-10-25 1988-12-27 Mitsubishi Denki Kabushiki Kaisha Electrode device and a method for making the same
JPH0245650U (en) * 1988-09-24 1990-03-29
US9084348B2 (en) 2009-12-07 2015-07-14 Murata Manufacturing Co., Ltd. High-frequency module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4794446A (en) * 1985-10-25 1988-12-27 Mitsubishi Denki Kabushiki Kaisha Electrode device and a method for making the same
JPH0245650U (en) * 1988-09-24 1990-03-29
US9084348B2 (en) 2009-12-07 2015-07-14 Murata Manufacturing Co., Ltd. High-frequency module

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