JPS6096012A - Variable gain amplifier - Google Patents
Variable gain amplifierInfo
- Publication number
- JPS6096012A JPS6096012A JP20408083A JP20408083A JPS6096012A JP S6096012 A JPS6096012 A JP S6096012A JP 20408083 A JP20408083 A JP 20408083A JP 20408083 A JP20408083 A JP 20408083A JP S6096012 A JPS6096012 A JP S6096012A
- Authority
- JP
- Japan
- Prior art keywords
- current
- emitter
- resistance
- voltage
- dynamic range
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
- H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0035—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements
- H03G1/007—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements using FET type devices
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、バイポーラトランジスタおよび電界効果型ト
ランジスタよりなる可変利得増幅器に関するものであり
、音響および産業分野に利用可能性を有する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a variable gain amplifier made of bipolar transistors and field effect transistors, and has applicability in the acoustic and industrial fields.
従来例の構成とその問題点
第1図に電流を可変として増幅率を変える従来の可変利
得増幅回路を示す。第1図において、Q1iQ2はNP
N)・ランジスタであり、それぞれベース側を入力端子
v1.v2とし、エミッタ側は、抵抗R3,R4に接続
され、抵抗R3,R4間にAGC(自動利得制御)検出
器1および定電流源2が接続される。一方、コレクタ側
は、抵抗R1,R2を介して電源■。0 に接続され、
且つ出力端子V。1゜vo2 となっている。Conventional Structure and Problems Therein FIG. 1 shows a conventional variable gain amplifier circuit that changes the amplification factor by making the current variable. In Figure 1, Q1iQ2 is NP
N) and transistors, each with its base side connected to the input terminal v1. v2, and the emitter side is connected to resistors R3 and R4, and an AGC (automatic gain control) detector 1 and a constant current source 2 are connected between the resistors R3 and R4. On the other hand, the collector side is connected to the power supply (2) via resistors R1 and R2. connected to 0,
and output terminal V. 1°vo2.
図において、工。はトランジスタQ1.Q2を流れる電
流I、、I2の和であり、ICは定電流源の電流、IA
GcはAGC検出器1からの信号電流である。第1図に
示すトランジスタQ1.Q2により構成される差動増幅
回路、の利得Gは次式のように表わされる。In the figure, Eng. is transistor Q1. It is the sum of the currents I, , I2 flowing through Q2, and IC is the current of the constant current source, IA
Gc is a signal current from the AGC detector 1. Transistor Q1 shown in FIG. The gain G of the differential amplifier circuit constituted by Q2 is expressed as follows.
G=2gm RC−(1)
但し、R1−R2=Ro、R3−R4−RE とし、捷
だ、gmは差動増幅器における相互コンダクタンスであ
る。ここで、gmは次式で表わされる。G=2gm RC-(1) However, R1-R2=Ro, R3-R4-RE, and gm is the mutual conductance in the differential amplifier. Here, gm is expressed by the following formula.
但し、VTはしきい値電圧、■。=Ic−工AGc。However, VT is the threshold voltage, ■. =Ic-AGc.
ところで、(1)式の利得を、従来方法で可変にするに
は、(2)式の電流工。を可変にしなければならないの
で、出力端子の直流電圧が利得により、変化し、1だA
GC電流が大きくなるという欠点を有する。By the way, in order to make the gain in equation (1) variable using the conventional method, change the current factor in equation (2). Since it has to be made variable, the DC voltage at the output terminal changes depending on the gain, and the
This has the disadvantage that the GC current increases.
即ち、第1図に示す可変利得回路において、AGC電流
を変化させて、利得を−20dB変化させるには、(2
)式で表わされるqmを1/1o倍にしなければならな
い。そのときの電流工。の値をIx とすると、
従って、
RE=5oOQ、vT−25,8mV、工。=200μ
AとするとIx=7.29μAとなり、工AGCは、I
AGC= I C−I != 192 、7 (μA
〕となり、定電流源2には、この電流が加わり、変化前
の約2倍の電流を流さねばならなくなる。That is, in the variable gain circuit shown in Fig. 1, in order to change the gain by -20 dB by changing the AGC current, (2
) must be multiplied by 1/1o. Electrician at that time. If the value of is Ix, then RE=5oOQ, vT-25, 8mV, engineering. =200μ
If A, then Ix = 7.29μA, and the engineering AGC is I
AGC=IC-I! = 192, 7 (μA
], this current is added to the constant current source 2, and the current must flow approximately twice as much as before the change.
発明の目的
本発明は、前述のような従来の欠点を除去するものでア
リ、NPN )ランジスタよりなる差動増幅器のエミッ
タ抵抗を可変にして、可変利得増幅器を構成しようとす
るものである。OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned drawbacks of the prior art, and attempts to construct a variable gain amplifier by making the emitter resistance of a differential amplifier made of NPN transistors variable.
発明の構成
本発明は、差動対画トランジスタの各コレクタを、それ
ぞれに負荷を介して、電源に接続し、かつ、各エミッタ
を、それぞれに電界効果トランジスタを介して、単一電
流源に接続すると共に、前記電界効果トランジスタの各
ゲートを自動利得制御信号源に接続した可変利得増幅器
であり、これにより、差動増幅回路の電流源電流を変動
させずに、したがって、出力端子の直流電圧レベルを変
えずに可変利得増幅器出力が得られる。Structure of the Invention The present invention provides a method in which each collector of a differential pair transistor is connected to a power supply through a load, and each emitter is connected to a single current source through a field effect transistor. and a variable gain amplifier in which each gate of the field effect transistor is connected to an automatic gain control signal source, which allows the current source current of the differential amplifier circuit to remain unchanged, and thus to control the DC voltage level at the output terminal. Variable gain amplifier output can be obtained without changing .
実施例の説明
第2図は本発明実施例回路図であり、AGC回路3の信
号により、Nチャンネル接合型電界効果トランジスタ(
N−JFETと略す)Q3.Q4の抵抗値を変化させ、
出力電圧利得を得るものである。ここで、N−lFET
の電流電圧特性を第3図に示す。横軸にドレイン・ソー
ス電圧(VDs)をとシ縦軸にドレイン・ソース電流(
Ins)をとると、ドレイン・ソース電圧■Ds の増
加と共にドレイン・ソース電流よりsは増加し、一定電
流値で飽和する、ゲート電圧vG工 を増加させること
により、電流飽和値は増加する。この原理によりN−J
FETの抵抗変化を用い、例えば、−20dBの利得変
化させるには、(2)式のqmを1/10倍にしなけれ
ばならない。N−TFETの可変抵抗の値をREx と
して、その値をめると、)
とナル。各パラメータを、Io=2ooμA、vT=2
5.8mV 、RE:600Ω として、可変抵抗値R
Exをめると
REx=73220
と得られるので、この値はN−TFETを用いて実現す
ることができる。DESCRIPTION OF EMBODIMENTS FIG. 2 is a circuit diagram of an embodiment of the present invention, in which an N-channel junction field effect transistor (
(abbreviated as N-JFET)Q3. By changing the resistance value of Q4,
This is to obtain output voltage gain. Here, N-lFET
Figure 3 shows the current-voltage characteristics of . The horizontal axis represents the drain-source voltage (VDs), and the vertical axis represents the drain-source current (VDs).
Ins), as the drain-source voltage Ds increases, the drain-source current s increases and saturates at a constant current value.By increasing the gate voltage vG, the current saturation value increases. By this principle, N-J
In order to change the gain by, for example, -20 dB using a change in the resistance of the FET, qm in equation (2) must be multiplied by 1/10. Letting the value of the variable resistance of the N-TFET be REx, and subtracting that value, we get ) and null. Each parameter is Io=2ooμA, vT=2
5.8mV, RE: 600Ω, variable resistance value R
Subtracting Ex gives REx=73220, so this value can be realized using an N-TFET.
次に、ダイナミックレンジは、エミッタ電流”EE1エ
ミッタ抵抗REに比例するので、
D(ダイナミックレンジ) oc I E E REと
表現できる。Next, since the dynamic range is proportional to the emitter current "EE1" and the emitter resistance RE, it can be expressed as D (dynamic range) oc I E E RE.
従来のエミッタ電流を減らしてAGCをかける場合は、
ダイナミックレンジは小さくなり、本発明のエミッタ抵
抗を増加させてAGCをかける場合はダイナミックレン
ジが広がる。例えば、前述のように、−20dBのAG
Cをかける場合で比1文すると、ダイナミックレンジD
f(+、次の、にうになる。1
1)ACACがかか−、−(:l/+ない」易自D=(
IEERE) ・K
2)IEE 変化によるAGC
D=(2(3工EE)RE・K
3)REによるAGC
D′−(IEE−コτ「RE) K
、’、DI/′D= 418.4倍
即ち、エミッタ抵抗REを変化させる方法が、エミッタ
電流工EE を変化させるよシも、ダイナミックレンジ
が広い。第4図a、bに、この結果を示す。第4図aが
従来例による場合、bが本発明による場合で、I、、I
2.ΔVの略目盛単位は同一である。第4図かられかる
ように、同じゲインに対して大入力の範囲までリニヤな
増幅が可能である。When applying AGC by reducing the conventional emitter current,
The dynamic range becomes smaller, and when AGC is applied by increasing the emitter resistance of the present invention, the dynamic range becomes wider. For example, as mentioned above, -20 dB AG
When multiplying by C, the dynamic range is D.
f(+, next, becomes. 1 1) ACAC is active -, -(:l/+ is not" easy own D = (
IEERE) ・K 2) AGC due to IEE change D = (2 (3 engineering EE) RE・K 3) AGC due to RE D'-(IEE-koτ'RE) K, ', DI/'D = 418.4 In other words, the method of changing the emitter resistance RE has a wider dynamic range than the method of changing the emitter current EE.The results are shown in Figures 4a and b.Figure 4a shows the conventional example. ,b according to the present invention, I, ,I
2. The approximately scale unit of ΔV is the same. As can be seen from FIG. 4, linear amplification is possible up to a large input range for the same gain.
なお、実施例では、N−JFETによって可変抵抗部分
を実現しだが、これは、MO8型電界効果トランジスタ
によっても同様な作用を実現することができる。In the embodiment, the variable resistance portion was realized by an N-JFET, but the same effect can be realized by an MO8 type field effect transistor.
発明の効果
本発明によれば、
1、エミッタ抵抗を可変にしているだめ、ダイナミック
レンジが広がる、従って大入力に対してもリニヤな出力
が得られる。Effects of the Invention According to the present invention: 1. Since the emitter resistance is made variable, the dynamic range is widened, and therefore a linear output can be obtained even in response to a large input.
2、差動増幅回路の電流を変化させていないため出力の
直流電圧レベルの変化がなく、多段に゛する時の設計が
容易である。2. Since the current of the differential amplifier circuit is not changed, there is no change in the output DC voltage level, making it easy to design when using multiple stages.
3、回路全体の電流バスの変化がない。3. There is no change in the current bus throughout the circuit.
などのすぐれた効果が得られる。Excellent effects such as
第1図は従来例の可変利得増幅器、第2図は本発明実施
例の可変利得増幅器、第3図は本発明実施例に使用した
JFETの工・V特性図、第4図a、bは、従来例およ
び本発明実施例の各ダイナミックレンジ特性図である。
Ql、Q2・・・・・NPN)ランジスタ、R1,R2
・°・・・・・抵抗、Q3.Q4.、、=・N−J F
ET、Vl、V2・・・・・入力部、vcc・・・・・
電源、4− ・定電流源、3・・・・・AGC検出回路
部、■o1.■。2・・・・出力部。
代理人の氏名 弁理士 中 尾 敏 男 ほか1毛彫
2 図
第3図
II4図Fig. 1 shows a conventional variable gain amplifier, Fig. 2 shows a variable gain amplifier according to an embodiment of the present invention, Fig. 3 shows a power-V characteristic diagram of the JFET used in an embodiment of the present invention, and Fig. 4 a and b show FIG. 2 is a dynamic range characteristic diagram of a conventional example and an example of the present invention. Ql, Q2...NPN) transistor, R1, R2
・°・・・Resistance, Q3. Q4. ,,=・N−J F
ET, Vl, V2...input section, vcc...
Power supply, 4- ・Constant current source, 3...AGC detection circuit section, ■o1. ■. 2... Output section. Name of agent: Patent attorney Toshio Nakao and 1 other person
2 Figure 3 Figure II Figure 4
Claims (2)
に負荷を介して、電源に接続し、かつ、各エミッタを、
それぞれに電界効果トランジスタを介して、単一電流源
に接続すると共に、前記電界効果トランジスタの各ゲー
トを自動利得制御信号源に接続した可変利得増幅器。(1) Connect each collector of the differential picture transistor to the power supply through a load, and connect each emitter to the power supply.
A variable gain amplifier, each connected to a single current source through a field effect transistor, and each gate of said field effect transistor connected to an automatic gain control signal source.
効果トランジスタもしくは同MO3型電界効果トランジ
スタから選定された特許請求の範囲第1項に記載の可変
利得増幅器。(2) The variable gain amplifier according to claim 1, wherein the K field effect transistor is selected from an N channel junction field effect transistor or an MO3 field effect transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20408083A JPS6096012A (en) | 1983-10-31 | 1983-10-31 | Variable gain amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20408083A JPS6096012A (en) | 1983-10-31 | 1983-10-31 | Variable gain amplifier |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6096012A true JPS6096012A (en) | 1985-05-29 |
Family
ID=16484443
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20408083A Pending JPS6096012A (en) | 1983-10-31 | 1983-10-31 | Variable gain amplifier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6096012A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63178611A (en) * | 1987-01-20 | 1988-07-22 | Toshiba Corp | Gain control circuit |
JPS63284914A (en) * | 1987-05-15 | 1988-11-22 | Nec Corp | Differential type agc circuit |
EP0632583A1 (en) * | 1993-06-30 | 1995-01-04 | STMicroelectronics S.r.l. | Variable gain amplifier |
WO2000021205A1 (en) * | 1998-10-07 | 2000-04-13 | Microtune, Inc. | Highly linear variable-gain low noise amplifier |
US6771124B1 (en) | 2000-08-04 | 2004-08-03 | Microtune (Texas), L.P. | System and method for low-noise amplifier with a high frequency response |
-
1983
- 1983-10-31 JP JP20408083A patent/JPS6096012A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63178611A (en) * | 1987-01-20 | 1988-07-22 | Toshiba Corp | Gain control circuit |
JPH0551206B2 (en) * | 1987-01-20 | 1993-08-02 | Tokyo Shibaura Electric Co | |
JPS63284914A (en) * | 1987-05-15 | 1988-11-22 | Nec Corp | Differential type agc circuit |
EP0632583A1 (en) * | 1993-06-30 | 1995-01-04 | STMicroelectronics S.r.l. | Variable gain amplifier |
WO2000021205A1 (en) * | 1998-10-07 | 2000-04-13 | Microtune, Inc. | Highly linear variable-gain low noise amplifier |
US6771124B1 (en) | 2000-08-04 | 2004-08-03 | Microtune (Texas), L.P. | System and method for low-noise amplifier with a high frequency response |
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